[RFC,v2,17/19] tune-riscv.inc: clarify zifencei comment

Message ID	20260930-riscv-tuning-rework-v2-17-9e29f3531d0e@baylibre.com
State	Under Review
Headers	show Return-Path: <david.partain@est.tech> ip: 74.125.230.171, mailfrom: tgamblin@baylibre.com) From: "Trevor Gamblin" <tgamblin@baylibre.com> Date: Wed, 30 Sep 2026 12:38:21 -0400 Subject: [OE-core][PATCH RFC v2 17/19] tune-riscv.inc: clarify zifencei comment MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-17-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin <tgamblin@baylibre.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit
Series	riscv: add new ISA extensions and profile support \| expand [RFC,v2,00/19] riscv: add new ISA extensions and profile support [RFC,v2,01/19] tune-riscv: be explicit about riscv32gc, riscv64gc defaults [RFC,v2,02/19] tune-riscv.inc: add 'riscv64gcv' tune [RFC,v2,03/19] arch-riscv.inc: add missing RVA20 extensions [RFC,v2,04/19] meta/lib/oe/tune.py: support profile strings, add rva20u64 [RFC,v2,05/19] tune-riscv.inc: add rva20u64 to AVAILTUNES [RFC,v2,06/19] arch-riscv.inc: add rva22u64 extensions [RFC,v2,07/19] meta/lib/oe/tune.py: add rva22u64 profile [RFC,v2,08/19] tune-riscv.inc: add rva22u64 to AVAILTUNES [RFC,v2,09/19] arch-riscv.inc: add rva23u64 extensions [RFC,v2,10/19] meta/lib/oe/tune.py: add rva23u64 profile [RFC,v2,11/19] tune-riscv.inc: add rva23u64 to AVAILTUNES [RFC,v2,12/19] meta/lib/oe/tune.py: add riscv_pkgarch() [RFC,v2,13/19] arch-riscv.inc: rename TUNE_RISCV_PKGARCH -> TUNE_RISCV_PKGARCH_EXACT in assignments [RFC,v2,14/19] tune.py: add implied tuning logic [RFC,v2,15/19] tune.py: add vector extensions to RISCV_IMPLIED [RFC,v2,16/19] tune-riscv.inc: add RISCV_PKGARCH vars, set PACKAGE_EXTRA_ARCHS [RFC,v2,17/19] tune-riscv.inc: clarify zifencei comment [RFC,v2,18/19] selftest: oelib: add tune.py [RFC,v2,19/19] selftest: cases: add riscvtune.py

Message ID

20260930-riscv-tuning-rework-v2-17-9e29f3531d0e@baylibre.com

State

Under Review

Headers

From: "Trevor Gamblin" <tgamblin@baylibre.com>
Date: Wed, 30 Sep 2026 12:38:21 -0400
Subject: [OE-core][PATCH RFC v2 17/19] tune-riscv.inc: clarify zifencei
 comment
MIME-Version: 1.0
Message-Id: <20260930-riscv-tuning-rework-v2-17-9e29f3531d0e@baylibre.com>
References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com>
In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com>
To: openembedded-core@lists.openembedded.org
Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org,
 Trevor Gamblin <tgamblin@baylibre.com>
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit

Series

riscv: add new ISA extensions and profile support | expand

Commit Message

Trevor Gamblin Sept. 30, 2026, 4:38 p.m. UTC

Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
 meta/conf/machine/include/riscv/tune-riscv.inc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index b31d903172..76c7dad713 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -15,7 +15,8 @@  RISCV_PKGARCH_RVA22 = "rva22u64_zifencei"
 # (they lack the 'v' extension) but rva23 is, so split it out for comprehension.
 RISCV_PKGARCH_GCV = "riscv64imafdcv_zicsr_zifencei"
 
-# Linux kernel requires it, so add it on top of the profile's extensions.
+# zifencei isn't a mandatory extension in these profiles, but the Linux
+# kernel requires it, so add it on top of the profile's extensions.
 TUNE_FEATURES:tune-rva20u64 := "${@oe.tune.riscv_isa_to_tune("rva20u64")} zifencei"
 PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${RISCV_PKGARCH_GC} ${TUNE_RISCV_PKGARCH}"

[RFC,v2,17/19] tune-riscv.inc: clarify zifencei comment

Commit Message

Patch