From patchwork Wed Sep 30 16:38:05 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 99730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A7D0CA5FCB for ; Wed, 30 Sep 2026 16:41:54 +0000 (UTC) Received: from mail-qv2-f43.google.com (mail-qv2-f43.google.com [74.125.230.171]) by mx.groups.io with SMTP id smtpd.msgproc02-g2.18021.1790786298218843201 for ; Wed, 30 Sep 2026 09:38:18 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@baylibre.com header.s=google header.b=PmbwhltI; spf=pass (domain: baylibre.com, ip: 74.125.230.171, mailfrom: tgamblin@baylibre.com) Received: by mail-qv2-f43.google.com with SMTP id 6a1803df08f44-91434eba57fso42248886d6.2 for ; Wed, 30 Sep 2026 09:38:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1790786297; x=1791391097; darn=lists.openembedded.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=aPWiXpWriIzgM/Y5uFItMkp+RgYPzuuI8OBR9yO4Mxg=; b=PmbwhltIm/3kxtw2c0WjGbBYRV/xAIx4mGRnx0s0x17Vv+pM7PBwp8lQiZ5rRttjTy BgV31mgunEe8fOWpM9oasdP5VRe6NDYvydNkHkjsbRBqQqv12DELrhu/14m9z1DaimmA tkIdxcc0YfUSdaGQDSKnPBkID9FUh6baI2HXJpvZV9sx5NJ24bnbdupF6R67+c58qc/u +bnDl01h1NOHIUqumJAt/9zq67jBlRO/bbaoRfIlrBJVO5QLz1Tu0qGpJUu9up+Gq1wg YwshTtlShkSLlQGK4aZLYV2j5DFLIKkgHIGOSaDE2joqWoiwIrK8oeOvtJQHTI2rCCmk Wzrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790786297; x=1791391097; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=aPWiXpWriIzgM/Y5uFItMkp+RgYPzuuI8OBR9yO4Mxg=; b=xUOrmzFtog/aZD2kaRZJDpbfFkgLOS3Cf02XCu2brFLKSV6oCUcpG8Jna/xkAIcSo4 l5UJtoKgCtMkpiv8aPvCgtDzqtt0TTH9vK3eO6g2bLct2vUOGtZ8j7piEU5SjYuL2eRn XiE5WFEhHecUJFx7036gDotgBE18VHyYhPQ5S4qGZWHiVMdzct4hO61+4AbRh3r5FQ5X uvbxAHc7lF85f5U5MPo5jQiySZ7AKGTH8WXot7ucd94zO+dId/2ZrrzB3NHxKAENnujt Mpzu6my1AsLMmcfOr3i7g1R6NGPCLeOR4xm+uz9qh0awXHPRX6jGEodZPmOLeieQ22lz z1Kw== X-Gm-Message-State: AFuF++lnacSXU4w+a0js3EqdNSbn+x3PRUjUnauOC7Nl4xRSf3HV9bum CJX4HHKMVzNlP/Zw+42hY5Hf7abZ5lDJyL9BESZ3NX4kb1sS/lxCXSCuSco+019rWjw= X-Gm-Gg: AYBFou24KHI99z2NpobltTrGOXIVEq5CpZ/yV5NPJE3XXT2SQ2pOXB27342JJvfdiyK gYugW/BFVAyX0KIIa+4FOqhxlyuZRb4TT5u5Yy+Uzb8ZKRdo6wCQnNFINOz8YXNL8X9BiDT5zyh LIyjc9Ow9scSpUFvEHjRfEDrxdBa9B6m6tXN6qYwFa551aS5C2NBd3nc5WT9Zw27czZUHYQPXan GmqF2JMk6n/4wNDToBiHy3P6LJvoyMzUw/CGSg/Na1MPQ/6GtOSuysgjR+dEYvrmM1tJrr7PBLn AQ6kXYTJDUsuKwLR/BYfvtcDfYSHXuYydmSKt5ZbtScD5fpnPdkXL0d4WONBEgUnF2eqDBaCNUR ir+U4/f3hemUrl8nCrb/EkMHFt1zgizto7bsvZ+RN8T14VRWtQLeFrpMYdl5iipav//jPUS8boC JSgqW3f02V+pKzdJYdHpBbYzcLO98hyRrtvUcSELv+PTyKVv+rJ0tzvc3EX/Cg8UyDq4q+dJywu R4TR5/3P0i7VGFK4DGmfmO8fMFFMVn3itEbet3eghg= X-Received: by 2002:a05:6214:4489:b0:914:56b2:89a2 with SMTP id 6a1803df08f44-917a0bd9a52mr29857326d6.20.1790786296995; Wed, 30 Sep 2026 09:38:16 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:16 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:05 -0400 Subject: [OE-core][PATCH RFC v2 01/19] tune-riscv: be explicit about riscv32gc, riscv64gc defaults MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-1-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:41:54 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246981 The string 'riscv64' is a generic descriptor for the 64-bit RISC-V ISA, and can mean different things under different contexts. In the case of tune-riscv.inc, it has served as an alias for the 'riscv64gc' profile which packages are typically built against, resulting in the following output (from a typical bitbake preamble): |TUNE_FEATURES = "rv 64 i m a f d c zicsr zifencei" Modify tune-riscv.inc to avoid overloading the 'riscv64' string in this way, instead setting DEFAULTTUNE to 'riscv64gc', and changing other occurrences to match. TUNE_FEATURES remains the same under this adjustment, but the .inc file is clearer which profile is being targeted. Do the same for riscv32 -> riscv32gc. In this case, we also need to update qemuriscv32.conf, since it sets DEFAULTTUNE to override the default. Also add TUNE_FEATURE aliases for the old riscv32 and riscv64 names so that other layers using them don't break. Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/tune-riscv.inc | 18 ++++++++++++------ meta/conf/machine/qemuriscv32.conf | 2 +- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index 12c1125c8b..8a14971d5f 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -1,15 +1,21 @@ require conf/machine/include/riscv/arch-riscv.inc -DEFAULTTUNE ?= "riscv64" +DEFAULTTUNE ?= "riscv64gc" -AVAILTUNES += "riscv64 riscv32 riscv64nc riscv64nf riscv32nf" +AVAILTUNES += "riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf" # Default -TUNE_FEATURES:tune-riscv64 := "${@oe.tune.riscv_isa_to_tune("rv64gc")}" -PACKAGE_EXTRA_ARCHS:tune-riscv64 = "${TUNE_RISCV_PKGARCH}" +TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}" +PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}" -TUNE_FEATURES:tune-riscv32 := "${@oe.tune.riscv_isa_to_tune("rv32gc")}" -PACKAGE_EXTRA_ARCHS:tune-riscv32 = "${TUNE_RISCV_PKGARCH}" +TUNE_FEATURES:tune-riscv32gc := "${@oe.tune.riscv_isa_to_tune("rv32gc")}" +PACKAGE_EXTRA_ARCHS:tune-riscv32gc = "${TUNE_RISCV_PKGARCH}" + +# Compatibility aliases so that layers using old tunes don't break +TUNE_FEATURES:tune-riscv64 := "${TUNE_FEATURES:tune-riscv64gc}" +PACKAGE_EXTRA_ARCHS:tune-riscv64 = "${PACKAGE_EXTRA_ARCHS:tune-riscv64gc}" +TUNE_FEATURES:tune-riscv32 := "${TUNE_FEATURES:tune-riscv32gc}" +PACKAGE_EXTRA_ARCHS:tune-riscv32 = "${PACKAGE_EXTRA_ARCHS:tune-riscv32gc}" # No float TUNE_FEATURES:tune-riscv64nf := "${@oe.tune.riscv_isa_to_tune("rv64imac_zicsr_zifencei")}" diff --git a/meta/conf/machine/qemuriscv32.conf b/meta/conf/machine/qemuriscv32.conf index aff36c28a5..5cb9ba5aa9 100644 --- a/meta/conf/machine/qemuriscv32.conf +++ b/meta/conf/machine/qemuriscv32.conf @@ -2,7 +2,7 @@ #@NAME: generic riscv32 machine #@DESCRIPTION: Machine configuration for running a generic riscv32 -DEFAULTTUNE ?= "riscv32" +DEFAULTTUNE ?= "riscv32gc" require conf/machine/include/riscv/qemuriscv.inc From patchwork Wed Sep 30 16:38:06 2026 Content-Type: text/plain; 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Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/tune-riscv.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index 8a14971d5f..ed71dc06ba 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -2,12 +2,15 @@ require conf/machine/include/riscv/arch-riscv.inc DEFAULTTUNE ?= "riscv64gc" -AVAILTUNES += "riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf" +AVAILTUNES += "riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf" # Default TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}" PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}" +TUNE_FEATURES:tune-riscv64gcv := "${@oe.tune.riscv_isa_to_tune("rv64gcv")}" +PACKAGE_EXTRA_ARCHS:tune-riscv64gcv = "${TUNE_RISCV_PKGARCH}" + TUNE_FEATURES:tune-riscv32gc := "${@oe.tune.riscv_isa_to_tune("rv32gc")}" PACKAGE_EXTRA_ARCHS:tune-riscv32gc = "${TUNE_RISCV_PKGARCH}" From patchwork Wed Sep 30 16:38:07 2026 Content-Type: text/plain; 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Wed, 30 Sep 2026 09:38:20 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:19 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:07 -0400 Subject: [OE-core][PATCH RFC v2 03/19] arch-riscv.inc: add missing RVA20 extensions MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-3-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:42:04 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246983 There are currently many RISC-V ISA extensions missing from the arch-riscv.inc file, even some which are required by core 'riscv64gc' extensions. For example: |tgamblin@megalith ~/workspace/ypbuilds/poky-qemuriscv64/layers/openembedded-core (master)$ riscv64-linux-gnu-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -Q --help=target | grep rv64 | -march= rv64imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd versus: |TUNE_FEATURES = "rv 64 i m a f d c zicsr zifencei" which is missing zmmul, zaamo, zalrsc, zca, and zcd. There are even more absent when comparing against the official RVA20 spec - passing '-march=rva20u64' to gcc and checking the ISA extension string shows: |tgamblin@alchemist ~ $ riscv64-linux-gnu-gcc -march=rva20u64 -mabi=lp64d -Q --help=target | grep rv64 | -march= rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd Add the following extensions to arch-riscv.inc, along with their conditional inclusions required: - za128rs - zaamo (required by 'a') - zalrsc (required by 'a') - zca (required by 'c') - zcd - ziccamoa - ziccif - zicclsm - ziccrse - zicntr - zmmul (required by 'm') We also need to change the extension ordering in the file, so that they appear in the same order as the compiler expects. Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/arch-riscv.inc | 46 +++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc index 6f9b74974d..0f12059159 100644 --- a/meta/conf/machine/include/riscv/arch-riscv.inc +++ b/meta/conf/machine/include/riscv/arch-riscv.inc @@ -86,14 +86,58 @@ TUNEVALID[zicbom] = "Cache-block management extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}" +TUNEVALID[ziccamoa] = "PMA guarantees for A-extension atomics extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}" + +TUNEVALID[ziccif] = "Patching instructions at run time extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", "_ziccif", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", "_ziccif", "", d)}" + +TUNEVALID[zicclsm] = "Software that assumes misaligned access works extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", "_zicclsm", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", "_zicclsm", "", d)}" + +TUNEVALID[ziccrse] = "Guarantees LR/SC forward progress extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", "_ziccrse", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", "_ziccrse", "", d)}" + +TUNEVALID[zicntr] = "Cycle and instruction counting for profiling extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}" + TUNEVALID[zicsr] = "Control and status register access extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}" -TUNEVALID[zifencei] = "Instruction-fetch fence extension" +TUNEVALID[zifencei] = "Instruction-fetch fence extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" +TUNEVALID[zmmul] = "Cheaper M subset (mul only) extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}" + +TUNEVALID[za128rs] = "Reservation set granularity (128-byte) extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}" + +TUNEVALID[zaamo] = "Atomic read-modify-write memory operations extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}" + +TUNEVALID[zalrsc] = "Extended LR/SC semantics extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}" + +TUNEVALID[zca] = "Compressed base integer ops extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "c zca", "_zca", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", "_zca", "", d)}" + +TUNEVALID[zcd] = "16-bit encodings for 64-bit FP extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}" + TUNEVALID[zba] = "Address bit manipulation extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}" From patchwork Wed Sep 30 16:38:08 2026 Content-Type: text/plain; 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Wed, 30 Sep 2026 09:38:22 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:20 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:08 -0400 Subject: [OE-core][PATCH RFC v2 04/19] meta/lib/oe/tune.py: support profile strings, add rva20u64 MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-4-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:42:14 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246984 Signed-off-by: Trevor Gamblin --- meta/lib/oe/tune.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py index 7fda19430d..fed593e9af 100644 --- a/meta/lib/oe/tune.py +++ b/meta/lib/oe/tune.py @@ -4,16 +4,25 @@ # SPDX-License-Identifier: GPL-2.0-only # +# RISC-V profile name -> equivalent ISA string. These are determined from compiler output, like: +# tgamblin@alchemist ~ $ riscv64-linux-gnu-gcc -march=rva20u64 -mabi=lp64d -Q --help=target | grep rv64 +# -march=rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd +RISCV_PROFILES = { + 'rva20u64': 'rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd', +} + # riscv_isa_to_tune(isa) # # Automatically translate a RISC-V ISA string to TUNE_FEATURES # # Abbreviations, such as rv32g -> rv32imaffd_zicsr_zifencei are supported. # -# Profiles, such as rva22u64, are NOT supported, you must use ISA strings. +# Profiles are supported for the names listed in RISCV_PROFILES. Otherwise, you +# must use ISA strings. # def riscv_isa_to_tune(isa): _isa = isa.lower() + _isa = RISCV_PROFILES.get(_isa, _isa) feature = [] iter = 0 From patchwork Wed Sep 30 16:38:09 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 99734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B54ECA5FC7 for ; Wed, 30 Sep 2026 16:42:24 +0000 (UTC) Received: from mail-qk1-f177.google.com (mail-qk1-f177.google.com [209.85.222.177]) by mx.groups.io with SMTP id smtpd.msgproc01-g2.18096.1790786304743241765 for ; Wed, 30 Sep 2026 09:38:24 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@baylibre.com header.s=google header.b=gZD0hHHA; spf=pass (domain: baylibre.com, ip: 209.85.222.177, mailfrom: tgamblin@baylibre.com) Received: by mail-qk1-f177.google.com with SMTP id af79cd13be357-93c64decd21so144747685a.1 for ; Wed, 30 Sep 2026 09:38:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1790786304; x=1791391104; darn=lists.openembedded.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=QLWvOlAQIW2RRoxfytmeiMBfhASybU2hiKjiK1vjk70=; b=gZD0hHHAdVRtQOV+CKhea7zwi2PuoePV10Atyo22yyPt6cGvzMpRK9O2oZdVQvDniO Bupi5vSvTvO6qh8IE0ihW2C9F7r1XkNzigcIrPFKoDQbundmaAWxgMpCwfB+P+h54Pit 7KOEPS1Wu72ygR/MUbuZQxPnzZ5O4MIOd9DgCRXx21xXuwjRM76naV7EQaS3sa2RwakR HaJihxCTk0bTiDWgAbEXEfYqAdOqCKNxABhrRqvP+8SSknOp/bhU6BZ4TSmZap8fnPB6 /pwz8qGqYK+p0JclFyKtfNMX72pG0xc77zJ0VkciTguYpvrQzMvn1dBtNsOPbeGmbI8a 0hEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790786304; x=1791391104; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=QLWvOlAQIW2RRoxfytmeiMBfhASybU2hiKjiK1vjk70=; b=OvS2rhjy5uuc7kx1Am3LLFCouOjtYIwMkCVLhijmDmZBW3Sy639s5xDtUJ5PWh2RPx 6VipNm1NIIQSAz7S731VMSfesymwCLMwn4Z026puVd74T08b8u756Z1El7XAw1zXFDAy d3vZC3qWpS442/XbdiLuehcD7BJIWoX0JSmM8OiD0ttqqKEhmXLYymtBYVBz1HL+6r07 3NyOmWo0/g8jEPt9TaVGwir50Iv49QYYF5l3DP8hlXVhooWtq/mreIRDyMkPBPPupaym s6M1XyCNU+zAmb/CH1P1sG6H/xe458yajxkM7lQ09z1TURdVnno/CgLzKCszsfWJjMO6 ykyw== X-Gm-Message-State: AFuF++nDVxE4HXOmwDawmJnl4Nfs6h/S8sbZtqdM/rrVyJnSFoDcQ/Ag cpekNWornvtRIDrAfW1JokxDz9SVdIydYgpV8utAvtsXlbSHrA3ottEMtUfyDRdvlj8VkcKmx+h dl2eR X-Gm-Gg: AYBFou2FPUUgJh2N4B1zjsJlGnEmm6r3O5cnt3KViCXnu+RAoh0wXv5KVNvhufres3K kJhA4CcX/zSIMgsIHEIXhdAV6CyiYzRcLxtTxCst8BxJb0jM9UzXNsNjR72MCHN5QonV2fUpYgH YmW+p+XUm5w3VhemLyPVMCN20DHJ3578LsKMxghqLh7jbmAThdrhN5i9V+oVo/2Qne+YuLBmAdf V3JqEtW5BfAzi405w2cWzK006M/0FF4P8TCEBGqwsaW17/QSGhaTeR1EN/bwbHO5K0qy1isGG1C 3K5XsGl/6BoQRJwZlbR3KDydO7QCBCt5W1Mex1JnJ5aBTko8atfcbPMc1+VPV0abqL5zSIp5WId G5NomRDmIsX+1FbOD6Bj8exd/pPWjbalK8GQ2dLNV4EFAOI8DK9ylERVt9RvbeSdgu/Wm9p1Mzd Y2uozeiQwTaZjXlI/oBJi+LDEUrGm2vLT01GiBxx71i8IDt8Ag+RX2/tLIHLWOOJxH6tX92aAFm hYSHwL3rgxyQ8GDOWGUCE8OAJuZ1HMhhUiQ9QOinxA= X-Received: by 2002:a05:620a:3187:b0:93a:2eb:36e2 with SMTP id af79cd13be357-93cb5c7ab21mr31213585a.35.1790786303621; Wed, 30 Sep 2026 09:38:23 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:22 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:09 -0400 Subject: [OE-core][PATCH RFC v2 05/19] tune-riscv.inc: add rva20u64 to AVAILTUNES MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-5-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:42:24 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246985 riscv64gc remains the default for now. Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/tune-riscv.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index ed71dc06ba..80c17ea0b7 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -2,7 +2,12 @@ require conf/machine/include/riscv/arch-riscv.inc DEFAULTTUNE ?= "riscv64gc" -AVAILTUNES += "riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf" +AVAILTUNES += "rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf" + +# zifencei isn't part of these profiles per gcc's -march expansion, but the +# Linux kernel requires it, so add it on top of the profile's extensions. +TUNE_FEATURES:tune-rva20u64 := "${@oe.tune.riscv_isa_to_tune("rva20u64")} zifencei" +PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${TUNE_RISCV_PKGARCH}" # Default TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}" From patchwork Wed Sep 30 16:38:10 2026 Content-Type: text/plain; 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Wed, 30 Sep 2026 09:38:24 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:24 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:10 -0400 Subject: [OE-core][PATCH RFC v2 06/19] arch-riscv.inc: add rva22u64 extensions MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-6-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:42:24 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246986 gcc reports the following extension string for '-march=rva22u64': |tgamblin@megalith ~/workspace/ypbuilds/poky-qemuriscv64/layers/openembedded-core (master)$ riscv64-linux-gnu-gcc -march=rva22u64 -mabi=lp64d -Q --help=target | grep rv64 | -march= rv64imafdcb_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zihintpause_zmmul_za64rs_zaamo_zalrsc_zfhmin_zca_zcd_zba_zbb_zbs_zkt Add the following extensions needed to complete the profile: - za64rs - zfhmin - zic64b - zicbop - zicboz - zihintpause - zkt Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/arch-riscv.inc | 28 ++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc index 0f12059159..352d6bd878 100644 --- a/meta/conf/machine/include/riscv/arch-riscv.inc +++ b/meta/conf/machine/include/riscv/arch-riscv.inc @@ -82,10 +82,22 @@ TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}" # Now the special Z extensions +TUNEVALID[zic64b] = "Cache block size is 64 bytes extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zic64b", "_zic64b", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zic64b", "_zic64b", "", d)}" + TUNEVALID[zicbom] = "Cache-block management extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}" +TUNEVALID[zicbop] = "Cache-block prefetching extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbop", "_zicbop", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbop", "_zicbop", "", d)}" + +TUNEVALID[zicboz] = "Cache-block zeroing extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicboz", "_zicboz", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicboz", "_zicboz", "", d)}" + TUNEVALID[ziccamoa] = "PMA guarantees for A-extension atomics extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}" @@ -114,6 +126,10 @@ TUNEVALID[zifencei] = "Instruction-fetch fence extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" +TUNEVALID[zihintpause] = "Pause hint extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}" + TUNEVALID[zmmul] = "Cheaper M subset (mul only) extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}" @@ -122,6 +138,10 @@ TUNEVALID[za128rs] = "Reservation set granularity (128-byte) extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}" +TUNEVALID[za64rs] = "Reservation set size of at most 64 bytes extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za64rs", "_za64rs", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za64rs", "_za64rs", "", d)}" + TUNEVALID[zaamo] = "Atomic read-modify-write memory operations extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}" @@ -130,6 +150,10 @@ TUNEVALID[zalrsc] = "Extended LR/SC semantics extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}" +TUNEVALID[zfhmin] = "Minimal half-precision floating point extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}" + TUNEVALID[zca] = "Compressed base integer ops extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "c zca", "_zca", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", "_zca", "", d)}" @@ -154,6 +178,10 @@ TUNEVALID[zbs] = "Single-bit manipulation extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}" +TUNEVALID[zkt] = "Data-independent execution latency extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}" + # Construct TUNE_CCARGS # This should result in a CCARG similar to: # -march=rv32imac -mabi=ilp32 From patchwork Wed Sep 30 16:38:11 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 99736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62DF8CA5FC7 for ; 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Wed, 30 Sep 2026 09:38:26 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:25 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:11 -0400 Subject: [OE-core][PATCH RFC v2 07/19] meta/lib/oe/tune.py: add rva22u64 profile MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-7-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:42:34 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246987 Signed-off-by: Trevor Gamblin --- meta/lib/oe/tune.py | 1 + 1 file changed, 1 insertion(+) diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py index fed593e9af..8827d68a23 100644 --- a/meta/lib/oe/tune.py +++ b/meta/lib/oe/tune.py @@ -9,6 +9,7 @@ # -march=rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd RISCV_PROFILES = { 'rva20u64': 'rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd', + 'rva22u64': 'rv64imafdcb_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zihintpause_zmmul_za64rs_zaamo_zalrsc_zfhmin_zca_zcd_zba_zbb_zbs_zkt', } # riscv_isa_to_tune(isa) From patchwork Wed Sep 30 16:38:12 2026 Content-Type: text/plain; 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Wed, 30 Sep 2026 09:38:27 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:26 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:12 -0400 Subject: [OE-core][PATCH RFC v2 08/19] tune-riscv.inc: add rva22u64 to AVAILTUNES MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-8-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:42:35 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246988 Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/tune-riscv.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index 80c17ea0b7..e3f3897978 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -2,13 +2,16 @@ require conf/machine/include/riscv/arch-riscv.inc DEFAULTTUNE ?= "riscv64gc" -AVAILTUNES += "rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf" +AVAILTUNES += "rva22u64 rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf" # zifencei isn't part of these profiles per gcc's -march expansion, but the # Linux kernel requires it, so add it on top of the profile's extensions. TUNE_FEATURES:tune-rva20u64 := "${@oe.tune.riscv_isa_to_tune("rva20u64")} zifencei" PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${TUNE_RISCV_PKGARCH}" +TUNE_FEATURES:tune-rva22u64 := "${@oe.tune.riscv_isa_to_tune("rva22u64")} zifencei" +PACKAGE_EXTRA_ARCHS:tune-rva22u64 = "${TUNE_RISCV_PKGARCH}" + # Default TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}" PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}" From patchwork Wed Sep 30 16:38:13 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 99738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BDFCCA5FC7 for ; Wed, 30 Sep 2026 16:42:44 +0000 (UTC) Received: from mail-qv2-f42.google.com (mail-qv2-f42.google.com [74.125.230.170]) by mx.groups.io with SMTP id smtpd.msgproc02-g2.18028.1790786309899128734 for ; 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Wed, 30 Sep 2026 09:38:28 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:27 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:13 -0400 Subject: [OE-core][PATCH RFC v2 09/19] arch-riscv.inc: add rva23u64 extensions MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-9-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:42:44 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246989 gcc reports the following extension string for '-march=rva23u64': |tgamblin@megalith ~/workspace/ypbuilds/poky-qemuriscv64/layers/openembedded-core (master)$ riscv64-linux-gnu-gcc -march=rva23u64 -mabi=lp64d -Q --help=target | grep rv64 | -march= rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_z Add the following extensions to complete the profile: - zawrs - zcb - zcmop - zfa - zicond - zihintntl - zihpm - zimop - zvbb - zve32f - zve32x - zve64d - zve64f - zve64x - zvfhmin - zvkb - zvkt - zvl32b - zvl64b - zvl128b - supm Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/arch-riscv.inc | 84 ++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc index 352d6bd878..aa5c430eba 100644 --- a/meta/conf/machine/include/riscv/arch-riscv.inc +++ b/meta/conf/machine/include/riscv/arch-riscv.inc @@ -118,6 +118,10 @@ TUNEVALID[zicntr] = "Cycle and instruction counting for profiling extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}" +TUNEVALID[zicond] = "Conditional zeroing operations extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicond", "_zicond", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicond", "_zicond", "", d)}" + TUNEVALID[zicsr] = "Control and status register access extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}" @@ -126,10 +130,22 @@ TUNEVALID[zifencei] = "Instruction-fetch fence extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" +TUNEVALID[zihintntl] = "Non-temporal locality hints extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintntl", "_zihintntl", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintntl", "_zihintntl", "", d)}" + TUNEVALID[zihintpause] = "Pause hint extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}" +TUNEVALID[zihpm] = "Hardware performance counters extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihpm", "_zihpm", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihpm", "_zihpm", "", d)}" + +TUNEVALID[zimop] = "Hardware performance counters extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zimop", "_zimop", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zimop", "_zimop", "", d)}" + TUNEVALID[zmmul] = "Cheaper M subset (mul only) extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}" @@ -150,6 +166,14 @@ TUNEVALID[zalrsc] = "Extended LR/SC semantics extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}" +TUNEVALID[zawrs] = "Wait-on-reservation-set instructions extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zawrs", "_zawrs", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zawrs", "_zawrs", "", d)}" + +TUNEVALID[zfa] = "Additional floating point instructions extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfa", "_zfa", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfa", "_zfa", "", d)}" + TUNEVALID[zfhmin] = "Minimal half-precision floating point extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}" @@ -158,10 +182,18 @@ TUNEVALID[zca] = "Compressed base integer ops extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "c zca", "_zca", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", "_zca", "", d)}" +TUNEVALID[zcb] = "Extra compressed integer ops extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcb", "_zcb", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcb", "_zcb", "", d)}" + TUNEVALID[zcd] = "16-bit encodings for 64-bit FP extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}" +TUNEVALID[zcmop] = "Compressed may-be-ops extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcmop", "_zcmop", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcmop", "_zcmop", "", d)}" + TUNEVALID[zba] = "Address bit manipulation extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}" @@ -182,6 +214,58 @@ TUNEVALID[zkt] = "Data-independent execution latency extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}" TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}" +TUNEVALID[zvbb] = "Vector basic bit-manipulation extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvbb", "_zvbb", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvbb", "_zvbb", "", d)}" + +TUNEVALID[zve32f] = "Embedded vector computation (32-bit integer, 32-bit FP) extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32f", "_zve32f", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32f", "_zve32f", "", d)}" + +TUNEVALID[zve32x] = "Embedded vector computation (32-bit integer) extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32x", "_zve32x", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32x", "_zve32x", "", d)}" + +TUNEVALID[zve64d] = "Embedded vector computation (64-bit integer, 64-bit FP) extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64d", "_zve64d", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64d", "_zve64d", "", d)}" + +TUNEVALID[zve64f] = "Embedded vector computation (64-bit integer, 32-bit FP) extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64f", "_zve64f", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64f", "_zve64f", "", d)}" + +TUNEVALID[zve64x] = "Embedded vector computation (64-bit integer) extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64x", "_zve64x", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64x", "_zve64x", "", d)}" + +TUNEVALID[zvfhmin] = "Vector half-precision minimal extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvfhmin", "_zvfhmin", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvfhmin", "_zvfhmin", "", d)}" + +TUNEVALID[zvkb] = "Vector cryptography bit-manipulation extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkb", "_zvkb", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkb", "_zvkb", "", d)}" + +TUNEVALID[zvkt] = "Vector data independent execution latency extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkt", "_zvkt", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkt", "_zvkt", "", d)}" + +TUNEVALID[zvl128b] = "Minimum vector length standard extensions (128-bit)." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl128b", "_zvl128b", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl128b", "_zvl128b", "", d)}" + +TUNEVALID[zvl32b] = "Minimum vector length standard extensions (32-bit)." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl32b", "_zvl32b", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl32b", "_zvl32b", "", d)}" + +TUNEVALID[zvl64b] = "Minimum vector length standard extensions (64-bit)." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl64b", "_zvl64b", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl64b", "_zvl64b", "", d)}" + +TUNEVALID[supm] = "User-mode pointer masking extension." +TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "supm", "_supm", "", d)}" +TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "supm", "_supm", "", d)}" + # Construct TUNE_CCARGS # This should result in a CCARG similar to: # -march=rv32imac -mabi=ilp32 From patchwork Wed Sep 30 16:38:14 2026 Content-Type: text/plain; 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Wed, 30 Sep 2026 09:38:29 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:29 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:14 -0400 Subject: [OE-core][PATCH RFC v2 10/19] meta/lib/oe/tune.py: add rva23u64 profile MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-10-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:42:55 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246990 Signed-off-by: Trevor Gamblin --- meta/lib/oe/tune.py | 1 + 1 file changed, 1 insertion(+) diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py index 8827d68a23..7296f39e66 100644 --- a/meta/lib/oe/tune.py +++ b/meta/lib/oe/tune.py @@ -10,6 +10,7 @@ RISCV_PROFILES = { 'rva20u64': 'rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd', 'rva22u64': 'rv64imafdcb_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zihintpause_zmmul_za64rs_zaamo_zalrsc_zfhmin_zca_zcd_zba_zbb_zbs_zkt', + 'rva23u64': 'rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_zvl128b_zvl32b_zvl64b_supm', } # riscv_isa_to_tune(isa) From patchwork Wed Sep 30 16:38:15 2026 Content-Type: text/plain; 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Wed, 30 Sep 2026 09:38:31 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:30 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:15 -0400 Subject: [OE-core][PATCH RFC v2 11/19] tune-riscv.inc: add rva23u64 to AVAILTUNES MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-11-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:42:56 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246991 Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/tune-riscv.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index e3f3897978..500808ef12 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -2,7 +2,7 @@ require conf/machine/include/riscv/arch-riscv.inc DEFAULTTUNE ?= "riscv64gc" -AVAILTUNES += "rva22u64 rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf" +AVAILTUNES += "rva23u64 rva22u64 rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf" # zifencei isn't part of these profiles per gcc's -march expansion, but the # Linux kernel requires it, so add it on top of the profile's extensions. @@ -12,6 +12,9 @@ PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${TUNE_RISCV_PKGARCH}" TUNE_FEATURES:tune-rva22u64 := "${@oe.tune.riscv_isa_to_tune("rva22u64")} zifencei" PACKAGE_EXTRA_ARCHS:tune-rva22u64 = "${TUNE_RISCV_PKGARCH}" +TUNE_FEATURES:tune-rva23u64 := "${@oe.tune.riscv_isa_to_tune("rva23u64")} zifencei" +PACKAGE_EXTRA_ARCHS:tune-rva23u64 = "${TUNE_RISCV_PKGARCH}" + # Default TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}" PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}" From patchwork Wed Sep 30 16:38:16 2026 Content-Type: text/plain; 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Wed, 30 Sep 2026 09:38:33 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:31 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:16 -0400 Subject: [OE-core][PATCH RFC v2 12/19] meta/lib/oe/tune.py: add riscv_pkgarch() MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-12-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:43:05 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246992 Create a new function to help match RISC-V ISA extension combinations against recognized profile strings (e.g. 'rva22u64'), so that we can use simpler patterns for naming things like sstate/build paths. Signed-off-by: Trevor Gamblin --- meta/lib/oe/tune.py | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py index 7296f39e66..0d8e4417e7 100644 --- a/meta/lib/oe/tune.py +++ b/meta/lib/oe/tune.py @@ -90,3 +90,32 @@ def riscv_isa_to_tune(isa): # Eliminate duplicates, but preserve the order feature = list(dict.fromkeys(feature)) return ' '.join(feature) + +# riscv_pkgarch(features, exact_pkgarch) +# +# Prefer a RISCV_PROFILES name (plus any extensions enabled on top of it) as the +# package arch fragment, since otherwise the full ISA extension list will exceed +# what the sstate class can handle. When several profiles match, the one with +# the most extensions is preferred, as it is the more specific/clearer match. +# If there's no clear profile matching the extension list, then fall back to +# exact_pkgarch. +def riscv_pkgarch(features, exact_pkgarch): + if not features: + return exact_pkgarch + + current = set(features.split()) + + best_match = None + best_features = None + for name in RISCV_PROFILES: + profile_features = set(riscv_isa_to_tune(name).split()) + if profile_features.issubset(current): + if best_features is None or len(profile_features) > len(best_features): + best_match = name + best_features = profile_features + + if best_match is None: + return exact_pkgarch + + extra = sorted(current - best_features) + return '_'.join([best_match] + extra) From patchwork Wed Sep 30 16:38:17 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 99742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66128CA5FC7 for ; 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Wed, 30 Sep 2026 09:38:34 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:34 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:17 -0400 Subject: [OE-core][PATCH RFC v2 13/19] arch-riscv.inc: rename TUNE_RISCV_PKGARCH -> TUNE_RISCV_PKGARCH_EXACT in assignments MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-13-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:43:25 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246993 Change the naming convention we use when determining TUNE_RISCV_PKGARCH, so that we have the option of relying on a known RISC-V profile name (e.g. 'rva22u64') as a baseline, rather than always specifying the full ISA extension set. An example from 'bitbake -e opensbi' with 'DEFAULTTUNE = "rva22u64" in conf/local.conf: |TUNE_RISCV_PKGARCH="rva22u64" |# $TUNE_RISCV_PKGARCH_EXACT [48 operations] |TUNE_RISCV_PKGARCH_EXACT="riscv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zihintpause_zmmul_za64rs_zaamo_zalrsc_zfhmin_zca_zcd_zba_zbb_zbs_zkt" Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/arch-riscv.inc | 118 +++++++++++++------------ 1 file changed, 62 insertions(+), 56 deletions(-) diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc index aa5c430eba..c1ccf6bda3 100644 --- a/meta/conf/machine/include/riscv/arch-riscv.inc +++ b/meta/conf/machine/include/riscv/arch-riscv.inc @@ -32,7 +32,7 @@ TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "64", "lp64", "", d)}" # The package arch starts with the canonical arch, but adds some extensions to make # package compatibility clear -TUNE_RISCV_PKGARCH = "${TUNE_RISCV_ARCH}" +TUNE_RISCV_PKGARCH_EXACT = "${TUNE_RISCV_ARCH}" # i, e, or g are defined by gcc, but 'g' refers to 'i' + extensions 'MAFD Zicsr Zifencei' # So 'g' will not be defined here as it is an abbreviation of the expanded version @@ -40,231 +40,237 @@ TUNEVALID[e] = "Reduced register base integer extension" TUNECONFLICTS[e] = "i" TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}" TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}" TUNEVALID[i] = "Base integer extension" TUNECONFLICTS[i] = "e" TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}" # Extensions TUNEVALID[m] = "Integer multiplication and division extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}" TUNEVALID[a] = "Atomic extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}" TUNEVALID[f] = "Single-precision floating-point extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}" TUNEVALID[d] = "Double-precision floating-point extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}" # Only f OR d, but just one TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", bb.utils.contains("TUNE_FEATURES", "f", "f", "", d), d)}" TUNEVALID[c] = "Compressed extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}" TUNEVALID[b] = "Bit Manipulation extension" # Handled below via zba, zbb, zbs # This matches current Linux kernel behavior #TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}" -#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}" +#TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}" TUNEVALID[v] = "Vector operations extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}" # Now the special Z extensions TUNEVALID[zic64b] = "Cache block size is 64 bytes extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zic64b", "_zic64b", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zic64b", "_zic64b", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zic64b", "_zic64b", "", d)}" TUNEVALID[zicbom] = "Cache-block management extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}" TUNEVALID[zicbop] = "Cache-block prefetching extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbop", "_zicbop", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbop", "_zicbop", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbop", "_zicbop", "", d)}" TUNEVALID[zicboz] = "Cache-block zeroing extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicboz", "_zicboz", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicboz", "_zicboz", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicboz", "_zicboz", "", d)}" TUNEVALID[ziccamoa] = "PMA guarantees for A-extension atomics extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "ziccamoa", "_ziccamoa", "", d)}" TUNEVALID[ziccif] = "Patching instructions at run time extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", "_ziccif", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", "_ziccif", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "ziccif", "_ziccif", "", d)}" TUNEVALID[zicclsm] = "Software that assumes misaligned access works extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", "_zicclsm", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", "_zicclsm", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zicclsm", "_zicclsm", "", d)}" TUNEVALID[ziccrse] = "Guarantees LR/SC forward progress extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", "_ziccrse", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", "_ziccrse", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "ziccrse", "_ziccrse", "", d)}" TUNEVALID[zicntr] = "Cycle and instruction counting for profiling extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zicntr", "_zicntr", "", d)}" TUNEVALID[zicond] = "Conditional zeroing operations extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicond", "_zicond", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zicond", "_zicond", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zicond", "_zicond", "", d)}" TUNEVALID[zicsr] = "Control and status register access extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}" TUNEVALID[zifencei] = "Instruction-fetch fence extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}" TUNEVALID[zihintntl] = "Non-temporal locality hints extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintntl", "_zihintntl", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintntl", "_zihintntl", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zihintntl", "_zihintntl", "", d)}" TUNEVALID[zihintpause] = "Pause hint extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zihintpause", "_zihintpause", "", d)}" TUNEVALID[zihpm] = "Hardware performance counters extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihpm", "_zihpm", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zihpm", "_zihpm", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zihpm", "_zihpm", "", d)}" TUNEVALID[zimop] = "Hardware performance counters extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zimop", "_zimop", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zimop", "_zimop", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zimop", "_zimop", "", d)}" TUNEVALID[zmmul] = "Cheaper M subset (mul only) extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "m zmmul", "_zmmul", "", d)}" TUNEVALID[za128rs] = "Reservation set granularity (128-byte) extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "za128rs", "_za128rs", "", d)}" TUNEVALID[za64rs] = "Reservation set size of at most 64 bytes extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za64rs", "_za64rs", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "za64rs", "_za64rs", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "za64rs", "_za64rs", "", d)}" TUNEVALID[zaamo] = "Atomic read-modify-write memory operations extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "a zaamo", "_zaamo", "", d)}" TUNEVALID[zalrsc] = "Extended LR/SC semantics extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "a zalrsc", "_zalrsc", "", d)}" TUNEVALID[zawrs] = "Wait-on-reservation-set instructions extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zawrs", "_zawrs", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zawrs", "_zawrs", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zawrs", "_zawrs", "", d)}" TUNEVALID[zfa] = "Additional floating point instructions extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfa", "_zfa", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfa", "_zfa", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zfa", "_zfa", "", d)}" TUNEVALID[zfhmin] = "Minimal half-precision floating point extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zfhmin", "_zfhmin", "", d)}" TUNEVALID[zca] = "Compressed base integer ops extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "c zca", "_zca", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", "_zca", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "c zca", "_zca", "", d)}" TUNEVALID[zcb] = "Extra compressed integer ops extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcb", "_zcb", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcb", "_zcb", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zcb", "_zcb", "", d)}" TUNEVALID[zcd] = "16-bit encodings for 64-bit FP extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zcd", "_zcd", "", d)}" TUNEVALID[zcmop] = "Compressed may-be-ops extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcmop", "_zcmop", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zcmop", "_zcmop", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains("TUNE_FEATURES", "zcmop", "_zcmop", "", d)}" TUNEVALID[zba] = "Address bit manipulation extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}" TUNEVALID[zbb] = "Basic bit manipulation extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}" TUNEVALID[zbc] = "Carry-less multiplication extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}" TUNEVALID[zbs] = "Single-bit manipulation extension" TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}" TUNEVALID[zkt] = "Data-independent execution latency extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zkt", "_zkt", "", d)}" TUNEVALID[zvbb] = "Vector basic bit-manipulation extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvbb", "_zvbb", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvbb", "_zvbb", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvbb", "_zvbb", "", d)}" TUNEVALID[zve32f] = "Embedded vector computation (32-bit integer, 32-bit FP) extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32f", "_zve32f", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32f", "_zve32f", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32f", "_zve32f", "", d)}" TUNEVALID[zve32x] = "Embedded vector computation (32-bit integer) extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32x", "_zve32x", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32x", "_zve32x", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve32x", "_zve32x", "", d)}" TUNEVALID[zve64d] = "Embedded vector computation (64-bit integer, 64-bit FP) extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64d", "_zve64d", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64d", "_zve64d", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64d", "_zve64d", "", d)}" TUNEVALID[zve64f] = "Embedded vector computation (64-bit integer, 32-bit FP) extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64f", "_zve64f", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64f", "_zve64f", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64f", "_zve64f", "", d)}" TUNEVALID[zve64x] = "Embedded vector computation (64-bit integer) extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64x", "_zve64x", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64x", "_zve64x", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zve64x", "_zve64x", "", d)}" TUNEVALID[zvfhmin] = "Vector half-precision minimal extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvfhmin", "_zvfhmin", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvfhmin", "_zvfhmin", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvfhmin", "_zvfhmin", "", d)}" TUNEVALID[zvkb] = "Vector cryptography bit-manipulation extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkb", "_zvkb", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkb", "_zvkb", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkb", "_zvkb", "", d)}" TUNEVALID[zvkt] = "Vector data independent execution latency extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkt", "_zvkt", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkt", "_zvkt", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvkt", "_zvkt", "", d)}" TUNEVALID[zvl128b] = "Minimum vector length standard extensions (128-bit)." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl128b", "_zvl128b", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl128b", "_zvl128b", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl128b", "_zvl128b", "", d)}" TUNEVALID[zvl32b] = "Minimum vector length standard extensions (32-bit)." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl32b", "_zvl32b", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl32b", "_zvl32b", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl32b", "_zvl32b", "", d)}" TUNEVALID[zvl64b] = "Minimum vector length standard extensions (64-bit)." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl64b", "_zvl64b", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl64b", "_zvl64b", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "zvl64b", "_zvl64b", "", d)}" TUNEVALID[supm] = "User-mode pointer masking extension." TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "supm", "_supm", "", d)}" -TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "supm", "_supm", "", d)}" +TUNE_RISCV_PKGARCH_EXACT .= "${@bb.utils.contains_any("TUNE_FEATURES", "supm", "_supm", "", d)}" + +# Prefer a known RVA profile name (e.g. "rva22u64"), plus any extensions on +# top of the profile (e.g. "rva22u64_zvbb"), over the fully expanded exact +# extension list, when TUNE_FEATURES clearly matches a profile. Falls back +# to TUNE_RISCV_PKGARCH_EXACT for combinations that don't match a profile. +TUNE_RISCV_PKGARCH = "${@oe.tune.riscv_pkgarch(d.getVar('TUNE_FEATURES'), d.getVar('TUNE_RISCV_PKGARCH_EXACT'))}" # Construct TUNE_CCARGS # This should result in a CCARG similar to: From patchwork Wed Sep 30 16:38:18 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 99744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6617CCA5FC7 for ; Wed, 30 Sep 2026 16:43:35 +0000 (UTC) Received: from mail-qk2-f43.google.com (mail-qk2-f43.google.com [74.125.230.235]) by mx.groups.io with SMTP id smtpd.msgproc01-g2.18108.1790786317075220333 for ; Wed, 30 Sep 2026 09:38:37 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@baylibre.com header.s=google header.b=Ma2ghaXG; spf=pass (domain: baylibre.com, ip: 74.125.230.235, mailfrom: tgamblin@baylibre.com) Received: by mail-qk2-f43.google.com with SMTP id af79cd13be357-93ca7aa84e4so77204985a.0 for ; Wed, 30 Sep 2026 09:38:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre.com; s=google; t=1790786316; x=1791391116; darn=lists.openembedded.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Nf0nOZ4HP13InUx48vdmCWSCf07V3OVL/HKwyfwrbaE=; b=Ma2ghaXGW6wOSZxMjdxqwE9zrO02J5v+xNHASLo7suuCTkISjAIOYzFJ/XOVnVm3Sh NhsZUPMyqfh1r7CmtwmFn8a6hcAtAABZFkamL68S+niUyg/vzywA1OWAYDmO776aCaYk XuWHLuAvUJDcwbvCZZ7gfDpkac260tnLynDGuuKwj28MLSHk1EwIqlXunbkwkXnpURkU p2Yue80R5OlmAUN4D2PQZTCB7lMwx6vWokUClbU8gjGxa6HxDoRzBRVAddAXD7C276/B HduZi/D58SCRV3ulqOwkRGdEIE3gk9cJ+Ma7KrFRBu5iUC9iHu4sKSEkHJpkQuOCGxW6 5lWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790786316; x=1791391116; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=Nf0nOZ4HP13InUx48vdmCWSCf07V3OVL/HKwyfwrbaE=; b=FrxRu4lixUbEHu21K4x5lj2x1FFgb5hWrlJYrZv8dfZvLZZjn7fCOQlXqs9hqJsHuT PgwtTvb54tOlB8vX4UR7qscPVOv9rNDUX9nH7OrmDvNr3y6n6cNYL4QMvnfKYwUD1Qhh PLJvLMx2w+ej762Ol9twqSXPcA3aSUiGwNs7pMbJ7hub8GsPLLq3bqDSWcD14KEufu77 u4QE6VBV3/JgER1CwVLw9ivVVZwBHcX9ONtKA/D1D+uPvbuSN/Xe43V7nfbZ7yXloNoQ YaUq7nrCJ9+NJhCEfsx1DT+KigfyCWnbPdLccJgeAF8bge3Sf3uWKe6OV3Zghirn/5NG Rrfw== X-Gm-Message-State: AFuF++lN1bLSpWFrNVmpvLOhjmkhozaM8dkMq/xeKX9Io90toL5UiWVo hOnWuqdFrTLpsCXtvEXMcLoDwaBmGm0X0EgvRpKzjlMUbIpvAD5FJn9vRBegqLwcdhw= X-Gm-Gg: AYBFou2hSEY/tMt94wyk4Nhxb0Dst16E257AIyhucbKAMG0mqJZCS9QkpU9PD7TOB59 uHLKpin0d4931XWN8xmVyy71RPGtRGgPl8wOmgDChvqnI4aVUXLAOvS40ieslq2S1DGsPORJ06D sJcV3DkKPfppa8m73i4O3qTMRwt28lO40YoFtt7XNmaOWNh2CUu7NUZyxJhSX1Heo9UruJ7u3zq VtVOyrTbNtzHQ/tIQNnUcAF9neHzqCS10CMq2rwBBC4EIA/0jXyZJT1YvbVcPjLOScUwgncz6E1 B2VgDW3tGEUY9hMBKMPa7A8IlrCELfxih5dJN41DiLzgpCfsbi0B3UdbLI3MEFjHeshRtDmOUUj bHABPMYrX4pyl3CvvPd80C7HLi9xwha24/SfOEwbQDtPsEslbmgJoPVp4QnWDI+dxFpzQUM+L7n WqHn55pYcrGtWzRD1fgiKjCfY5jlJH8LsrhnkjDh2ulrPrXNMIW3aDtZPcoDhf2jkuy6Ofa+Edl JuVBDFngkgnpFk46eh1ThpG1L8yMDh3f70BgnRkYbY= X-Received: by 2002:a05:620a:172b:b0:93b:c3ac:a94f with SMTP id af79cd13be357-93ca96cef57mr336308585a.37.1790786315883; Wed, 30 Sep 2026 09:38:35 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:35 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:18 -0400 Subject: [OE-core][PATCH RFC v2 14/19] tune.py: add implied tuning logic MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-14-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:43:35 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246994 Add a new function, riscv_implied() and corresponding tuning lists to help with shortening PKGARCH-related variables. There's no need to specify every extension when some (e.g. 'm' implying 'zmmul') are automatic. AI-Generated: Uses Claude Opus 5.5 Signed-off-by: Trevor Gamblin --- meta/lib/oe/tune.py | 59 ++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 5 deletions(-) diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py index 0d8e4417e7..1ff4b32e74 100644 --- a/meta/lib/oe/tune.py +++ b/meta/lib/oe/tune.py @@ -4,15 +4,42 @@ # SPDX-License-Identifier: GPL-2.0-only # -# RISC-V profile name -> equivalent ISA string. These are determined from compiler output, like: -# tgamblin@alchemist ~ $ riscv64-linux-gnu-gcc -march=rva20u64 -mabi=lp64d -Q --help=target | grep rv64 -# -march=rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd +# RISC-V profile name -> equivalent ISA string, i.e. the mandatory extensions of +# each profile as ratified in the RISC-V Profiles specification +# (https://github.com/riscv/riscv-profiles): +# RVA20U64, RVA22U64: RVA20/RVA22 Profiles, version 1.0 +# RVA23U64: RVA23 Profiles, version 1.0 +# plus the extensions those imply (e.g. zmmul, zaamo, zca, zve*). +# +# The profile names are used as package architectures, so each entry here is an +# ABI claim: packages built for "rva22u64" must keep meaning exactly this +# extension set. Do not regenerate these from compiler output (e.g. gcc's +# -march expansion); a newer compiler, or clang, may expand a profile +# differently. Changing an entry changes what existing package feeds mean. RISCV_PROFILES = { 'rva20u64': 'rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zmmul_za128rs_zaamo_zalrsc_zca_zcd', 'rva22u64': 'rv64imafdcb_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zihintpause_zmmul_za64rs_zaamo_zalrsc_zfhmin_zca_zcd_zba_zbb_zbs_zkt', 'rva23u64': 'rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_zvl128b_zvl32b_zvl64b_supm', } +# Extensions implied by another enabled extension (per GCC's +# riscv_implied_info). zicsr (implied by f) is left out for backwards +# compatibility, i.e. so the package archs of the existing non-profile tunes +# (e.g. riscv64imafdc_zicsr_zifencei) stay the same. +RISCV_IMPLIED = { + 'm': ['zmmul'], + 'a': ['zaamo', 'zalrsc'], + 'c': ['zca'], + 'b': ['zba', 'zbb', 'zbs'], + 'v': ['zve32f', 'zve32x', 'zve64d', 'zve64f', 'zve64x', 'zvl32b', 'zvl64b', 'zvl128b'], + 'zcb': ['zca'], + 'zcd': ['zca'], + 'zcmop': ['zca'], + 'zvbb': ['zvkb'], + # a reservation set of at most 64 bytes is also at most 128 bytes + 'za64rs': ['za128rs'], +} + # riscv_isa_to_tune(isa) # # Automatically translate a RISC-V ISA string to TUNE_FEATURES @@ -91,6 +118,15 @@ def riscv_isa_to_tune(isa): feature = list(dict.fromkeys(feature)) return ' '.join(feature) +# riscv_implied(enabled) +# +# Return the set of extensions implied by those in enabled. +def riscv_implied(enabled): + implied = {i for e in enabled for i in RISCV_IMPLIED.get(e, [])} + if 'c' in enabled and 'd' in enabled: + implied |= {'zcd', 'zca'} + return implied + # riscv_pkgarch(features, exact_pkgarch) # # Prefer a RISCV_PROFILES name (plus any extensions enabled on top of it) as the @@ -98,12 +134,25 @@ def riscv_isa_to_tune(isa): # what the sstate class can handle. When several profiles match, the one with # the most extensions is preferred, as it is the more specific/clearer match. # If there's no clear profile matching the extension list, then fall back to -# exact_pkgarch. +# exact_pkgarch. Either way, extensions implied by others are left out. def riscv_pkgarch(features, exact_pkgarch): if not features: return exact_pkgarch current = set(features.split()) + # Match profiles whether or not implied extensions (or the b shorthand) + # were listed + if {'zba', 'zbb', 'zbs'} <= current: + current.add('b') + implied = riscv_implied(current) + current |= implied + + # Drop implied extensions from the exact form too, keeping its base + # (e.g. riscv64imafdc) and canonical ordering. Only drop what the string + # itself implies, as b is never written out there. + base, *exts = exact_pkgarch.split('_') + exact_implied = riscv_implied(set(base[len('riscv64'):]) | set(exts)) + exact_pkgarch = '_'.join([base] + [e for e in exts if e not in exact_implied]) best_match = None best_features = None @@ -117,5 +166,5 @@ def riscv_pkgarch(features, exact_pkgarch): if best_match is None: return exact_pkgarch - extra = sorted(current - best_features) + extra = sorted(current - best_features - implied) return '_'.join([best_match] + extra) From patchwork Wed Sep 30 16:38:19 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 99743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7374ECA5FC4 for ; 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Wed, 30 Sep 2026 09:38:37 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:36 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:19 -0400 Subject: [OE-core][PATCH RFC v2 15/19] tune.py: add vector extensions to RISCV_IMPLIED MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-15-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:43:35 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246995 AI-Generated: Uses Claude Opus 5.5 Signed-off-by: Trevor Gamblin --- meta/lib/oe/tune.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/meta/lib/oe/tune.py b/meta/lib/oe/tune.py index 1ff4b32e74..2ab3428da7 100644 --- a/meta/lib/oe/tune.py +++ b/meta/lib/oe/tune.py @@ -36,6 +36,17 @@ RISCV_IMPLIED = { 'zcd': ['zca'], 'zcmop': ['zca'], 'zvbb': ['zvkb'], + # The vector subsets nest, for tunes with some of them but not v. Each + # entry lists everything it implies, since riscv_implied() only does one + # level of lookup. + 'zve64d': ['zve32f', 'zve32x', 'zve64f', 'zve64x', 'zvl32b', 'zvl64b'], + 'zve64f': ['zve32f', 'zve32x', 'zve64x', 'zvl32b', 'zvl64b'], + 'zve64x': ['zve32x', 'zvl32b', 'zvl64b'], + 'zve32f': ['zve32x', 'zvl32b'], + 'zve32x': ['zvl32b'], + 'zvfhmin': ['zve32f', 'zve32x', 'zvl32b'], + 'zvl128b': ['zvl32b', 'zvl64b'], + 'zvl64b': ['zvl32b'], # a reservation set of at most 64 bytes is also at most 128 bytes 'za64rs': ['za128rs'], } From patchwork Wed Sep 30 16:38:20 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 99745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65FC3CA5FC4 for ; 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Wed, 30 Sep 2026 09:38:38 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:37 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:20 -0400 Subject: [OE-core][PATCH RFC v2 16/19] tune-riscv.inc: add RISCV_PKGARCH vars, set PACKAGE_EXTRA_ARCHS MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-16-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:43:45 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246996 Add the RISCV_PKGARCH variables to help with indicating which tuning profiles are valid for use on configurations which are supersets of them, e.g. 'riscv64gc' packages are valid also for the 'rva20u64' profile. AI-Generated: Uses Claude Opus 5.5 Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/tune-riscv.inc | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index 500808ef12..b31d903172 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -4,23 +4,33 @@ DEFAULTTUNE ?= "riscv64gc" AVAILTUNES += "rva23u64 rva22u64 rva20u64 riscv64gcv riscv64gc riscv32gc riscv64 riscv32 riscv64nc riscv64nf riscv32nf" -# zifencei isn't part of these profiles per gcc's -march expansion, but the +# Each profile is a superset of the previous one and of riscv64gc (with the same +# lp64d ABI), so list those as compatible package archs, with lowest priority +# first. TUNE_RISCV_PKGARCH only expands to the currently selected tune's name. +RISCV_PKGARCH_GC = "riscv64imafdc_zicsr_zifencei" +RISCV_PKGARCH_RVA20 = "rva20u64_zifencei" +RISCV_PKGARCH_RVA22 = "rva22u64_zifencei" + +# riscv64gcv is unique in that rva20 and rva22 are not strict supersets of it +# (they lack the 'v' extension) but rva23 is, so split it out for comprehension. +RISCV_PKGARCH_GCV = "riscv64imafdcv_zicsr_zifencei" + # Linux kernel requires it, so add it on top of the profile's extensions. TUNE_FEATURES:tune-rva20u64 := "${@oe.tune.riscv_isa_to_tune("rva20u64")} zifencei" -PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${TUNE_RISCV_PKGARCH}" +PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${RISCV_PKGARCH_GC} ${TUNE_RISCV_PKGARCH}" TUNE_FEATURES:tune-rva22u64 := "${@oe.tune.riscv_isa_to_tune("rva22u64")} zifencei" -PACKAGE_EXTRA_ARCHS:tune-rva22u64 = "${TUNE_RISCV_PKGARCH}" +PACKAGE_EXTRA_ARCHS:tune-rva22u64 = "${RISCV_PKGARCH_GC} ${RISCV_PKGARCH_RVA20} ${TUNE_RISCV_PKGARCH}" TUNE_FEATURES:tune-rva23u64 := "${@oe.tune.riscv_isa_to_tune("rva23u64")} zifencei" -PACKAGE_EXTRA_ARCHS:tune-rva23u64 = "${TUNE_RISCV_PKGARCH}" +PACKAGE_EXTRA_ARCHS:tune-rva23u64 = "${RISCV_PKGARCH_GC} ${RISCV_PKGARCH_GCV} ${RISCV_PKGARCH_RVA20} ${RISCV_PKGARCH_RVA22} ${TUNE_RISCV_PKGARCH}" # Default TUNE_FEATURES:tune-riscv64gc := "${@oe.tune.riscv_isa_to_tune("rv64gc")}" PACKAGE_EXTRA_ARCHS:tune-riscv64gc = "${TUNE_RISCV_PKGARCH}" TUNE_FEATURES:tune-riscv64gcv := "${@oe.tune.riscv_isa_to_tune("rv64gcv")}" -PACKAGE_EXTRA_ARCHS:tune-riscv64gcv = "${TUNE_RISCV_PKGARCH}" +PACKAGE_EXTRA_ARCHS:tune-riscv64gcv = "${RISCV_PKGARCH_GC} ${TUNE_RISCV_PKGARCH}" TUNE_FEATURES:tune-riscv32gc := "${@oe.tune.riscv_isa_to_tune("rv32gc")}" PACKAGE_EXTRA_ARCHS:tune-riscv32gc = "${TUNE_RISCV_PKGARCH}" From patchwork Wed Sep 30 16:38:21 2026 Content-Type: text/plain; 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Wed, 30 Sep 2026 09:38:39 -0700 (PDT) Received: from [192.168.40.142] ([2001:1970:3847:e000:e8bd:ca0f:c232:9f10]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-917a89edf7fsm3519516d6.21.2026.09.30.09.38.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 09:38:39 -0700 (PDT) From: "Trevor Gamblin" Date: Wed, 30 Sep 2026 12:38:21 -0400 Subject: [OE-core][PATCH RFC v2 17/19] tune-riscv.inc: clarify zifencei comment MIME-Version: 1.0 Message-Id: <20260930-riscv-tuning-rework-v2-17-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:43:55 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246997 Signed-off-by: Trevor Gamblin --- meta/conf/machine/include/riscv/tune-riscv.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index b31d903172..76c7dad713 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -15,7 +15,8 @@ RISCV_PKGARCH_RVA22 = "rva22u64_zifencei" # (they lack the 'v' extension) but rva23 is, so split it out for comprehension. RISCV_PKGARCH_GCV = "riscv64imafdcv_zicsr_zifencei" -# Linux kernel requires it, so add it on top of the profile's extensions. +# zifencei isn't a mandatory extension in these profiles, but the Linux +# kernel requires it, so add it on top of the profile's extensions. TUNE_FEATURES:tune-rva20u64 := "${@oe.tune.riscv_isa_to_tune("rva20u64")} zifencei" PACKAGE_EXTRA_ARCHS:tune-rva20u64 = "${RISCV_PKGARCH_GC} ${TUNE_RISCV_PKGARCH}" From patchwork Wed Sep 30 16:38:22 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 99747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73159CA5FCB for ; Wed, 30 Sep 2026 16:43:55 +0000 (UTC) Received: from mail-qv2-f12.google.com (mail-qv2-f12.google.com [74.125.230.140]) by mx.groups.io with SMTP id smtpd.msgproc01-g2.18110.1790786321900887195 for ; Wed, 30 Sep 2026 09:38:42 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@baylibre.com header.s=google header.b=Xs5gIABr; spf=pass (domain: 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Message-Id: <20260930-riscv-tuning-rework-v2-18-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:43:55 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246998 Add a basic suite for meta/lib/oe/tune.py to test: - riscv_isa_to_tune() logic/expansion/parsing - riscv_implied() rules handling - Profile compatibility/nesting (e.g. rva22 is a superset of rva20) - riscv_pkgarch() profile naming/matching, including zifencei - Include testing of vector subsets when 'v' isn't specified, since these are technically valid AI-Generated: Uses Claude Opus 5.5 Signed-off-by: Trevor Gamblin --- meta/lib/oeqa/selftest/cases/oelib/tune.py | 88 ++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/meta/lib/oeqa/selftest/cases/oelib/tune.py b/meta/lib/oeqa/selftest/cases/oelib/tune.py new file mode 100644 index 0000000000..ff9b895fce --- /dev/null +++ b/meta/lib/oeqa/selftest/cases/oelib/tune.py @@ -0,0 +1,88 @@ +# +# Copyright OpenEmbedded Contributors +# +# SPDX-License-Identifier: MIT +# + +from unittest.case import TestCase +from oe.tune import RISCV_PROFILES, riscv_isa_to_tune, riscv_implied, riscv_pkgarch + +def features(isa): + return set(riscv_isa_to_tune(isa).split()) + +class TestRiscvIsaToTune(TestCase): + def test_abbreviation(self): + self.assertEqual(riscv_isa_to_tune('rv64gc'), 'rv 64 i m a f d c zicsr zifencei') + self.assertEqual(riscv_isa_to_tune('rv32gcv'), 'rv 32 i m a f d c v zicsr zifencei') + + def test_explicit(self): + self.assertEqual(riscv_isa_to_tune('rv32imac_zicsr_zifencei'), 'rv 32 i m a c zicsr zifencei') + self.assertEqual(riscv_isa_to_tune('RV64IMAFD_Zicsr'), 'rv 64 i m a f d zicsr') + + def test_profile(self): + for name, isa in RISCV_PROFILES.items(): + self.assertEqual(riscv_isa_to_tune(name), riscv_isa_to_tune(isa)) + + def test_not_riscv(self): + self.assertEqual(riscv_isa_to_tune('x86_64'), 'x86_64') + +class TestRiscvImplied(TestCase): + def test_implied(self): + self.assertEqual(riscv_implied({'m'}), {'zmmul'}) + self.assertEqual(riscv_implied({'c', 'd'}), {'zca', 'zcd'}) + self.assertEqual(riscv_implied({'za64rs'}), {'za128rs'}) + self.assertIn('zve64d', riscv_implied({'v'})) + # vector subsets, without v + self.assertEqual(riscv_implied({'zve64d', 'zvl128b'}), + {'zve32f', 'zve32x', 'zve64f', 'zve64x', 'zvl32b', 'zvl64b'}) + + def test_zicsr_kept(self): + # Dropping zicsr would rename the existing non-profile package archs + self.assertNotIn('zicsr', riscv_implied({'f', 'd'})) + + def test_profiles_nest(self): + # Later profiles are supersets of earlier ones, which tune-riscv.inc + # relies on for PACKAGE_EXTRA_ARCHS + names = ['rva20u64', 'rva22u64', 'rva23u64'] + for lower, higher in zip(names, names[1:]): + h = features(higher) + self.assertLessEqual(features(lower), h | riscv_implied(h), '%s is not a subset of %s' % (lower, higher)) + +class TestRiscvPkgarch(TestCase): + def test_no_features(self): + self.assertEqual(riscv_pkgarch('', 'riscv64imafdc'), 'riscv64imafdc') + + def test_profiles(self): + for name in RISCV_PROFILES: + self.assertEqual(riscv_pkgarch(riscv_isa_to_tune(name), 'unused'), name) + self.assertEqual(riscv_pkgarch(riscv_isa_to_tune(name) + ' zifencei', 'unused'), name + '_zifencei') + + def test_existing_names_unchanged(self): + self.assertEqual(riscv_pkgarch(riscv_isa_to_tune('rv64gc'), 'riscv64imafdc_zicsr_zifencei'), + 'riscv64imafdc_zicsr_zifencei') + self.assertEqual(riscv_pkgarch(riscv_isa_to_tune('rv32imac_zicsr_zifencei'), 'riscv32imac_zicsr_zifencei'), + 'riscv32imac_zicsr_zifencei') + + def test_most_specific_profile(self): + # rva23u64 without supm isn't rva23u64, but still contains all of rva22u64 + f = riscv_isa_to_tune('rva23u64').replace(' supm', '') + pkgarch = riscv_pkgarch(f, 'unused') + self.assertTrue(pkgarch.startswith('rva22u64_v_'), pkgarch) + # implied by v, so left out + self.assertNotIn('zve', pkgarch) + + def test_implied_not_listed(self): + # b is implied by zba/zbb/zbs, so leaving it out still matches the profile + f = riscv_isa_to_tune('rva22u64').replace(' b ', ' ') + self.assertEqual(riscv_pkgarch(f, 'unused'), 'rva22u64') + + def test_exact_drops_implied(self): + f = riscv_isa_to_tune('rv32imafdcv_zmmul_zaamo_zalrsc_zca_zcd_zve32x_zvl32b_zicsr_zifencei') + exact = 'riscv32imafdcv_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zve32x_zvl32b' + self.assertEqual(riscv_pkgarch(f, exact), 'riscv32imafdcv_zicsr_zifencei') + + def test_exact_keeps_bitmanip(self): + # b is never written out in the exact pkgarch, so zba/zbb/zbs must stay + f = riscv_isa_to_tune('rv64gc_zba_zbb_zbs') + exact = 'riscv64imafdc_zicsr_zifencei_zba_zbb_zbs' + self.assertEqual(riscv_pkgarch(f, exact), exact) From patchwork Wed Sep 30 16:38:23 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 99748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6791ACA5FC4 for ; Wed, 30 Sep 2026 16:44:05 +0000 (UTC) Received: from mail-qv2-f41.google.com (mail-qv2-f41.google.com [74.125.230.169]) by mx.groups.io with SMTP id smtpd.msgproc01-g2.18112.1790786323669537098 for ; Wed, 30 Sep 2026 09:38:43 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@baylibre.com header.s=google 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Message-Id: <20260930-riscv-tuning-rework-v2-19-9e29f3531d0e@baylibre.com> References: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> In-Reply-To: <20260930-riscv-tuning-rework-v2-0-9e29f3531d0e@baylibre.com> To: openembedded-core@lists.openembedded.org Cc: raj.khem@gmail.com, mark.hatle@kernel.crashing.org, Trevor Gamblin X-Mailer: b4 0.16.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 30 Sep 2026 16:44:05 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/246999 Add a test suite to ensure that all RISC-V tunes (default or 'unusual') yield valid pkgarch combinations and that PACKAGES_EXTRA_ARCHS lists only compatible tunings. AI-Generated: Uses Claude Opus 5.5 Signed-off-by: Trevor Gamblin --- meta/lib/oeqa/selftest/cases/riscvtune.py | 96 +++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/meta/lib/oeqa/selftest/cases/riscvtune.py b/meta/lib/oeqa/selftest/cases/riscvtune.py new file mode 100644 index 0000000000..2716b5bd02 --- /dev/null +++ b/meta/lib/oeqa/selftest/cases/riscvtune.py @@ -0,0 +1,96 @@ +# +# Copyright OpenEmbedded Contributors +# +# SPDX-License-Identifier: MIT +# + +from oe.tune import riscv_implied, riscv_isa_to_tune +from oeqa.selftest.case import OESelftestTestCase +from oeqa.utils.commands import bitbake, get_bb_var, get_bb_vars + +class RiscvTuneTests(OESelftestTestCase): + @classmethod + def setUpClass(cls): + super().setUpClass() + cls.orig_machine = get_bb_var('MACHINE') + + def machine_config(self, machine): + # Builds set up by bitbake-setup select the machine with a builtin + # fragment, which is fatal alongside a MACHINE assignment, so drop it + return 'OE_FRAGMENTS:remove = "machine/%s"\nMACHINE = "%s"\n' % (self.orig_machine, machine) + + def test_riscv_default_tunes(self): + """ + Parse every RISC-V tune and check it yields a usable package arch, and + that PACKAGE_EXTRA_ARCHS only lists archs of other tunes whose + extensions are all available in this one. + """ + self.write_config(self.machine_config('qemuriscv64')) + tunes = get_bb_var('AVAILTUNES').split() + + vars = {} + for tune in tunes: + machine = 'qemuriscv32' if 'riscv32' in tune else 'qemuriscv64' + self.write_config(self.machine_config(machine) + 'DEFAULTTUNE = "%s"\n' % tune) + vars[tune] = get_bb_vars(['TUNE_FEATURES', 'TUNE_PKGARCH', 'PACKAGE_EXTRA_ARCHS', 'PACKAGE_ARCHS']) + + pkgarch_features = {v['TUNE_PKGARCH']: set(v['TUNE_FEATURES'].split()) for v in vars.values()} + + for tune, v in vars.items(): + with self.subTest(tune=tune): + self.assertTrue(v['TUNE_FEATURES'], 'empty TUNE_FEATURES') + self.assertTrue(v['TUNE_PKGARCH'], 'empty TUNE_PKGARCH') + self.assertIn(v['TUNE_PKGARCH'], v['PACKAGE_ARCHS'].split()) + # sstate/package names get unwieldy past this + self.assertLessEqual(len(v['TUNE_PKGARCH']), 64, v['TUNE_PKGARCH']) + + features = set(v['TUNE_FEATURES'].split()) + features |= riscv_implied(features) + for arch in v['PACKAGE_EXTRA_ARCHS'].split(): + self.assertIn(arch, pkgarch_features, '%s is not the package arch of any tune' % arch) + self.assertLessEqual(pkgarch_features[arch], features, '%s needs extensions %s lacks' % (arch, tune)) + + # Profile tunes are named after the profile + for profile in ['rva20u64', 'rva22u64', 'rva23u64']: + self.assertEqual(vars[profile]['TUNE_PKGARCH'], profile + '_zifencei') + + # Legacy tune names behave exactly like the tunes they alias + for alias, target in [('riscv64', 'riscv64gc'), ('riscv32', 'riscv32gc')]: + with self.subTest(alias=alias): + self.assertIn(alias, tunes) + self.assertEqual(vars[alias], vars[target]) + + def test_riscv_unusual_tunes(self): + """ + Define custom tunes with unusual extension combinations, as a BSP + might, and check each one builds: the sanity checks accept the + package arch, gcc and binutils accept the -march string, and the + package arch fits in the sstate object names. + """ + def profile(name, drop=None): + return ' '.join(f for f in riscv_isa_to_tune(name).split() if f != drop) + ' zifencei' + tunes = { + # no float (lp64 ABI), with bitmanip + 'rv64-nofloat-bitmanip': riscv_isa_to_tune('rv64imac_zicsr_zifencei_zba_zbb_zbs'), + # no profile, scalar extensions on top of gc + 'rv64gc-scalar-extras': riscv_isa_to_tune('rv64gc_zicbom_zicboz_zicond_zfa_zfhmin'), + # profile plus vector crypto extensions + 'rva20-vector-crypto': profile('rva20u64') + ' v zvbb zvkt', + # a profile missing one extension, falling back to the previous one + 'rva22-no-zkt': profile('rva22u64', 'zkt'), + # rva23u64 without the full vector extension + 'rva23-no-v': profile('rva23u64', 'v'), + } + + config = self.machine_config('qemuriscv64') + for tune, features in tunes.items(): + config += 'AVAILTUNES += "%s"\n' % tune + config += 'TUNE_FEATURES:tune-%s = "%s"\n' % (tune, features) + config += 'PACKAGE_EXTRA_ARCHS:tune-%s = "${TUNE_RISCV_PKGARCH}"\n' % tune + + for tune in tunes: + with self.subTest(tune=tune): + self.write_config(config + 'DEFAULTTUNE = "%s"\n' % tune) + # small, and compiled with TUNE_CCARGS. It has no do_build, and + # populate_sysroot also writes an sstate object. + bitbake('libgcc-initial -c populate_sysroot')