diff mbox series

[meta-lts-mixins,scarthgap/rust,09/11] rust-target-config.bbclass: add RUST_TARGET_ABI to sstate signature exclusions

Message ID 0b09e58edb7fd57bf5583e7d80e40a390d1e2642.1769470900.git.scott.murray@konsulko.com
State New
Headers show
Series Update to Rust 1.92.0 | expand

Commit Message

Scott Murray Jan. 26, 2026, 11:51 p.m. UTC 
From: Alexander Kanavin <alex@linutronix.de>

This was overlooked in
https://lists.openembedded.org/g/openembedded-core/message/218953

and caused non-reusable sstate for rust-native when
the target is one of risc-v machines.

[YOCTO #16132]

Signed-off-by: Alexander Kanavin <alex@linutronix.de>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
(adapted from oe-core commit 9993e62f35c96aa8fce39a583f6cc391c0cbba99)
Signed-off-by: Scott Murray <scott.murray@konsulko.com>
---
 classes-recipe/rust-target-config.bbclass | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/classes-recipe/rust-target-config.bbclass b/classes-recipe/rust-target-config.bbclass
index 41e5362..73f13fd 100644
--- a/classes-recipe/rust-target-config.bbclass
+++ b/classes-recipe/rust-target-config.bbclass
@@ -416,7 +416,7 @@  def rust_gen_target(d, thing, wd, arch):
         json.dump(tspec, f, indent=4)
 
 # These are accounted for in tmpdir path names so don't need to be in the task sig
-rust_gen_target[vardepsexclude] += "ABIEXTENSION llvm_cpu"
+rust_gen_target[vardepsexclude] += "ABIEXTENSION llvm_cpu TUNE_RISCV_ABI"
 
 do_rust_gen_targets[vardeps] += "DATA_LAYOUT TARGET_ENDIAN TARGET_POINTER_WIDTH TARGET_C_INT_WIDTH MAX_ATOMIC_WIDTH FEATURES"