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[wrynose,10/17] u-boot: re-enable RISC-V compressed (c) ISA extension

Message ID c643e2d8af772182167a4ee2a65d5bcdc469934f.1784364567.git.yoann.congal@smile.fr
State New
Headers show
Series [wrynose,01/17] scripts/install-buildtools: Update to 6.0.2 | expand

Commit Message

Yoann Congal July 18, 2026, 8:52 a.m. UTC 
From: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>

SRC_URI_RISCV clears every RISC-V ISA extension via
u-boot-riscv-isa_clear.cfg, then conditionally re-adds a fragment per
TUNE_FEATURES bit: a, f, d, b/zbb, zicbom. There is no line for c, even
though u-boot-riscv-isa_c.cfg (CONFIG_RISCV_ISA_C=y) already ships in
the recipe. So for any tune with c in TUNE_FEATURES (e.g. the default
rv64gc/rv32gc tunes), compressed instructions stay disabled after the
clear fragment runs, and .config ends up with:

  # CONFIG_RISCV_ISA_C is not set

Building without RVC noticeably inflates .text: on qemuriscv64
(tune-riscv64, rv64gc), the resulting u-boot binary is 1312625 bytes of
.text without the fix vs 1082853 bytes with CONFIG_RISCV_ISA_C=y
correctly set, 229772 bytes (17.5%) smaller. On size-constrained
RISC-V SPL targets this .text growth can make the SPL .bss VMA overlap
the .text VMA and fail the link.

Add the missing "c" mapping line, mirroring the existing per-extension
entries (a, f, d, b/zbb, zicbom) already present in SRC_URI_RISCV.

Tested on oe-core master, MACHINE=qemuriscv64, via the
oe-nodistro-master bitbake-setup config:

  bitbake -c cleansstate u-boot && bitbake u-boot
  grep CONFIG_RISCV_ISA_C .../u-boot/2026.04/build/.config
  # before: "# CONFIG_RISCV_ISA_C is not set"
  # after:  "CONFIG_RISCV_ISA_C=y"

do_package_qa passes both before and after; only the ISA config and
resulting .text size change.

Fixes: cd9e7304481b ("u-boot: Overhaul UBOOT_CONFIG flow")

AI-Generated: Uses Cursor

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
(cherry picked from commit fef027f2350cec0e6b890b636d2529a13f1fab58)
Signed-off-by: Yoann Congal <yoann.congal@smile.fr>
---
 meta/recipes-bsp/u-boot/u-boot_2026.01.bb | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/meta/recipes-bsp/u-boot/u-boot_2026.01.bb b/meta/recipes-bsp/u-boot/u-boot_2026.01.bb
index ac1b0b9b2b4..6d9bc126a16 100644
--- a/meta/recipes-bsp/u-boot/u-boot_2026.01.bb
+++ b/meta/recipes-bsp/u-boot/u-boot_2026.01.bb
@@ -14,6 +14,7 @@  SRC_URI_RISCV = "\
     ${@bb.utils.contains    ("TUNE_FEATURES", "a",      "file://u-boot-riscv-isa_a.cfg", "", d)} \
     ${@bb.utils.contains    ("TUNE_FEATURES", "f",      "file://u-boot-riscv-isa_f.cfg", "", d)} \
     ${@bb.utils.contains    ("TUNE_FEATURES", "d",      "file://u-boot-riscv-isa_d.cfg", "", d)} \
+    ${@bb.utils.contains    ("TUNE_FEATURES", "c",      "file://u-boot-riscv-isa_c.cfg", "", d)} \
     ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb",  "file://u-boot-riscv-isa_zbb.cfg", "", d)} \
     ${@bb.utils.contains    ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \
     "