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[2a01:cb00:1331:aa00:1444:456e:f7d8:4e9a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4954a2b87c6sm176409335e9.7.2026.07.18.01.53.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jul 2026 01:53:26 -0700 (PDT) From: Yoann Congal To: openembedded-core@lists.openembedded.org Subject: [OE-core][wrynose 10/17] u-boot: re-enable RISC-V compressed (c) ISA extension Date: Sat, 18 Jul 2026 10:52:49 +0200 Message-ID: X-Mailer: git-send-email 2.47.3 In-Reply-To: References: MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Sat, 18 Jul 2026 08:53:31 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/241247 From: Gustavo Henrique Nihei SRC_URI_RISCV clears every RISC-V ISA extension via u-boot-riscv-isa_clear.cfg, then conditionally re-adds a fragment per TUNE_FEATURES bit: a, f, d, b/zbb, zicbom. There is no line for c, even though u-boot-riscv-isa_c.cfg (CONFIG_RISCV_ISA_C=y) already ships in the recipe. So for any tune with c in TUNE_FEATURES (e.g. the default rv64gc/rv32gc tunes), compressed instructions stay disabled after the clear fragment runs, and .config ends up with: # CONFIG_RISCV_ISA_C is not set Building without RVC noticeably inflates .text: on qemuriscv64 (tune-riscv64, rv64gc), the resulting u-boot binary is 1312625 bytes of .text without the fix vs 1082853 bytes with CONFIG_RISCV_ISA_C=y correctly set, 229772 bytes (17.5%) smaller. On size-constrained RISC-V SPL targets this .text growth can make the SPL .bss VMA overlap the .text VMA and fail the link. Add the missing "c" mapping line, mirroring the existing per-extension entries (a, f, d, b/zbb, zicbom) already present in SRC_URI_RISCV. Tested on oe-core master, MACHINE=qemuriscv64, via the oe-nodistro-master bitbake-setup config: bitbake -c cleansstate u-boot && bitbake u-boot grep CONFIG_RISCV_ISA_C .../u-boot/2026.04/build/.config # before: "# CONFIG_RISCV_ISA_C is not set" # after: "CONFIG_RISCV_ISA_C=y" do_package_qa passes both before and after; only the ISA config and resulting .text size change. Fixes: cd9e7304481b ("u-boot: Overhaul UBOOT_CONFIG flow") AI-Generated: Uses Cursor Signed-off-by: Gustavo Henrique Nihei Signed-off-by: Mathieu Dubois-Briand Signed-off-by: Richard Purdie (cherry picked from commit fef027f2350cec0e6b890b636d2529a13f1fab58) Signed-off-by: Yoann Congal --- meta/recipes-bsp/u-boot/u-boot_2026.01.bb | 1 + 1 file changed, 1 insertion(+) diff --git a/meta/recipes-bsp/u-boot/u-boot_2026.01.bb b/meta/recipes-bsp/u-boot/u-boot_2026.01.bb index ac1b0b9b2b4..6d9bc126a16 100644 --- a/meta/recipes-bsp/u-boot/u-boot_2026.01.bb +++ b/meta/recipes-bsp/u-boot/u-boot_2026.01.bb @@ -14,6 +14,7 @@ SRC_URI_RISCV = "\ ${@bb.utils.contains ("TUNE_FEATURES", "a", "file://u-boot-riscv-isa_a.cfg", "", d)} \ ${@bb.utils.contains ("TUNE_FEATURES", "f", "file://u-boot-riscv-isa_f.cfg", "", d)} \ ${@bb.utils.contains ("TUNE_FEATURES", "d", "file://u-boot-riscv-isa_d.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "c", "file://u-boot-riscv-isa_c.cfg", "", d)} \ ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "file://u-boot-riscv-isa_zbb.cfg", "", d)} \ ${@bb.utils.contains ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \ "