| Message ID | 1751492664-12569-1-git-send-email-mark.hatle@kernel.crashing.org |
|---|---|
| Headers | show |
| Series | ISA based RISC-V tune implementation | expand |
Hi Mark, On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via lists.openembedded.org wrote: > From: Mark Hatle <mark.hatle@amd.com> > > The following implements the risc-v processor tune based on the ISA approach > as documented in the oe-architecture post: > > https://lists.openembedded.org/g/openembedded-architecture/message/2155 > > This set also attempts to make u-boot and kernel configurations dynamic > based on the TUNE_FEATURES. > > For the linux-yocto, I suspect that the config fragments should be > sent to the kmeta (kernel-cache), but I'd like a review from Bruce and > others before I do this. > > Additionally, this enables a new (optional) features_check for TUNE_FEATURES. > > I've found numerous items in the system have certain RISC-V ISA expectations > that may need to be addressed over time, however the obvious one is the > Linux kernel requires ima_zicsr_zifencei. Since it has it's own -march= > setting this will ensure the processor defintion will be compatible. > > Also dynamically configure the QEMU cpu based on the tune_features. This > is nice to ensure that what we're actually building should be able to run > on real hardware. However, it does highlight some of the (extension) > limitations in the current design. (limitations as in extension not yet > enabled.) > > Note: OpenSBI _requires_ the 'c' extension or it will not execute. I > suspect this can be fixed, but it's beyond my capabilities at this time. I've narrowed it down to something in these patches which causes these ptest failures on qemuriscv64: https://autobuilder.yoctoproject.org/valkyrie/#/builders/56/builds/187 We need to track down and fix those regressions before this can merge. Cheers, Richard
On 7/9/25 12:42 AM, Richard Purdie via lists.openembedded.org wrote: > Hi Mark, > > On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via lists.openembedded.org wrote: >> From: Mark Hatle <mark.hatle@amd.com> >> >> The following implements the risc-v processor tune based on the ISA approach >> as documented in the oe-architecture post: >> >> https://lists.openembedded.org/g/openembedded-architecture/message/2155 >> >> This set also attempts to make u-boot and kernel configurations dynamic >> based on the TUNE_FEATURES. >> >> For the linux-yocto, I suspect that the config fragments should be >> sent to the kmeta (kernel-cache), but I'd like a review from Bruce and >> others before I do this. >> >> Additionally, this enables a new (optional) features_check for TUNE_FEATURES. >> >> I've found numerous items in the system have certain RISC-V ISA expectations >> that may need to be addressed over time, however the obvious one is the >> Linux kernel requires ima_zicsr_zifencei. Since it has it's own -march= >> setting this will ensure the processor defintion will be compatible. >> >> Also dynamically configure the QEMU cpu based on the tune_features. This >> is nice to ensure that what we're actually building should be able to run >> on real hardware. However, it does highlight some of the (extension) >> limitations in the current design. (limitations as in extension not yet >> enabled.) >> >> Note: OpenSBI _requires_ the 'c' extension or it will not execute. I >> suspect this can be fixed, but it's beyond my capabilities at this time. > > I've narrowed it down to something in these patches which causes these > ptest failures on qemuriscv64: > > https://autobuilder.yoctoproject.org/valkyrie/#/builders/56/builds/187 > > We need to track down and fix those regressions before this can merge. > I think the extension selection should match the base platform spec for rvb23 profile for default qemu machine, perhaps something regressed there with Mark's extension based construction of default tunes. > Cheers, > > Richard > > > > -=-=-=-=-=-=-=-=-=-=-=- > Links: You receive all messages sent to this group. > View/Reply Online (#220078): https://lists.openembedded.org/g/openembedded-core/message/220078 > Mute This Topic: https://lists.openembedded.org/mt/113956552/1997914 > Group Owner: openembedded-core+owner@lists.openembedded.org > Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub [raj.khem@gmail.com] > -=-=-=-=-=-=-=-=-=-=-=- >
From: Mark Hatle <mark.hatle@amd.com> The following implements the risc-v processor tune based on the ISA approach as documented in the oe-architecture post: https://lists.openembedded.org/g/openembedded-architecture/message/2155 This set also attempts to make u-boot and kernel configurations dynamic based on the TUNE_FEATURES. For the linux-yocto, I suspect that the config fragments should be sent to the kmeta (kernel-cache), but I'd like a review from Bruce and others before I do this. Additionally, this enables a new (optional) features_check for TUNE_FEATURES. I've found numerous items in the system have certain RISC-V ISA expectations that may need to be addressed over time, however the obvious one is the Linux kernel requires ima_zicsr_zifencei. Since it has it's own -march= setting this will ensure the processor defintion will be compatible. Also dynamically configure the QEMU cpu based on the tune_features. This is nice to ensure that what we're actually building should be able to run on real hardware. However, it does highlight some of the (extension) limitations in the current design. (limitations as in extension not yet enabled.) Note: OpenSBI _requires_ the 'c' extension or it will not execute. I suspect this can be fixed, but it's beyond my capabilities at this time. v3: - The base implementation has been merged. This is the remaining items for kernel dependencies, and linux. (reworked to use yocto-kernel-cache) as well as the u-boot and qemu items. (These are the same as v2.) As noted in 5/6, some of these dynamic ISA options seem to be adjusted by other default settings. Specifically CONFIG_ISA_C is enabled by CONFIG_EFI. I did test various combinations with a custom defconfig (in qemu) to verify that the code does what it should AND/OR reports any settings it couldn't disable. Tested combinations: rv32ima_zicsr_zifencei rv32imac_zicsr_zifencei rv32gc rv32imafdc_zicsr_zifencei rv64ima_zicsr_zifencei rv64imac_zicsr_zifencei rv64gc rv64gcv rv64imafdc_zicsr_zifencei Testing involved kernel disabling CONFIG_EFI, enabling CONFIG_NONPORTABLE and the corresponding tune. v2: - Note: the linux-yocto change still needs further rework (noted in commit) (if everything else is merged, it will still work fine) - Change the TUNE_FEATURES check to kernel.bbclass per review comments - Add 7/7 patch for RUST configuration. Mark Hatle (6): u-boot: Dynamic RISC-V ISA configuration features_check.bbclass: Add support for required TUNE_FEATURES kernel.bbclass: State riscv required tune_features for Linux linux-yocto/6.12: riscv: Enable dynamic ISA selection linux-yocto/6.12: riscv: Enable TUNE_FEATURES based KERNEL_FEATURES qemuriscv: Dynamically configure qemu CPU meta/classes-recipe/features_check.bbclass | 2 +- meta/classes-recipe/kernel.bbclass | 6 +++- meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++-- .../u-boot/files/u-boot-riscv-isa_a.cfg | 1 + .../u-boot/files/u-boot-riscv-isa_c.cfg | 1 + .../u-boot/files/u-boot-riscv-isa_clear.cfg | 6 ++++ .../u-boot/files/u-boot-riscv-isa_d.cfg | 1 + .../u-boot/files/u-boot-riscv-isa_f.cfg | 1 + .../u-boot/files/u-boot-riscv-isa_zbb.cfg | 1 + .../u-boot/files/u-boot-riscv-isa_zicbom.cfg | 1 + meta/recipes-bsp/u-boot/u-boot-common.inc | 12 +++++++ .../linux/linux-yocto-rt_6.12.bb | 2 +- .../linux/linux-yocto-tiny_6.12.bb | 2 +- meta/recipes-kernel/linux/linux-yocto.inc | 16 ++++++++++ meta/recipes-kernel/linux/linux-yocto_6.12.bb | 2 +- 15 files changed, 77 insertions(+), 8 deletions(-) create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg