@@ -16,8 +16,8 @@ TFA_BL2_BINARY = "bl2-corstone1000.bin"
TFA_FIP_BINARY = "fip-corstone1000.bin"
# optee
-PREFERRED_VERSION_optee-os ?= "4.7.%"
-PREFERRED_VERSION_optee-client ?= "4.7.%"
+PREFERRED_VERSION_optee-os ?= "4.9.%"
+PREFERRED_VERSION_optee-client ?= "4.9.%"
# Trusted Services
TS_PLATFORM = "arm/corstone1000"
@@ -27,7 +27,7 @@ sys.path.append(os.path.dirname(__file__))
# -- Project information -----------------------------------------------------
project = 'corstone1000'
-copyright = '2020-2024, Arm Limited'
+copyright = '2020-2026, Arm Limited'
author = 'Arm Limited'
@@ -91,7 +91,7 @@ Host Processor Components
+----------+-------------------------------------------------------------------------------------------------------+
| bbappend | ``${WORKSPACE}/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_%.bbappend`` |
+----------+-------------------------------------------------------------------------------------------------------+
-| Recipe | ``${WORKSPACE}/meta-arm/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.13.0.bb`` |
+| Recipe | ``${WORKSPACE}/meta-arm/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.14.0.bb`` |
+----------+-------------------------------------------------------------------------------------------------------+
`Trusted Services <https://trusted-services.readthedocs.io/en/latest/index.html>`__
@@ -133,7 +133,7 @@ Host Processor Components
+----------+------------------------------------------------------------------------------------------+
| bbappend | ``${WORKSPACE}/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os_4.%.bbappend`` |
+----------+------------------------------------------------------------------------------------------+
-| Recipe | ``${WORKSPACE}/meta-arm/meta-arm/recipes-security/optee/optee-os_4.7.0.bb`` |
+| Recipe | ``${WORKSPACE}/meta-arm/meta-arm/recipes-security/optee/optee-os_4.9.0.bb`` |
+----------+------------------------------------------------------------------------------------------+
`U-Boot <https://github.com/u-boot/u-boot.git>`__
@@ -2365,7 +2365,7 @@ and `Arm Development Studio <arm-ds-website_>`__ versions 2022.2, 2022.c, or 202
--------------
-*Copyright (c) 2022-2025, Arm Limited. All rights reserved.*
+*Copyright (c) 2022-2026, Arm Limited. All rights reserved.*
.. _arm-developer-fvp: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
.. _secure-debug-manager-repo-readme: https://github.com/ARM-software/secure-debug-manager/tree/master?tab=readme-ov-file#secure-debug-manager-psa-adac--sdc-600
deleted file mode 100644
@@ -1,143 +0,0 @@
-From 4a8fa965a39879d98eac1626c4c756043985726d Mon Sep 17 00:00:00 2001
-From: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
-Date: Tue, 11 Nov 2025 08:09:40 +0000
-Subject: [PATCH] plat-corstone1000: Add Cortex-A320 support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
-(default) assignment so users can override it (for example to
-cortex-a320) via the make command line.
-
-The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
-When arm64-platform-cpuarch is set to cortex-a320, switch to
--march=armv9.2-a.
-
-The new Corstone-1000 variant with Cortex-A320 replaces the original
-GIC-400 (v2) interrupt controller with a GIC-600, which is
-architecturally compliant with GICv3. Since OP-TEE already provides
-a generic GICv3 driver, only minimal platform changes are needed
-to expose the updated register map and initialize the GICv3 interface.
-
-**Changes introduced**
-
-* When `cortex-a320` is selected:
- * Force `CFG_ARM_GICV3=y`.
- * Introduce `CFG_CORSTONE1000_CORTEX_A320` to guard
- Cortex-A320–specific code.
-* Map the Redistributor region (`GICR_BASE`).
-* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
-* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
-* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
- the Cortex-A35 + GIC-400 variant continues to build unchanged.
-
-Upstream-Status: Submitted (https://github.com/OP-TEE/optee_os/pull/7627)
-Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
-Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
----
- core/arch/arm/plat-corstone1000/conf.mk | 11 ++++++++++-
- core/arch/arm/plat-corstone1000/main.c | 11 ++++++++++-
- .../arm/plat-corstone1000/platform_config.h | 19 +++++++++++++++++--
- 3 files changed, 37 insertions(+), 4 deletions(-)
-
-diff --git a/core/arch/arm/plat-corstone1000/conf.mk b/core/arch/arm/plat-corstone1000/conf.mk
-index 86b8d8480..147b6972f 100644
---- a/core/arch/arm/plat-corstone1000/conf.mk
-+++ b/core/arch/arm/plat-corstone1000/conf.mk
-@@ -23,9 +23,18 @@ $(call force,CFG_PL011,y)
- $(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
- $(call force,CFG_ARM64_core,y)
-
--arm64-platform-cpuarch := cortex-a35
-+# Default CPU core for Corstone1000 platform; override for other cores (e.g. cortex-a320)
-+arm64-platform-cpuarch ?= cortex-a35
-+
-+ifeq ($(arm64-platform-cpuarch),cortex-a320)
-+arm64-platform-cflags += -march=armv9.2-a
-+arm64-platform-aflags += -march=armv9.2-a
-+$(call force,CFG_ARM_GICV3,y)
-+$(call force,CFG_CORSTONE1000_CORTEX_A320,y)
-+else
- arm64-platform-cflags += -mcpu=$(arm64-platform-cpuarch)
- arm64-platform-aflags += -mcpu=$(arm64-platform-cpuarch)
-+endif
-
- CFG_WITH_STATS ?= y
- CFG_WITH_ARM_TRUSTED_FW ?= y
-diff --git a/core/arch/arm/plat-corstone1000/main.c b/core/arch/arm/plat-corstone1000/main.c
-index 9e1482a7b..fd2dd888c 100644
---- a/core/arch/arm/plat-corstone1000/main.c
-+++ b/core/arch/arm/plat-corstone1000/main.c
-@@ -1,6 +1,6 @@
- // SPDX-License-Identifier: BSD-2-Clause
- /*
-- * Copyright (c) 2022, Arm Limited
-+ * Copyright (c) 2022, 2025, Arm Limited
- */
-
- #include <console.h>
-@@ -18,11 +18,20 @@ register_ddr(DRAM0_BASE, DRAM0_SIZE);
-
- register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
- register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
-+
-+#if defined(CFG_CORSTONE1000_CORTEX_A320) && defined(CFG_ARM_GICV3)
-+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_REDIST_REG_SIZE);
-+#else
- register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
-+#endif
-
- void boot_primary_init_intc(void)
- {
-+#if defined(CFG_CORSTONE1000_CORTEX_A320) && defined(CFG_ARM_GICV3)
-+ gic_init_v3(0, GICD_BASE, GICR_BASE);
-+#else
- gic_init(GICC_BASE, GICD_BASE);
-+#endif
- }
-
- void boot_secondary_init_intc(void)
-diff --git a/core/arch/arm/plat-corstone1000/platform_config.h b/core/arch/arm/plat-corstone1000/platform_config.h
-index f59c93a14..600b2c02e 100644
---- a/core/arch/arm/plat-corstone1000/platform_config.h
-+++ b/core/arch/arm/plat-corstone1000/platform_config.h
-@@ -1,6 +1,6 @@
- /* SPDX-License-Identifier: BSD-2-Clause */
- /*
-- * Copyright (c) 2022, Arm Limited
-+ * Copyright (c) 2022, 2025 Arm Limited
- */
-
- #ifndef PLATFORM_CONFIG_H
-@@ -20,11 +20,26 @@
- #define DRAM0_BASE 0x80000000
- #define DRAM0_SIZE CFG_DDR_SIZE
-
-+#if defined(CFG_CORSTONE1000_CORTEX_A320) && defined(CFG_ARM_GICV3)
-+#define GICR_SIZE_PER_CORE 0x20000
-+#define GIC_REDIST_REG_SIZE (GICR_SIZE_PER_CORE * CFG_TEE_CORE_NB_CORE)
-+#endif
-+
-+#if defined(CFG_CORSTONE1000_CORTEX_A320) && defined(CFG_ARM_GICV3)
-+/* Corstone-1000 with Cortex-A320 uses GIC-v3 which supports GICR */
-+#define GICD_OFFSET 0x00000
-+#define GICR_OFFSET 0x40000
-+#else
- #define GICD_OFFSET 0x10000
- #define GICC_OFFSET 0x2F000
-+#endif
-
--#define GICD_BASE (GIC_BASE + GICD_OFFSET)
-+#if defined(CFG_CORSTONE1000_CORTEX_A320) && defined(CFG_ARM_GICV3)
-+#define GICR_BASE (GIC_BASE + GICR_OFFSET)
-+#else
- #define GICC_BASE (GIC_BASE + GICC_OFFSET)
-+#endif
-+#define GICD_BASE (GIC_BASE + GICD_OFFSET)
-
- #define UART_BAUDRATE 115200
- #define CONSOLE_BAUDRATE UART_BAUDRATE
-2.50.1
-
@@ -1,9 +1,5 @@
FILESEXTRAPATHS:prepend := "${THISDIR}/files/optee-os/corstone1000:"
-SRC_URI:append = " \
- file://0001-plat-corstone1000-Add-Cortex-A320-support.patch \
-"
-
COMPATIBLE_MACHINE = "corstone1000"
OPTEEMACHINE = "corstone1000"
@@ -1,11 +1,8 @@
require recipes-security/optee/optee-client.inc
-# v4.8.0
-SRCREV = "9d6f69844ff60ec0966cf3659abcc38eda8b31ea"
+# v4.9.0
+SRCREV = "9f5e90918093c1d1cd264d8149081b64ab7ba672"
PV .= "+git"
-FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
-SRC_URI += "file://0001-tee-supplicant-update-udev-systemd-install-code.patch"
-
# Not a release recipe, try our hardest to not pull this in implicitly
DEFAULT_PREFERENCE = "-1"
Bump Corstone-1000 machine OP-TEE version from 4.7.0 to version 4.9.0. Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> --- .../conf/machine/include/corstone1000.inc | 4 +- .../documentation/corstone1000/conf.py | 2 +- .../documentation/corstone1000/user-guide.rst | 6 +- ...corstone1000-Add-Cortex-A320-support.patch | 143 ------------------ .../optee/optee-os-corstone1000-common.inc | 4 - .../optee/optee-client_git.bb | 7 +- 6 files changed, 8 insertions(+), 158 deletions(-) delete mode 100644 meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0001-plat-corstone1000-Add-Cortex-A320-support.patch