[v3,6/6] qemuriscv: Dynamically configure qemu CPU

From: Mark Hatle <mark.hatle@amd.com>

Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
options selected by the DEFAULTTUNE.

Note: OpenSBI currently requires 'c' (compressed instructions) or it will
not work.

Change the base device configuration to use a different variable to select
the emulate devices.  This will allow a user to override or append the
QB_OPT_APPEND without the riscv32 override getting in the way.

Signed-off-by: Mark Hatle <mark.hatle@amd.com>
---
 meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
 1 file changed, 28 insertions(+), 3 deletions(-)

On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via lists.openembedded.org wrote:
> From: Mark Hatle <mark.hatle@amd.com>
> 
> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
> options selected by the DEFAULTTUNE.
> 
> Note: OpenSBI currently requires 'c' (compressed instructions) or it will
> not work.
> 
> Change the base device configuration to use a different variable to select
> the emulate devices.  This will allow a user to override or append the
> QB_OPT_APPEND without the riscv32 override getting in the way.
> 
> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
> ---
>  meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
>  1 file changed, 28 insertions(+), 3 deletions(-)
> 

FWIW I narrowed down the ptest failures to this patch.

Cheers,

Richard

I will investigate.

I suspect SOME of this may be test cases with hard coded riscv assembly in them 
using extensions that we've not enabled.

The configuration listed in the logs for the kernel are:

rv64imafdc

  '[    0.000000] riscv: base ISA extensions acdfim\n'
  '[    0.000000] riscv: ELF capabilities acdfim\n'

The 'v' (vector) extension is intentionally not enabled to match the software 
configuration, but some tests may be trying to use it.

I'll walk through this and attempt to get this identified for real.

--Mark

On 7/9/25 4:17 AM, Richard Purdie via lists.openembedded.org wrote:
> On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via lists.openembedded.org wrote:
>> From: Mark Hatle <mark.hatle@amd.com>
>>
>> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
>> options selected by the DEFAULTTUNE.
>>
>> Note: OpenSBI currently requires 'c' (compressed instructions) or it will
>> not work.
>>
>> Change the base device configuration to use a different variable to select
>> the emulate devices.  This will allow a user to override or append the
>> QB_OPT_APPEND without the riscv32 override getting in the way.
>>
>> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
>> ---
>>   meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
>>   1 file changed, 28 insertions(+), 3 deletions(-)
>>
> 
> FWIW I narrowed down the ptest failures to this patch.
> 
> Cheers,
> 
> Richard
> 
> 
> 
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On 7/9/25 7:54 AM, Mark Hatle via lists.openembedded.org wrote:
> I will investigate.
> 
> I suspect SOME of this may be test cases with hard coded riscv assembly 
> in them using extensions that we've not enabled.
> 
> The configuration listed in the logs for the kernel are:
> 
> rv64imafdc
> 
>   '[    0.000000] riscv: base ISA extensions acdfim\n'
>   '[    0.000000] riscv: ELF capabilities acdfim\n'
> 
> The 'v' (vector) extension is intentionally not enabled to match the 
> software configuration, but some tests may be trying to use it.
> 
> I'll walk through this and attempt to get this identified for real.


We should be enabling the rvb23 (rv64gcv) profile as default for qemu, since
that is the baseline for a RISCV profile that OE will be used as base 
infrastructure and we should target that commonly, perhaps changing 
default tune for qemuriscv64 to consider that would be a good thing. I 
know there is
a value in constructing the ISA+extension set that qemu emulates based 
on tune selection and whatever rv64gcv devolves down in terms of 
extensions.

> 
> --Mark
> 
> On 7/9/25 4:17 AM, Richard Purdie via lists.openembedded.org wrote:
>> On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via 
>> lists.openembedded.org wrote:
>>> From: Mark Hatle <mark.hatle@amd.com>
>>>
>>> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
>>> options selected by the DEFAULTTUNE.
>>>
>>> Note: OpenSBI currently requires 'c' (compressed instructions) or it 
>>> will
>>> not work.
>>>
>>> Change the base device configuration to use a different variable to 
>>> select
>>> the emulate devices.  This will allow a user to override or append the
>>> QB_OPT_APPEND without the riscv32 override getting in the way.
>>>
>>> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
>>> ---
>>>   meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
>>>   1 file changed, 28 insertions(+), 3 deletions(-)
>>>
>>
>> FWIW I narrowed down the ptest failures to this patch.
>>
>> Cheers,
>>
>> Richard
>>
>>
>>
>>
>>
> 
> 
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On 7/9/25 11:23 AM, Khem Raj wrote:
> 
> 
> On 7/9/25 7:54 AM, Mark Hatle via lists.openembedded.org wrote:
>> I will investigate.
>>
>> I suspect SOME of this may be test cases with hard coded riscv assembly
>> in them using extensions that we've not enabled.
>>
>> The configuration listed in the logs for the kernel are:
>>
>> rv64imafdc
>>
>>    '[    0.000000] riscv: base ISA extensions acdfim\n'
>>    '[    0.000000] riscv: ELF capabilities acdfim\n'
>>
>> The 'v' (vector) extension is intentionally not enabled to match the
>> software configuration, but some tests may be trying to use it.
>>
>> I'll walk through this and attempt to get this identified for real.
> 
> 
> We should be enabling the rvb23 (rv64gcv) profile as default for qemu, since
> that is the baseline for a RISCV profile that OE will be used as base
> infrastructure and we should target that commonly, perhaps changing

I disagree that the 'baseline' should be rv64gcv.  Because this is a variable 
ISA, we need the baseline to be something reasonably common across multiple 
vendors.  (Note, I didn't say all vendors).  rv64gc seems to be common from the 
research I did, the 'v' is also available, but not as widely available on 
non-workstation oriented chips.

> default tune for qemuriscv64 to consider that would be a good thing. I
> know there is
> a value in constructing the ISA+extension set that qemu emulates based
> on tune selection and whatever rv64gcv devolves down in terms of
> extensions.

BEFORE my work, the tune was "riscv64".  (I maintained this after as well)

https://git.yoctoproject.org/poky/tree/meta/conf/machine/include/riscv/arch-riscv.inc?h=walnascar

https://git.yoctoproject.org/poky/tree/meta/conf/machine/include/riscv/tune-riscv.inc?h=walnascar

This mapped to rv64gc (NO V), so that is what I implemented.  How did I 
determine it was rv64gc and not rv64gcv?  I queried the compiler to see what the 
default options were since the ISA was not defined anywhere.

If we want to move to rv64gcv, then that can be adjusted in:

https://git.yoctoproject.org/poky/tree/meta/conf/machine/include/riscv/tune-riscv.inc

Just change the 'riscv64' configuration to add the 'v'.

I don't really care what our default is as long as someone defined it and tests 
it.  BUT I do care that NOT using our default WILL continue to work.

Just moving to rv64gcv unconditionally isn't right.  Not all riscv cores have 
vector units, or even the compressed extension, let along f/d floating point. 
So we have to be flexible or there is no purpose to this work.


I believe it's key for the RISC-V sponsors who will end up owning this work to 
speak up.  I can say what I know, you can say when you know -- but ultimately 
I'm only going to be doing this work until it meets my needs and then I'm going 
to step back while other people implement what they need.  (I'm not going to 
abandon it, but I need the work _now_, so I had to step in to implement it.)

What we do NOT have to be is platform that runs portable code with Ubuntu/Red 
Hat and others.

For _MY_ purposes, _MY_ chips do not have a vector unit, my rv32 do not have 
double precision floating point (only single).  Additional the following items 
are all user selectable:

rv32i vs rv32e (e is not compatible with Linux, but is with baremetal!)
rv64i

m - optional
a - optional
f - optional
d - only available with rv64i
c - optional (not recommended)
(as well as some z extensions)

Linux REQUIRES rv<size>ima

It does not require fdc (or v) as well as the z extensions (except for zicsr and 
zifencei).

--Mark


>>
>> --Mark
>>
>> On 7/9/25 4:17 AM, Richard Purdie via lists.openembedded.org wrote:
>>> On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via
>>> lists.openembedded.org wrote:
>>>> From: Mark Hatle <mark.hatle@amd.com>
>>>>
>>>> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
>>>> options selected by the DEFAULTTUNE.
>>>>
>>>> Note: OpenSBI currently requires 'c' (compressed instructions) or it
>>>> will
>>>> not work.
>>>>
>>>> Change the base device configuration to use a different variable to
>>>> select
>>>> the emulate devices.  This will allow a user to override or append the
>>>> QB_OPT_APPEND without the riscv32 override getting in the way.
>>>>
>>>> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
>>>> ---
>>>>    meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
>>>>    1 file changed, 28 insertions(+), 3 deletions(-)
>>>>
>>>
>>> FWIW I narrowed down the ptest failures to this patch.
>>>
>>> Cheers,
>>>
>>> Richard
>>>
>>>
>>>
>>>
>>>
>>
>>
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