| Message ID | 20260720124620.1194239-1-gustavo.nihei@espressif.com |
|---|---|
| State | Under Review |
| Delegated to: | Yoann Congal |
| Headers | show |
| Series | [wrynose,v2] u-boot: re-enable RISC-V compressed (c) ISA extension | expand |
On Mon Jul 20, 2026 at 2:46 PM CEST, Gustavo Henrique Nihei wrote: > SRC_URI_RISCV clears every RISC-V ISA extension via > u-boot-riscv-isa_clear.cfg, then conditionally re-adds a fragment per > TUNE_FEATURES bit: a, f, d, b/zbb, zicbom. There is no line for c, even > though u-boot-riscv-isa_c.cfg (CONFIG_RISCV_ISA_C=y) already ships in > the recipe. So for any tune with c in TUNE_FEATURES (e.g. the default > rv64gc/rv32gc tunes), compressed instructions stay disabled after the > clear fragment runs, and .config ends up with: > > # CONFIG_RISCV_ISA_C is not set > > Building without RVC noticeably inflates .text: on qemuriscv64 > (tune-riscv64, rv64gc), the resulting u-boot binary is 1312625 bytes of > .text without the fix vs 1082853 bytes with CONFIG_RISCV_ISA_C=y > correctly set, 229772 bytes (17.5%) smaller. On size-constrained > RISC-V SPL targets this .text growth can make the SPL .bss VMA overlap > the .text VMA and fail the link. > > Add the missing "c" mapping line, mirroring the existing per-extension > entries (a, f, d, b/zbb, zicbom) already present in SRC_URI_RISCV. > > Tested on oe-core master, MACHINE=qemuriscv64, via the > oe-nodistro-master bitbake-setup config: > > bitbake -c cleansstate u-boot && bitbake u-boot > grep CONFIG_RISCV_ISA_C .../u-boot/2026.04/build/.config > # before: "# CONFIG_RISCV_ISA_C is not set" > # after: "CONFIG_RISCV_ISA_C=y" > > do_package_qa passes both before and after; only the ISA config and > resulting .text size change. > > Fixes: de890297b392 ("u-boot: Dynamic RISC-V ISA configuration") > > AI-Generated: Uses Cursor > > Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com> > Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> > Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org> > --- > v2: Fix Fixes: tag, it pointed to the wrong commit (cd9e7304481b, > "u-boot: Overhaul UBOOT_CONFIG flow") instead of the commit that > actually introduced SRC_URI_RISCV (de890297b392, "u-boot: Dynamic > RISC-V ISA configuration"). > > meta/recipes-bsp/u-boot/u-boot_2026.01.bb | 1 + > 1 file changed, 1 insertion(+) Thanks, since it does not change the patch content, I directly replaced the v2 into my branch. Regards,
diff --git a/meta/recipes-bsp/u-boot/u-boot_2026.01.bb b/meta/recipes-bsp/u-boot/u-boot_2026.01.bb index ac1b0b9b2b..6d9bc126a1 100644 --- a/meta/recipes-bsp/u-boot/u-boot_2026.01.bb +++ b/meta/recipes-bsp/u-boot/u-boot_2026.01.bb @@ -14,6 +14,7 @@ SRC_URI_RISCV = "\ ${@bb.utils.contains ("TUNE_FEATURES", "a", "file://u-boot-riscv-isa_a.cfg", "", d)} \ ${@bb.utils.contains ("TUNE_FEATURES", "f", "file://u-boot-riscv-isa_f.cfg", "", d)} \ ${@bb.utils.contains ("TUNE_FEATURES", "d", "file://u-boot-riscv-isa_d.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "c", "file://u-boot-riscv-isa_c.cfg", "", d)} \ ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "file://u-boot-riscv-isa_zbb.cfg", "", d)} \ ${@bb.utils.contains ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \ "
SRC_URI_RISCV clears every RISC-V ISA extension via u-boot-riscv-isa_clear.cfg, then conditionally re-adds a fragment per TUNE_FEATURES bit: a, f, d, b/zbb, zicbom. There is no line for c, even though u-boot-riscv-isa_c.cfg (CONFIG_RISCV_ISA_C=y) already ships in the recipe. So for any tune with c in TUNE_FEATURES (e.g. the default rv64gc/rv32gc tunes), compressed instructions stay disabled after the clear fragment runs, and .config ends up with: # CONFIG_RISCV_ISA_C is not set Building without RVC noticeably inflates .text: on qemuriscv64 (tune-riscv64, rv64gc), the resulting u-boot binary is 1312625 bytes of .text without the fix vs 1082853 bytes with CONFIG_RISCV_ISA_C=y correctly set, 229772 bytes (17.5%) smaller. On size-constrained RISC-V SPL targets this .text growth can make the SPL .bss VMA overlap the .text VMA and fail the link. Add the missing "c" mapping line, mirroring the existing per-extension entries (a, f, d, b/zbb, zicbom) already present in SRC_URI_RISCV. Tested on oe-core master, MACHINE=qemuriscv64, via the oe-nodistro-master bitbake-setup config: bitbake -c cleansstate u-boot && bitbake u-boot grep CONFIG_RISCV_ISA_C .../u-boot/2026.04/build/.config # before: "# CONFIG_RISCV_ISA_C is not set" # after: "CONFIG_RISCV_ISA_C=y" do_package_qa passes both before and after; only the ISA config and resulting .text size change. Fixes: de890297b392 ("u-boot: Dynamic RISC-V ISA configuration") AI-Generated: Uses Cursor Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com> Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org> --- v2: Fix Fixes: tag, it pointed to the wrong commit (cd9e7304481b, "u-boot: Overhaul UBOOT_CONFIG flow") instead of the commit that actually introduced SRC_URI_RISCV (de890297b392, "u-boot: Dynamic RISC-V ISA configuration"). meta/recipes-bsp/u-boot/u-boot_2026.01.bb | 1 + 1 file changed, 1 insertion(+)