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[v4] opensbi: bump to 1.8

Message ID 20260108101609.60948-1-thomas.perrot@bootlin.com
State Under Review
Headers show
Series [v4] opensbi: bump to 1.8 | expand

Commit Message

Thomas Perrot Jan. 8, 2026, 10:16 a.m. UTC 
From: Thomas Perrot <thomas.perrot@bootlin.com>

This release has:
- Safe and reverse list iteration
- Stack protector support
- Allocate heap housekeeping nodes dynamically
- IPI device ratings
- Andes QiLai SoC support
- SpacemiT K1 SoC support
- ESWIN Computing EIC7700 SoC support
- Moved Ariane and Openpiton to generic platform
- SiFive CLINT v2 support
- Simple FDT based cache library
- SiFive PL2 cache controller driver
- SiFive Extensible Cache (EC) driver
- SiFive TMC0 based HSM driver
- SiFive SMC0 based system suspend driver
- MPXY RPMI mailbox driver for voltage service group
- MPXY RPMI mailbox driver for device power service group
- MPXY RPMI mailbox driver for performance service group
- HART protection abstraction

Overall, this release has various domain related improvements and
also adds multiple platform support.

Additionally, enable PMP support on QEMU using rva23s64, as PMP is
disabled by default, which causes the hart isolation configuration
to fail [1].

[1] https://lists.nongnu.org/archive/html/qemu-riscv/2026-01/msg00048.html

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

---
    Changes in v4:
    - Fix commit message (again, sorry)
    Changes in v3:
    - Fix commit message
    Changes in v2:
    - Enable PMP support on Qemu with rva23
    - Include tag=v${PV} in the SRC_URI
    - Link to v1: https://lists.openembedded.org/g/openembedded-core/message/228935
---
 meta/conf/machine/include/riscv/qemuriscv.inc               | 2 +-
 meta/recipes-bsp/opensbi/{opensbi_1.7.bb => opensbi_1.8.bb} | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
 rename meta/recipes-bsp/opensbi/{opensbi_1.7.bb => opensbi_1.8.bb} (96%)
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Patch

diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc b/meta/conf/machine/include/riscv/qemuriscv.inc
index b755d32c9d1a..bac376ce5a80 100644
--- a/meta/conf/machine/include/riscv/qemuriscv.inc
+++ b/meta/conf/machine/include/riscv/qemuriscv.inc
@@ -27,7 +27,7 @@  UBOOT_ENTRYPOINT:riscv64 = "0x80200000"
 # qemuboot options
 QB_SMP ?= "-smp 4"
 QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi"
-QB_CPU:riscv64 ?= "-cpu rva23s64"
+QB_CPU:riscv64 ?= "-cpu rva23s64,pmp=true"
 QB_MACHINE = "-machine virt"
 QB_DEFAULT_BIOS = "fw_jump.elf"
 QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no"
diff --git a/meta/recipes-bsp/opensbi/opensbi_1.7.bb b/meta/recipes-bsp/opensbi/opensbi_1.8.bb
similarity index 96%
rename from meta/recipes-bsp/opensbi/opensbi_1.7.bb
rename to meta/recipes-bsp/opensbi/opensbi_1.8.bb
index a460062e9398..5352c01d6693 100644
--- a/meta/recipes-bsp/opensbi/opensbi_1.7.bb
+++ b/meta/recipes-bsp/opensbi/opensbi_1.8.bb
@@ -8,8 +8,8 @@  require opensbi-payloads.inc
 
 inherit deploy
 
-SRCREV = "a32a91069119e7a5aa31e6bc51d5e00860be3d80"
-SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https"
+SRCREV = "e7fa66c2160ec139de1853a00f669c09320a9256"
+SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https;tag=v${PV}"
 
 TARGET_DBGSRC_DIR = "/share/opensbi/*/generic/firmware/"