| Message ID | 20260107093231.59163-1-thomas.perrot@bootlin.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [v2] opensbi: bump to 1.8 | expand |
On Wed, Jan 7, 2026 at 1:33 AM Thomas Perrot via lists.openembedded.org <thomas.perrot=bootlin.com@lists.openembedded.org> wrote: > From: Thomas Perrot <thomas.perrot@bootlin.com> > > This release has: > - Safe and reverse list iteration > - Stack protector support > - Allocate heap housekeeping nodes dynamically > - IPI device ratings > - Andes QiLai SoC support > - SpacemiT K1 SoC support > - ESWIN Computing EIC7700 SoC support > - Moved Ariane and Openpiton to generic platform > - SiFive CLINT v2 support > - Simple FDT based cache library > - SiFive PL2 cache controller driver > - SiFive Extensible Cache (EC) driver > - SiFive TMC0 based HSM driver > - SiFive SMC0 based system suspend driver > - MPXY RPMI mailbox driver for voltage service group > - MPXY RPMI mailbox driver for device power service group > - MPXY RPMI mailbox driver for performance service group > - HART protection abstraction > > Overall, this release has various domain related improvements and > also adds multiple platform support. > > Also switch Qemu -cpu parameter to rv64 because rva23s64 and rva22s64 > profiles lack PMP entries, causing hart isolation configuration to fail > [1]. > > [1] https://lists.nongnu.org/archive/html/qemu-riscv/2026-01/msg00048.html > > Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com> > > --- > Changes in v2: > - Enable PMP support on Qemu with rva23 > - Include tag=v${PV} in the SRC_URI > - Link to v1: > https://lists.openembedded.org/g/openembedded-core/message/228935 > --- > meta/conf/machine/include/riscv/qemuriscv.inc | 2 +- > meta/recipes-bsp/opensbi/{opensbi_1.7.bb => opensbi_1.8.bb} | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > rename meta/recipes-bsp/opensbi/{opensbi_1.7.bb => opensbi_1.8.bb} (97%) > > diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc > b/meta/conf/machine/include/riscv/qemuriscv.inc > index b755d32c9d1a..45fcf36e62d9 100644 > --- a/meta/conf/machine/include/riscv/qemuriscv.inc > +++ b/meta/conf/machine/include/riscv/qemuriscv.inc > @@ -27,7 +27,7 @@ UBOOT_ENTRYPOINT:riscv64 = "0x80200000" > # qemuboot options > QB_SMP ?= "-smp 4" > QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi" > -QB_CPU:riscv64 ?= "-cpu rva23s64" > +QB_CPU:riscv64 ?= "-cpu rv64" > Do we still need this after enabling PMP > QB_MACHINE = "-machine virt" > QB_DEFAULT_BIOS = "fw_jump.elf" > QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no" > diff --git a/meta/recipes-bsp/opensbi/opensbi_1.7.bb > b/meta/recipes-bsp/opensbi/opensbi_1.8.bb > similarity index 97% > rename from meta/recipes-bsp/opensbi/opensbi_1.7.bb > rename to meta/recipes-bsp/opensbi/opensbi_1.8.bb > index a460062e9398..f2d3e9f20082 100644 > --- a/meta/recipes-bsp/opensbi/opensbi_1.7.bb > +++ b/meta/recipes-bsp/opensbi/opensbi_1.8.bb > @@ -8,7 +8,7 @@ require opensbi-payloads.inc > > inherit deploy > > -SRCREV = "a32a91069119e7a5aa31e6bc51d5e00860be3d80" > +SRCREV = "e7fa66c2160ec139de1853a00f669c09320a9256" > SRC_URI = "git:// > github.com/riscv/opensbi.git;branch=master;protocol=https" > > TARGET_DBGSRC_DIR = "/share/opensbi/*/generic/firmware/" > -- > 2.52.0 > > > -=-=-=-=-=-=-=-=-=-=-=- > Links: You receive all messages sent to this group. > View/Reply Online (#228967): > https://lists.openembedded.org/g/openembedded-core/message/228967 > Mute This Topic: https://lists.openembedded.org/mt/117131548/1997914 > Group Owner: openembedded-core+owner@lists.openembedded.org > Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub [ > raj.khem@gmail.com] > -=-=-=-=-=-=-=-=-=-=-=- > >
On Wed, Jan 7, 2026 at 10:33 PM Thomas Perrot via lists.openembedded.org <thomas.perrot=bootlin.com@lists.openembedded.org> wrote: > > From: Thomas Perrot <thomas.perrot@bootlin.com> > > This release has: > - Safe and reverse list iteration > - Stack protector support > - Allocate heap housekeeping nodes dynamically > - IPI device ratings > - Andes QiLai SoC support > - SpacemiT K1 SoC support > - ESWIN Computing EIC7700 SoC support > - Moved Ariane and Openpiton to generic platform > - SiFive CLINT v2 support > - Simple FDT based cache library > - SiFive PL2 cache controller driver > - SiFive Extensible Cache (EC) driver > - SiFive TMC0 based HSM driver > - SiFive SMC0 based system suspend driver > - MPXY RPMI mailbox driver for voltage service group > - MPXY RPMI mailbox driver for device power service group > - MPXY RPMI mailbox driver for performance service group > - HART protection abstraction > > Overall, this release has various domain related improvements and > also adds multiple platform support. > > Also switch Qemu -cpu parameter to rv64 because rva23s64 and rva22s64 > profiles lack PMP entries, causing hart isolation configuration to fail [1]. > > [1] https://lists.nongnu.org/archive/html/qemu-riscv/2026-01/msg00048.html > > Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com> > > --- > Changes in v2: > - Enable PMP support on Qemu with rva23 > - Include tag=v${PV} in the SRC_URI > - Link to v1: https://lists.openembedded.org/g/openembedded-core/message/228935 > --- > meta/conf/machine/include/riscv/qemuriscv.inc | 2 +- > meta/recipes-bsp/opensbi/{opensbi_1.7.bb => opensbi_1.8.bb} | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > rename meta/recipes-bsp/opensbi/{opensbi_1.7.bb => opensbi_1.8.bb} (97%) > > diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc b/meta/conf/machine/include/riscv/qemuriscv.inc > index b755d32c9d1a..45fcf36e62d9 100644 > --- a/meta/conf/machine/include/riscv/qemuriscv.inc > +++ b/meta/conf/machine/include/riscv/qemuriscv.inc > @@ -27,7 +27,7 @@ UBOOT_ENTRYPOINT:riscv64 = "0x80200000" > # qemuboot options > QB_SMP ?= "-smp 4" > QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi" > -QB_CPU:riscv64 ?= "-cpu rva23s64" > +QB_CPU:riscv64 ?= "-cpu rv64" > QB_MACHINE = "-machine virt" > QB_DEFAULT_BIOS = "fw_jump.elf" > QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no" > diff --git a/meta/recipes-bsp/opensbi/opensbi_1.7.bb b/meta/recipes-bsp/opensbi/opensbi_1.8.bb > similarity index 97% > rename from meta/recipes-bsp/opensbi/opensbi_1.7.bb > rename to meta/recipes-bsp/opensbi/opensbi_1.8.bb > index a460062e9398..f2d3e9f20082 100644 > --- a/meta/recipes-bsp/opensbi/opensbi_1.7.bb > +++ b/meta/recipes-bsp/opensbi/opensbi_1.8.bb > @@ -8,7 +8,7 @@ require opensbi-payloads.inc > > inherit deploy > > -SRCREV = "a32a91069119e7a5aa31e6bc51d5e00860be3d80" > +SRCREV = "e7fa66c2160ec139de1853a00f669c09320a9256" > SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https" SRC_URI change is missing in v2 > TARGET_DBGSRC_DIR = "/share/opensbi/*/generic/firmware/" > -- > 2.52.0 > > > -=-=-=-=-=-=-=-=-=-=-=- > Links: You receive all messages sent to this group. > View/Reply Online (#228967): https://lists.openembedded.org/g/openembedded-core/message/228967 > Mute This Topic: https://lists.openembedded.org/mt/117131548/3619737 > Group Owner: openembedded-core+owner@lists.openembedded.org > Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub [ankur.tyagi85@gmail.com] > -=-=-=-=-=-=-=-=-=-=-=- >
Hello, On Thu, 2026-01-08 at 06:58 +1300, Ankur Tyagi wrote: > On Wed, Jan 7, 2026 at 10:33 PM Thomas Perrot via > lists.openembedded.org > <thomas.perrot=bootlin.com@lists.openembedded.org> wrote: > > > > From: Thomas Perrot <thomas.perrot@bootlin.com> > > > > This release has: > > - Safe and reverse list iteration > > - Stack protector support > > - Allocate heap housekeeping nodes dynamically > > - IPI device ratings > > - Andes QiLai SoC support > > - SpacemiT K1 SoC support > > - ESWIN Computing EIC7700 SoC support > > - Moved Ariane and Openpiton to generic platform > > - SiFive CLINT v2 support > > - Simple FDT based cache library > > - SiFive PL2 cache controller driver > > - SiFive Extensible Cache (EC) driver > > - SiFive TMC0 based HSM driver > > - SiFive SMC0 based system suspend driver > > - MPXY RPMI mailbox driver for voltage service group > > - MPXY RPMI mailbox driver for device power service group > > - MPXY RPMI mailbox driver for performance service group > > - HART protection abstraction > > > > Overall, this release has various domain related improvements and > > also adds multiple platform support. > > > > Also switch Qemu -cpu parameter to rv64 because rva23s64 and > > rva22s64 > > profiles lack PMP entries, causing hart isolation configuration to > > fail [1]. > > > > [1] > > https://lists.nongnu.org/archive/html/qemu-riscv/2026-01/msg00048.html > > > > Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com> > > > > --- > > Changes in v2: > > - Enable PMP support on Qemu with rva23 > > - Include tag=v${PV} in the SRC_URI > > - Link to v1: > > https://lists.openembedded.org/g/openembedded-core/message/228935 > > --- > > meta/conf/machine/include/riscv/qemuriscv.inc | 2 +- > > meta/recipes-bsp/opensbi/{opensbi_1.7.bb => opensbi_1.8.bb} | 2 +- > > 2 files changed, 2 insertions(+), 2 deletions(-) > > rename meta/recipes-bsp/opensbi/{opensbi_1.7.bb => opensbi_1.8.bb} > > (97%) > > > > diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc > > b/meta/conf/machine/include/riscv/qemuriscv.inc > > index b755d32c9d1a..45fcf36e62d9 100644 > > --- a/meta/conf/machine/include/riscv/qemuriscv.inc > > +++ b/meta/conf/machine/include/riscv/qemuriscv.inc > > @@ -27,7 +27,7 @@ UBOOT_ENTRYPOINT:riscv64 = "0x80200000" > > # qemuboot options > > QB_SMP ?= "-smp 4" > > QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi" > > -QB_CPU:riscv64 ?= "-cpu rva23s64" > > +QB_CPU:riscv64 ?= "-cpu rv64" > > QB_MACHINE = "-machine virt" > > QB_DEFAULT_BIOS = "fw_jump.elf" > > QB_TAP_OPT = "-netdev > > tap,id=net0,ifname=@TAP@,script=no,downscript=no" > > diff --git a/meta/recipes-bsp/opensbi/opensbi_1.7.bb > > b/meta/recipes-bsp/opensbi/opensbi_1.8.bb > > similarity index 97% > > rename from meta/recipes-bsp/opensbi/opensbi_1.7.bb > > rename to meta/recipes-bsp/opensbi/opensbi_1.8.bb > > index a460062e9398..f2d3e9f20082 100644 > > --- a/meta/recipes-bsp/opensbi/opensbi_1.7.bb > > +++ b/meta/recipes-bsp/opensbi/opensbi_1.8.bb > > @@ -8,7 +8,7 @@ require opensbi-payloads.inc > > > > inherit deploy > > > > -SRCREV = "a32a91069119e7a5aa31e6bc51d5e00860be3d80" > > +SRCREV = "e7fa66c2160ec139de1853a00f669c09320a9256" > > SRC_URI = > > "git://github.com/riscv/opensbi.git;branch=master;protocol=https" > > SRC_URI change is missing in v2 > Sorry, I pushed a v4 [1], the patch should be good now. [1] https://lists.openembedded.org/mt/117150136/5443093 Kind regards, Thomas Perrot > > TARGET_DBGSRC_DIR = "/share/opensbi/*/generic/firmware/" > > -- > > 2.52.0 > > > > > > -=-=-=-=-=-=-=-=-=-=-=- > > Links: You receive all messages sent to this group. > > View/Reply Online (#228967): > > https://lists.openembedded.org/g/openembedded-core/message/228967 > > Mute This Topic: > > https://lists.openembedded.org/mt/117131548/3619737 > > Group Owner: openembedded-core+owner@lists.openembedded.org > > Unsubscribe: > > https://lists.openembedded.org/g/openembedded-core/unsub [ > > ankur.tyagi85@gmail.com] > > -=-=-=-=-=-=-=-=-=-=-=- > >
diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc b/meta/conf/machine/include/riscv/qemuriscv.inc index b755d32c9d1a..45fcf36e62d9 100644 --- a/meta/conf/machine/include/riscv/qemuriscv.inc +++ b/meta/conf/machine/include/riscv/qemuriscv.inc @@ -27,7 +27,7 @@ UBOOT_ENTRYPOINT:riscv64 = "0x80200000" # qemuboot options QB_SMP ?= "-smp 4" QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi" -QB_CPU:riscv64 ?= "-cpu rva23s64" +QB_CPU:riscv64 ?= "-cpu rv64" QB_MACHINE = "-machine virt" QB_DEFAULT_BIOS = "fw_jump.elf" QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no" diff --git a/meta/recipes-bsp/opensbi/opensbi_1.7.bb b/meta/recipes-bsp/opensbi/opensbi_1.8.bb similarity index 97% rename from meta/recipes-bsp/opensbi/opensbi_1.7.bb rename to meta/recipes-bsp/opensbi/opensbi_1.8.bb index a460062e9398..f2d3e9f20082 100644 --- a/meta/recipes-bsp/opensbi/opensbi_1.7.bb +++ b/meta/recipes-bsp/opensbi/opensbi_1.8.bb @@ -8,7 +8,7 @@ require opensbi-payloads.inc inherit deploy -SRCREV = "a32a91069119e7a5aa31e6bc51d5e00860be3d80" +SRCREV = "e7fa66c2160ec139de1853a00f669c09320a9256" SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https" TARGET_DBGSRC_DIR = "/share/opensbi/*/generic/firmware/"