diff mbox series

opensbi: bump to 1.5

Message ID 20240701113625.2379263-1-thomas.perrot@bootlin.com
State New
Headers show
Series opensbi: bump to 1.5 | expand

Commit Message

Thomas Perrot July 1, 2024, 11:36 a.m. UTC 
From: Thomas Perrot <thomas.perrot@bootlin.com>

This release has:
- SBI debug triggers (DBTR) extension (Experimental)
- Support to specify coldboot harts in DT
- Relocatable FW_JUMP_ADDR and FW_JUMP_FDT_ADDR
- Smcsrind and Smcdeleg extensions support
- SBIUnit testing framework
- Initial domain context management support
- Platform specific load/store emulation callbacks
-  New trap context
- Improved sbi_trap_error() to dump state in a nested trap
- SBI supervisor software events (SSE) extension (Experimental)
- Simplified wait_for_coldboot() implementation
- Early wakeup of non-coldboot HART in the coldboot path
- Sophgo CV18XX/SG200X series support
- APLIC delegation DT property fix
- Svade and Svadu extensions support
- SBI firmware features (FWFT) extension (Experimental)

Overall, this release mainly adds more ISA extensions, SBI
extensions and other improvements.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
---
 meta/recipes-bsp/opensbi/{opensbi_1.4.bb => opensbi_1.5.bb} | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
 rename meta/recipes-bsp/opensbi/{opensbi_1.4.bb => opensbi_1.5.bb} (91%)
diff mbox series

Patch

diff --git a/meta/recipes-bsp/opensbi/opensbi_1.4.bb b/meta/recipes-bsp/opensbi/opensbi_1.5.bb
similarity index 91%
rename from meta/recipes-bsp/opensbi/opensbi_1.4.bb
rename to meta/recipes-bsp/opensbi/opensbi_1.5.bb
index cf37a411766b..6b31d15a051b 100644
--- a/meta/recipes-bsp/opensbi/opensbi_1.4.bb
+++ b/meta/recipes-bsp/opensbi/opensbi_1.5.bb
@@ -8,14 +8,15 @@  require opensbi-payloads.inc
 
 inherit autotools-brokensep deploy
 
-SRCREV = "a2b255b88918715173942f2c5e1f97ac9e90c877"
+SRCREV = "455de672dd7c2aa1992df54dfb08dc11abbc1b1a"
 SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https"
 
 S = "${WORKDIR}/git"
 
 TARGET_CC_ARCH += "${LDFLAGS}"
 
-EXTRA_OEMAKE += "PLATFORM=${RISCV_SBI_PLAT} I=${D} FW_PIC=y CLANG_TARGET= "
+RISCV_SBI_FW_TEXT_START ??= "0x80000000"
+EXTRA_OEMAKE += "PLATFORM=${RISCV_SBI_PLAT} I=${D} FW_TEXT_START=${RISCV_SBI_FW_TEXT_START}"
 # If RISCV_SBI_PAYLOAD is set then include it as a payload
 EXTRA_OEMAKE:append = " ${@riscv_get_extra_oemake_image(d)}"
 EXTRA_OEMAKE:append = " ${@riscv_get_extra_oemake_fdt(d)}"