@@ -247,12 +247,6 @@ musca-b1:
musca-s1:
extends: .build
-n1sdp:
- extends: .build
- parallel:
- matrix:
- - TESTING: [none, n1sdp-ts, n1sdp-optee, tftf]
-
pending-updates:
extends: .setup
artifacts:
@@ -8,7 +8,7 @@ This repository contains the Arm layers for OpenEmbedded.
* meta-arm-bsp
- This layer contains machines for Arm reference platforms, for example FVP Base, N1SDP, and Juno.
+ This layer contains machines for Arm reference platforms, for example FVP Base, Corstone1000, and Juno.
* meta-arm-toolchain
deleted file mode 100644
@@ -1,14 +0,0 @@
-# yaml-language-server: $schema=https://raw.githubusercontent.com/siemens/kas/master/kas/schema-kas.json
-
-header:
- version: 14
-
-# Config specific for the optee-xtests
-local_conf_header:
- optee-test: |
- # Include ARM FFA
- MACHINE_FEATURES:append = " arm-ffa"
- # Include trusted services
- TEST_SUITES:append = " trusted_services"
- # Include Optee xtests
- IMAGE_INSTALL:append = " optee-test"
deleted file mode 100644
@@ -1,16 +0,0 @@
-# yaml-language-server: $schema=https://raw.githubusercontent.com/siemens/kas/master/kas/schema-kas.json
-
-header:
- version: 14
- includes:
- - ci/meta-openembedded.yml
-
-local_conf_header:
- trusted_services: |
- TEST_SUITES:append = " trusted_services"
- # Include TS Crypto, TS Protected Storage, TS Internal and Trusted Storage SPs into optee-os image
- MACHINE_FEATURES:append = " arm-ffa ts-crypto ts-storage ts-its"
- # Include TS demo/test tools into image
- IMAGE_INSTALL:append = " packagegroup-ts-tests"
- # Include TS PSA Arch tests into image
- IMAGE_INSTALL:append = " packagegroup-ts-tests-psa"
deleted file mode 100644
@@ -1,12 +0,0 @@
-# yaml-language-server: $schema=https://raw.githubusercontent.com/siemens/kas/master/kas/schema-kas.json
-
-header:
- version: 14
- includes:
- - ci/base.yml
-
-machine: n1sdp
-
-local_conf_header:
- unsupported_trusted_services: |
- MACHINE_FEATURES:remove = "ts-smm-gateway"
@@ -37,13 +37,11 @@ Other steps depend on your machine/platform definition:
2. optee-os might require platform specific OP-TEE build parameters (for example what SEL the SPM Core is implemented at).
You can find examples in `meta-arm/recipes-security/optee/optee-os_%.bbappend` for qemuarm64-secureboot machine
- and in `meta-arm-bsp/recipes-security/optee/optee-os-n1sdp.inc` and `meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc`
- for N1SDP and Corstone1000 platforms accordingly.
+ and in `meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc` for the Corstone1000 platform.
3. trusted-firmware-a might require platform specific TF-A build parameters (SPD and SPMC details on the platform).
See `meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a_%.bbappend` for qemuarm64-secureboot machine
- and in `meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-n1sdp.inc` and
- `meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc` for N1SDP and Corstone1000 platforms.
+ and in `meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc` for theCorstone1000 platform.
4. Trusted Services supports an SPMC agonistic binary format. To build SPs to this format the `TS_ENV` variable is to be
set to `sp`. The resulting SP binaries should be able to boot under any FF-A v1.1 compliant SPMC implementation.
deleted file mode 100644
@@ -1,51 +0,0 @@
-# Configuration for Arm N1SDP development board
-
-#@TYPE: Machine
-#@NAME: N1SDP machine
-#@DESCRIPTION: Machine configuration for N1SDP
-
-require conf/machine/include/arm/armv8-2a/tune-neoversen1.inc
-
-KERNEL_IMAGETYPE = "Image"
-
-IMAGE_FSTYPES += "wic wic.gz wic.bmap tar.bz2 ext4"
-
-SERIAL_CONSOLES = "115200;ttyAMA0"
-
-# Set default WKS
-WKS_FILE ?= "n1sdp-efidisk.wks"
-IMAGE_EFI_BOOT_FILES ?= "n1sdp-multi-chip.dtb n1sdp-single-chip.dtb"
-WKS_FILE_DEPENDS:append = " ${EXTRA_IMAGEDEPENDS}"
-
-# Use kernel provided by yocto
-PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto"
-PREFERRED_VERSION_linux-yocto ?= "6.6%"
-
-# RTL8168E Gigabit Ethernet Controller is attached to the PCIe interface
-MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "linux-firmware-rtl8168"
-
-# TF-A
-EXTRA_IMAGEDEPENDS += "trusted-firmware-a"
-TFA_PLATFORM = "n1sdp"
-PREFERRED_VERSION_trusted-firmware-a ?= "2.10.%"
-PREFERRED_VERSION_tf-a-tests ?= "2.10.%"
-
-# SCP
-EXTRA_IMAGEDEPENDS += "virtual/control-processor-firmware"
-
-#UEFI EDK2 firmware
-EXTRA_IMAGEDEPENDS += "edk2-firmware"
-PREFERRED_VERSION_edk2-firmware ?= "202311"
-
-#optee
-PREFERRED_VERSION_optee-os ?= "4.1.%"
-PREFERRED_VERSION_optee-os-tadevkit ?= "4.1.%"
-PREFERRED_VERSION_optee-test ?= "4.1.%"
-PREFERRED_VERSION_optee-client ?= "4.1.%"
-
-#grub-efi
-EFI_PROVIDER ?= "grub-efi"
-MACHINE_FEATURES += "efi"
-
-# SD-Card firmware
-EXTRA_IMAGEDEPENDS += "sdcard-image-n1sdp"
deleted file mode 100644
@@ -1,78 +0,0 @@
-# N1SDP Development Platform Support in meta-arm-bsp
-
-## Overview
-The N1SDP provides access to the Arm Neoverse N1 SoC. The N1SDP enables software development for key enterprise technology
-and general Arm software development. The N1SDP consists of the N1 board containing the N1 SoC.
-The N1 SoC contains two dual-core Arm Neoverse N1 processor clusters.
-
-The system demonstrates Arm technology in the context of Cache-Coherent Interconnect for Accelerators (CCIX) protocol by:
-
-- Running coherent traffic between the N1 SoC and an accelerator card.
-- Coherent communication between two N1 SoCs.
-- Enabling development of CCIX-enabled FPGA accelerators.
-
-Further information on N1SDP can be found at
-https://community.arm.com/developer/tools-software/oss-platforms/w/docs/458/neoverse-n1-sdp
-
-## Configuration:
-In the local.conf file, MACHINE should be set as follow:
-MACHINE ?= "n1sdp"
-
-## Building
-```bash$ bitbake core-image-minimal```
-
-## Running
-
-# Update Firmware on SD card:
-
-(*) To use n1sdp board in single chip mode, flash:
- n1sdp-board-firmware_primary.tar.gz firmware.
-
-(*) To use n1sdp board in multi chip mode, flash:
- n1sdp-board-firmware_primary.tar.gz firmware to primary board,
- n1sdp-board-firmware_secondary.tar.gz firmware to secondary board.
-
-The SD card content is generated during the build here:
- tmp/deploy/images/n1sdp/n1sdp-board-firmware_primary.tar.gz
- tmp/deploy/images/n1sdp/n1sdp-board-firmware_secondary.tar.gz
-
-
-Its content must be written on the N1SDP firmware SD card.
-To do this:
-- insert the sdcard of the N1SDP in an SD card reader and mount it:
-```bash$ sudo mount /dev/sdx1 /mnt```
-(replace sdx by the device of the SD card)
-
-- erase its content and put the new one:
-```bash$ sudo rm -rf /mnt/*```
-```bash$ sudo tar --no-same-owner -xzf tmp/deploy/images/n1sdp/n1sdp-board-firmware_primary.tar.gz -C /mnt/```
-```bash$ sudo umount /mnt```
-
-- reinsert the SD card in the N1SDP board
-
-Firmware tarball contains iofpga configuration files, scp and uefi binaries.
-
-**NOTE**:
-If the N1SDP board was manufactured after November 2019 (Serial Number greater
-than 36253xxx), a different PMIC firmware image must be used to prevent
-potential damage to the board. More details can be found in [1].
-The `MB/HBI0316A/io_v123f.txt` file located in the microSD needs to be updated.
-To update it, set the PMIC image (300k_8c2.bin) to be used in the newer models
-by running the following commands on your host PC:
-
- $ sudo umount /dev/sdx1
- $ sudo mount /dev/sdx1 /mnt
- $ sudo sed -i '/^MBPMIC: pms_0V85.bin/s/^/;/g' /mnt/MB/HBI0316A/io_v123f.txt
- $ sudo sed -i '/^;MBPMIC: 300k_8c2.bin/s/^;//g' /mnt/MB/HBI0316A/io_v123f.txt
- $ sudo umount /mnt
-
-# Prepare an USB hard drive:
-
-Grub boot partition is placed on first partition of the *.wic image,
-Linux root file system is placed on the second partition of the *.wic image:
- tmp/deploy/images/n1sdp/core-image-minimal-n1sdp.wic
-
-This *.wic image should be copied to USB stick with simple dd call.
-
-
-[1]: https://community.arm.com/developer/tools-software/oss-platforms/w/docs/604/notice-potential-damage-to-n1sdp-boards-if-using-latest-firmware-release
@@ -16,4 +16,4 @@
*A summary of how to deploy or execute the image*
-*For example, an overview of the N1SDP SD structure, or FVP arguments*
+*For example, an overview of FVP arguments*
deleted file mode 100644
@@ -1,37 +0,0 @@
-SUMMARY = "Board Firmware binaries for N1SDP"
-SECTION = "firmware"
-
-LICENSE = "STM-SLA0044-Rev5"
-LIC_FILES_CHKSUM = "file://LICENSES/MB/STM.TXT;md5=1b74d8c842307d03c116f2d71cbf868a"
-
-inherit deploy
-
-INHIBIT_DEFAULT_DEPS = "1"
-
-PACKAGE_ARCH = "${MACHINE_ARCH}"
-COMPATIBLE_MACHINE = "n1sdp"
-
-SRC_URI = "git://git.gitlab.arm.com/arm-reference-solutions/board-firmware.git;protocol=https;branch=n1sdp"
-
-SRCREV = "70ba494265eee76747faff38264860c19e214540"
-PV .= "+git"
-
-S = "${WORKDIR}/git"
-
-INSTALL_DIR = "/n1sdp-board-firmware_source"
-
-do_install() {
- rm -rf ${S}/SOFTWARE
- install -d ${D}${INSTALL_DIR}
- cp -Rp --no-preserve=ownership ${S}/* ${D}${INSTALL_DIR}
-}
-
-FILES:${PN}-staticdev += " ${INSTALL_DIR}/LIB/sensor.a"
-FILES:${PN} = "${INSTALL_DIR}"
-SYSROOT_DIRS += "${INSTALL_DIR}"
-
-do_deploy() {
- install -d ${DEPLOYDIR}${INSTALL_DIR}
- cp -Rp --no-preserve=ownership ${S}/* ${DEPLOYDIR}${INSTALL_DIR}
-}
-addtask deploy after do_install before do_build
deleted file mode 100644
@@ -1,85 +0,0 @@
-SUMMARY = "Firmware image recipe for generating SD-Card artifacts."
-
-inherit deploy nopackages
-
-DEPENDS = "trusted-firmware-a \
- virtual/control-processor-firmware \
- n1sdp-board-firmware"
-
-LICENSE = "MIT"
-PACKAGE_ARCH = "${MACHINE_ARCH}"
-COMPATIBLE_MACHINE = "n1sdp"
-RM_WORK_EXCLUDE += "${PN}"
-do_configure[noexec] = "1"
-do_compile[noexec] = "1"
-do_install[noexec] = "1"
-
-FIRMWARE_DIR = "n1sdp-board-firmware_source"
-PRIMARY_DIR = "${WORKDIR}/n1sdp-board-firmware_primary"
-SECONDARY_DIR = "${WORKDIR}/n1sdp-board-firmware_secondary"
-
-SOC_BINARIES = "mcp_fw.bin scp_fw.bin mcp_rom.bin scp_rom.bin"
-
-prepare_package() {
- cd ${WORKDIR}
-
- # Master/Primary
- cp -av ${RECIPE_SYSROOT}/${FIRMWARE_DIR}/* ${PRIMARY_DIR}
- mkdir -p ${PRIMARY_DIR}/SOFTWARE/
-
- # Copy FIP binary
- cp -v ${RECIPE_SYSROOT}/firmware/fip.bin ${PRIMARY_DIR}/SOFTWARE/
-
- # Copy SOC binaries
- for f in ${SOC_BINARIES}; do
- cp -v ${RECIPE_SYSROOT}/firmware/${f} ${PRIMARY_DIR}/SOFTWARE/
- done
-
- sed -i -e 's|^C2C_ENABLE.*|C2C_ENABLE: TRUE ;C2C enable TRUE/FALSE|' \
- ${PRIMARY_DIR}/MB/HBI0316A/io_v123f.txt
- sed -i -e 's|^C2C_SIDE.*|C2C_SIDE: MASTER ;C2C side SLAVE/MASTER|' \
- ${PRIMARY_DIR}/MB/HBI0316A/io_v123f.txt
- sed -i -e 's|.*SOCCON: 0x1170.*PLATFORM_CTRL.*|SOCCON: 0x1170 0x00000100 ;SoC SCC PLATFORM_CTRL|' \
- ${PRIMARY_DIR}/MB/HBI0316A/io_v123f.txt
-
- # Update load address for trusted boot
- sed -i -e '/^IMAGE4ADDRESS:/ s|0x60200000|0x64200000|' ${PRIMARY_DIR}/MB/HBI0316A/images.txt
- sed -i -e '/^IMAGE4UPDATE:/ s|FORCE |SCP_AUTO|' ${PRIMARY_DIR}/MB/HBI0316A/images.txt
- sed -i -e '/^IMAGE4FILE: \\SOFTWARE\\/s|uefi.bin|fip.bin |' ${PRIMARY_DIR}/MB/HBI0316A/images.txt
-
- # Slave/Secondary
- cp -av ${RECIPE_SYSROOT}/${FIRMWARE_DIR}/* ${SECONDARY_DIR}
- mkdir -p ${SECONDARY_DIR}/SOFTWARE/
-
- # Copy SOC binaries
- for f in ${SOC_BINARIES}; do
- cp -v ${RECIPE_SYSROOT}/firmware/${f} ${SECONDARY_DIR}/SOFTWARE/
- done
-
- sed -i -e 's|^C2C_ENABLE.*|C2C_ENABLE: TRUE ;C2C enable TRUE/FALSE|' \
- ${SECONDARY_DIR}/MB/HBI0316A/io_v123f.txt
- sed -i -e 's|^C2C_SIDE.*|C2C_SIDE: SLAVE ;C2C side SLAVE/MASTER|' \
- ${SECONDARY_DIR}/MB/HBI0316A/io_v123f.txt
- sed -i -e 's|.*SOCCON: 0x1170.*PLATFORM_CTRL.*|SOCCON: 0x1170 0x00000101 ;SoC SCC PLATFORM_CTRL|' \
- ${SECONDARY_DIR}/MB/HBI0316A/io_v123f.txt
- sed -i -e '/^TOTALIMAGES:/ s|5|4|' ${SECONDARY_DIR}/MB/HBI0316A/images.txt
- sed -i -e 's|^IMAGE4|;&|' ${SECONDARY_DIR}/MB/HBI0316A/images.txt
-}
-
-do_deploy() {
- # prepare Master & Slave packages
- prepare_package
-
- for dir in ${PRIMARY_DIR} ${SECONDARY_DIR}; do
- dir_name=$(basename ${dir})
- mkdir -p ${D}/${dir_name}
- cp -av ${dir} ${D}
-
- # Compress the files
- tar -C ${D}/${dir_name} -zcvf ${DEPLOYDIR}/${dir_name}.tar.gz ./
- done
-}
-do_deploy[dirs] += "${PRIMARY_DIR} ${SECONDARY_DIR}"
-do_deploy[cleandirs] += "${PRIMARY_DIR} ${SECONDARY_DIR}"
-do_deploy[umask] = "022"
-addtask deploy after do_prepare_recipe_sysroot
deleted file mode 100644
@@ -1,35 +0,0 @@
-# N1SDP specific SCP configurations and build instructions
-
-COMPATIBLE_MACHINE:n1sdp = "n1sdp"
-
-SCP_LOG_LEVEL = "INFO"
-
-DEPENDS += "fiptool-native"
-DEPENDS += "trusted-firmware-a"
-DEPENDS += "n1sdp-board-firmware"
-
-# The n1sdp sensor library is needed for building SCP N1SDP Platform
-# https://github.com/ARM-software/SCP-firmware/tree/master/product/n1sdp
-EXTRA_OECMAKE:append = " \
- -DSCP_N1SDP_SENSOR_LIB_PATH=${RECIPE_SYSROOT}/n1sdp-board-firmware_source/LIB/sensor.a \
-"
-
-do_install:append() {
- fiptool \
- create \
- --scp-fw "${D}/firmware/scp_ramfw.bin" \
- --blob uuid=cfacc2c4-15e8-4668-82be-430a38fad705,file="${RECIPE_SYSROOT}/firmware/bl1.bin" \
- "scp_fw.bin"
-
- # This UUID is FIP_UUID_MCP_BL2 in SCP-Firmware.
- fiptool \
- create \
- --blob uuid=54464222-a4cf-4bf8-b1b6-cee7dade539e,file="${D}/firmware/mcp_ramfw.bin" \
- "mcp_fw.bin"
-
- install "scp_fw.bin" "${D}/firmware/scp_fw.bin"
- install "mcp_fw.bin" "${D}/firmware/mcp_fw.bin"
-
- ln -sf "scp_romfw.bin" "${D}/firmware/scp_rom.bin"
- ln -sf "mcp_romfw.bin" "${D}/firmware/mcp_rom.bin"
-}
@@ -3,7 +3,6 @@
MACHINE_SCP_REQUIRE ?= ""
MACHINE_SCP_REQUIRE:juno = "scp-firmware-juno.inc"
-MACHINE_SCP_REQUIRE:n1sdp = "scp-firmware-n1sdp.inc"
MACHINE_SCP_REQUIRE:sgi575 = "scp-firmware-sgi575.inc"
MACHINE_SCP_REQUIRE:tc = "scp-firmware-tc.inc"
deleted file mode 100644
@@ -1,42 +0,0 @@
-From 2d305094f8f500362079e9e7637d46129bf980e4 Mon Sep 17 00:00:00 2001
-From: Adam Johnston <adam.johnston@arm.com>
-Date: Tue, 25 Jul 2023 16:05:51 +0000
-Subject: [PATCH] n1sdp: Reserve OP-TEE memory from NWd
-
-The physical memory which is used to run OP-TEE on the N1SDP is known
-to the secure world via TOS_FW_CONFIG, but it may not be known to the
-normal world.
-
-As a precaution, explicitly reserve this memory via NT_FW_CONFIG to
-prevent the normal world from using it. This is not required on most
-platforms as the Trusted OS is run from secure RAM.
-
-Upstream-Status: Pending (not yet submitted to upstream)
-Signed-off-by: Adam Johnston <adam.johnston@arm.com>
-Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
----
- plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
-diff --git a/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts b/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts
-index da5e04ddb6..b7e2d4e86f 100644
---- a/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts
-+++ b/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts
-@@ -20,4 +20,16 @@
- local-ddr-size = <0x0>;
- remote-ddr-size = <0x0>;
- };
-+
-+ reserved-memory {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ optee@0xDE000000 {
-+ compatible = "removed-dma-pool";
-+ reg = <0x0 0xDE000000 0x0 0x02000000>;
-+ no-map;
-+ };
-+ };
- };
-\ No newline at end of file
deleted file mode 100644
@@ -1,46 +0,0 @@
-From cc0153b56d634aa80b740be5afed15bedb94a2c9 Mon Sep 17 00:00:00 2001
-From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
-Date: Tue, 23 Jan 2024 14:19:39 +0000
-Subject: [PATCH] n1sdp patch tests to skip
-
-Upstream-Status: Pending
-Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
----
- plat/arm/n1sdp/tests_to_skip.txt | 15 ++++++++++-----
- 1 file changed, 10 insertions(+), 5 deletions(-)
-
-diff --git a/plat/arm/n1sdp/tests_to_skip.txt b/plat/arm/n1sdp/tests_to_skip.txt
-index b6e87bf..1848408 100644
---- a/plat/arm/n1sdp/tests_to_skip.txt
-+++ b/plat/arm/n1sdp/tests_to_skip.txt
-@@ -11,7 +11,7 @@ SMMUv3 tests
- PSCI CPU Suspend in OSI mode
-
- # PSCI is enabled but not tested
--PSCI STAT/Stats test cases after system suspend
-+PSCI STAT
- PSCI System Suspend Validation
-
- # Disable FF-A Interrupt tests as TWDOG is not supported by TC platform
-@@ -25,9 +25,14 @@ FF-A Interrupt
- # files in TFTF, since the port was done purely to test the spectre workaround
- # performance impact. Once that was done no further work was done on the port.
-
--Timer framework Validation/Target timer to a power down cpu
--Timer framework Validation/Test scenario where multiple CPUs call same timeout
--Timer framework Validation/Stress test the timer framework
-+Timer framework Validation
- PSCI Affinity Info/Affinity info level0 powerdown
- PSCI CPU Suspend
--PSCI STAT/for valid composite state CPU suspend
-+Framework Validation/NVM serialisation
-+Framework Validation/Events API
-+Boot requirement tests
-+CPU Hotplug
-+ARM_ARCH_SVC/SMCCC_ARCH_WORKAROUND_1 test
-+ARM_ARCH_SVC/SMCCC_ARCH_WORKAROUND_2 test
-+ARM_ARCH_SVC/SMCCC_ARCH_WORKAROUND_3 test
-+FF-A Power management
-2.34.1
-
deleted file mode 100644
@@ -1,30 +0,0 @@
-From 15dab90c3cb8e7677c4f953c2269e8ee1afa01b0 Mon Oct 2 13:45:43 2023
-From: Mariam Elshakfy <mariam.elshakfy@arm.com>
-Date: Mon, 2 Oct 2023 13:45:43 +0000
-Subject: [PATCH] Modify BL32 Location to DDR4
-
-Since OP-TEE start address is changed to run
-from DDR4, this patch changes BL32 entrypoint
-to the correct one.
-
-Upstream-Status: Pending (not yet submitted to upstream)
-Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
----
- plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts b/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts
-index ed870803c..797dfe3a4 100644
---- a/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts
-+++ b/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts
-@@ -22,8 +22,8 @@
- maj_ver = <0x1>;
- min_ver = <0x0>;
- exec_state = <0x0>;
-- load_address = <0x0 0x08000000>;
-- entrypoint = <0x0 0x08000000>;
-+ load_address = <0x0 0xDE000000>;
-+ entrypoint = <0x0 0xDE000000>;
- binary_size = <0x2000000>;
- };
-
deleted file mode 100644
@@ -1,28 +0,0 @@
-From 9a1d11b9fbadf740c73aee6dca4fd0370b38e4a8 Tue Oct 3 13:49:13 2023
-From: Mariam Elshakfy <mariam.elshakfy@arm.com>
-Date: Tue, 3 Oct 2023 13:49:13 +0000
-Subject: [PATCH] Modify SPMC Base to DDR4
-
-Since OP-TEE start address is changed to run
-from DDR4, this patch changes SPMC base to
-the correct one.
-
-Upstream-Status: Pending (not yet submitted to upstream)
-Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
----
- plat/arm/board/n1sdp/include/platform_def.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
-index b3799a7b2..b12c61b61 100644
---- a/plat/arm/board/n1sdp/include/platform_def.h
-+++ b/plat/arm/board/n1sdp/include/platform_def.h
-@@ -118,7 +118,7 @@
-
- #define PLAT_ARM_MAX_BL31_SIZE UL(0x40000)
-
--#define PLAT_ARM_SPMC_BASE U(0x08000000)
-+#define PLAT_ARM_SPMC_BASE U(0xDE000000)
- #define PLAT_ARM_SPMC_SIZE UL(0x02000000) /* 32 MB */
-
-
@@ -1,16 +1,6 @@
# Machine specific TFAs
-FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
-
COMPATIBLE_MACHINE:corstone1000 = "corstone1000"
EXTRA_OEMAKE:append:corstone1000 = " DEBUG=0"
EXTRA_OEMAKE:append:corstone1000 = " LOG_LEVEL=30"
TFTF_MODE:corstone1000 = "release"
-
-COMPATIBLE_MACHINE:n1sdp = "n1sdp"
-EXTRA_OEMAKE:append:n1sdp = " DEBUG=1"
-EXTRA_OEMAKE:append:n1sdp = " LOG_LEVEL=50"
-TFTF_MODE:n1sdp = "debug"
-SRC_URI:append:n1sdp = " \
- file://0001-n1sdp-tftf-tests-to-skip.patch \
- "
deleted file mode 100644
@@ -1,41 +0,0 @@
-# N1SDP specific TFA support
-
-# Align with N1SDP-2023.06.22 Manifest
-SRCREV_tfa = "31f60a968347497562b0129134928d7ac4767710"
-PV .= "+git"
-
-COMPATIBLE_MACHINE = "n1sdp"
-TFA_BUILD_TARGET = "all fip"
-TFA_INSTALL_TARGET = "bl1 bl2 bl31 n1sdp-multi-chip n1sdp-single-chip n1sdp_fw_config n1sdp_tb_fw_config fip"
-TFA_DEBUG = "1"
-TFA_MBEDTLS = "1"
-TFA_UBOOT = "0"
-TFA_UEFI ?= "1"
-
-FILESEXTRAPATHS:prepend := "${THISDIR}/files/n1sdp:"
-
-SRC_URI:append = " \
- file://0001-Reserve-OP-TEE-memory-from-nwd.patch \
- file://0002-Modify-BL32-Location-to-DDR4.patch \
- file://0003-Modify-SPMC-Base-to-DDR4.patch \
- "
-
-TFA_ROT_KEY= "plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem"
-
-# Enabling Secure-EL1 Payload Dispatcher (SPD)
-TFA_SPD = "spmd"
-# Cortex-A35 supports Armv8.0-A (no S-EL2 execution state).
-# So, the SPD SPMC component should run at the S-EL1 execution state
-TFA_SPMD_SPM_AT_SEL2 = "0"
-
-# BL2 loads BL32 (optee). So, optee needs to be built first:
-DEPENDS += "optee-os"
-
-EXTRA_OEMAKE:append = "\
- TRUSTED_BOARD_BOOT=1 \
- GENERATE_COT=1 \
- CREATE_KEYS=1 \
- ARM_ROTPK_LOCATION="devel_rsa" \
- ROT_KEY="${TFA_ROT_KEY}" \
- BL32=${RECIPE_SYSROOT}/${nonarch_base_libdir}/firmware/tee-pager_v2.bin \
- "
@@ -6,7 +6,6 @@ MACHINE_TFA_REQUIRE ?= ""
MACHINE_TFA_REQUIRE:corstone1000 = "trusted-firmware-a-corstone1000.inc"
MACHINE_TFA_REQUIRE:fvp-base = "trusted-firmware-a-fvp-base.inc"
MACHINE_TFA_REQUIRE:juno = "trusted-firmware-a-juno.inc"
-MACHINE_TFA_REQUIRE:n1sdp = "trusted-firmware-a-n1sdp.inc"
MACHINE_TFA_REQUIRE:sbsa-ref = "trusted-firmware-a-sbsa-ref.inc"
MACHINE_TFA_REQUIRE:sgi575 = "trusted-firmware-a-sgi575.inc"
MACHINE_TFA_REQUIRE:tc = "trusted-firmware-a-tc.inc"
deleted file mode 100644
@@ -1,30 +0,0 @@
-# N1SDP specific EDK2 configurations
-EDK2_BUILD_RELEASE = "0"
-EDK2_PLATFORM = "n1sdp"
-EDK2_PLATFORM_DSC = "Platform/ARM/N1Sdp/N1SdpPlatform.dsc"
-EDK2_BIN_NAME = "BL33_AP_UEFI.fd"
-
-COMPATIBLE_MACHINE = "n1sdp"
-
-# UEFI EDK2 on N1SDP is unable to detect FS2 during boot resulting in launching of
-# EDK2 shell instead of launching grub. The startup.nsh will force launching of grub
-EFIDIR = "/EFI/BOOT"
-EFI_BOOT_IMAGE = "bootaa64.efi"
-
-FILESEXTRAPATHS:prepend := "${THISDIR}/files/n1sdp:"
-SRC_URI:append = "\
- file://0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch;patchdir=edk2-platforms \
- file://0002-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch;patchdir=edk2-platforms \
- file://0003-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch;patchdir=edk2-platforms \
- file://0004-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch;patchdir=edk2-platforms \
- file://0005-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch;patchdir=edk2-platforms \
- file://0006-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch;patchdir=edk2-platforms \
- file://0007-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch;patchdir=edk2-platforms \
- file://0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch;patchdir=edk2-platforms \
- file://0009-Platform-ARM-N1Sdp-Reserve-OP-TEE-Region-from-UEFI.patch;patchdir=edk2-platforms \
-"
-
-do_deploy:append() {
- EFIPATH=$(echo "${EFIDIR}" | sed 's/\//\\/g')
- printf 'FS2:%s\%s\n' "$EFIPATH" "${EFI_BOOT_IMAGE}" > ${DEPLOYDIR}/startup.nsh
-}
@@ -6,6 +6,5 @@ MACHINE_EDK2_REQUIRE:fvp-base = "edk2-firmware-fvp-base.inc"
MACHINE_EDK2_REQUIRE:juno = "edk2-firmware-juno.inc"
MACHINE_EDK2_REQUIRE:sbsa-ref = "edk2-firmware-sbsa-ref.inc"
MACHINE_EDK2_REQUIRE:sgi575 = "edk2-firmware-sgi575.inc"
-MACHINE_EDK2_REQUIRE:n1sdp = "edk2-firmware-n1sdp.inc"
require ${MACHINE_EDK2_REQUIRE}
deleted file mode 100644
@@ -1,471 +0,0 @@
-From 928cb457b9ab2abefbacad655eefdde943b4ee9a Mon Sep 17 00:00:00 2001
-From: sahil <sahil@arm.com>
-Date: Thu, 17 Mar 2022 16:28:05 +0530
-Subject: [PATCH] Platform/ARM/N1sdp: Add support to parse NT_FW_CONFIG
-
-NT_FW_CONFIG DTB contains platform information passed by
-Tf-A boot stage.
-This information is used for Virtual memory map generation
-during PEI phase and passed on to DXE phase as a HOB, where
-it is used in ConfigurationManagerDxe.
-
-Upstream-Status: Pending
-Signed-off-by: Adam Johnston <adam.johnston@arm.com>
-Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
-Signed-off-by: sahil <sahil@arm.com>
-Change-Id: I54a86277719607eb00d4a472fae8f13c180eafca
----
- .../ConfigurationManager.c | 24 ++--
- .../ConfigurationManagerDxe.inf | 3 +-
- .../ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 16 +--
- .../Library/PlatformLib/AArch64/Helper.S | 4 +-
- .../Library/PlatformLib/PlatformLib.c | 12 +-
- .../Library/PlatformLib/PlatformLib.inf | 8 +-
- .../Library/PlatformLib/PlatformLibMem.c | 103 +++++++++++++++++-
- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 7 +-
- 8 files changed, 152 insertions(+), 25 deletions(-)
-
-diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
-index a6b4cb0e..c15020f5 100644
---- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
-+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
-@@ -1,7 +1,7 @@
- /** @file
- Configuration Manager Dxe
-
-- Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
-+ Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-@@ -16,6 +16,7 @@
- #include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
- #include <Library/ArmLib.h>
- #include <Library/DebugLib.h>
-+#include <Library/HobLib.h>
- #include <Library/IoLib.h>
- #include <Library/PcdLib.h>
- #include <Library/UefiBootServicesTableLib.h>
-@@ -28,6 +29,7 @@
- #include "Platform.h"
-
- extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat;
-+static NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
-
- /** The platform configuration repository information.
- */
-@@ -1242,13 +1244,11 @@ InitializePlatformRepository (
- IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatRepoInfo
- )
- {
-- NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
- UINT64 Dram2Size;
- UINT64 RemoteDdrSize;
-
- RemoteDdrSize = 0;
-
-- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
- Dram2Size = ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB);
-
- PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size;
-@@ -1512,7 +1512,6 @@ GetGicCInfo (
- )
- {
- EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
-- NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
- UINT32 TotalObjCount;
- UINT32 ObjIndex;
-
-@@ -1523,7 +1522,6 @@ GetGicCInfo (
- }
-
- PlatformRepo = This->PlatRepoInfo;
-- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
-
- if (PlatInfo->MultichipMode == 1) {
- TotalObjCount = PLAT_CPU_COUNT * 2;
-@@ -1623,7 +1621,6 @@ GetStandardNameSpaceObject (
- {
- EFI_STATUS Status;
- EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
-- NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
- UINT32 AcpiTableCount;
-
- if ((This == NULL) || (CmObject == NULL)) {
-@@ -1634,7 +1631,7 @@ GetStandardNameSpaceObject (
-
- Status = EFI_NOT_FOUND;
- PlatformRepo = This->PlatRepoInfo;
-- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
-+
- AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList);
- if (PlatInfo->MultichipMode == 0)
- AcpiTableCount -= 1;
-@@ -1697,7 +1694,6 @@ GetArmNameSpaceObject (
- {
- EFI_STATUS Status;
- EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
-- NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
- UINT32 GicRedistCount;
- UINT32 GicCpuCount;
- UINT32 ProcHierarchyInfoCount;
-@@ -1718,8 +1714,6 @@ GetArmNameSpaceObject (
- Status = EFI_NOT_FOUND;
- PlatformRepo = This->PlatRepoInfo;
-
-- // Probe for multi chip information
-- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
- if (PlatInfo->MultichipMode == 1) {
- GicRedistCount = 2;
- GicCpuCount = PLAT_CPU_COUNT * 2;
-@@ -2162,8 +2156,18 @@ ConfigurationManagerDxeInitialize (
- IN EFI_SYSTEM_TABLE * SystemTable
- )
- {
-+ VOID *PlatInfoHob;
- EFI_STATUS Status;
-
-+ PlatInfoHob = GetFirstGuidHob (&gArmNeoverseN1SocPlatformInfoDescriptorGuid);
-+
-+ if (PlatInfoHob == NULL) {
-+ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n"));
-+ return EFI_NOT_FOUND;
-+ }
-+
-+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)GET_GUID_HOB_DATA (PlatInfoHob);
-+
- // Initialize the Platform Configuration Repository before installing the
- // Configuration Manager Protocol
- Status = InitializePlatformRepository (
-diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
-index 4f8e7f13..a4e8b783 100644
---- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
-+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
-@@ -1,7 +1,7 @@
- ## @file
- # Configuration Manager Dxe
- #
--# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
-+# Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.<BR>
- #
- # SPDX-License-Identifier: BSD-2-Clause-Patent
- #
-@@ -42,6 +42,7 @@
-
- [LibraryClasses]
- ArmPlatformLib
-+ HobLib
- PrintLib
- UefiBootServicesTableLib
- UefiDriverEntryPoint
-diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
-index 097160c7..4966011e 100644
---- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
-+++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
-@@ -1,6 +1,6 @@
- /** @file
- *
--* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
-+* Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-2-Clause-Patent
- *
-@@ -41,11 +41,6 @@
- #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000
- #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000
-
--// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is
--// pre-populated by a earlier boot stage
--#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \
-- 0x00008000)
--
- /*
- * Platform information structure stored in Non-secure SRAM. Platform
- * information are passed from the trusted firmware with the below structure
-@@ -55,12 +50,17 @@
- typedef struct {
- /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */
- UINT8 MultichipMode;
-- /*! Slave count in C2C mode */
-- UINT8 SlaveCount;
-+ /*! Secondary chip count in C2C mode */
-+ UINT8 SecondaryChipCount;
- /*! Local DDR memory size in GigaBytes */
- UINT8 LocalDdrSize;
- /*! Remote DDR memory size in GigaBytes */
- UINT8 RemoteDdrSize;
- } NEOVERSEN1SOC_PLAT_INFO;
-
-+// NT_FW_CONFIG DT structure
-+typedef struct {
-+ UINT64 NtFwConfigDtAddr;
-+} NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI;
-+
- #endif
-diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
-index 8d2069de..a0b89a7b 100644
---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
-+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
-@@ -1,6 +1,6 @@
- /** @file
- *
--* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
-+* Copyright (c) 2019 - 2023, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-2-Clause-Patent
- *
-@@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
- // the UEFI firmware through the CPU registers.
- //
- ASM_PFX(ArmPlatformPeiBootAction):
-+ adr x10, NtFwConfigDtBlob
-+ str x0, [x10]
- ret
-
- //
-diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
-index c0effd37..2f753be7 100644
---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
-+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
-@@ -1,6 +1,6 @@
- /** @file
-
-- Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
-+ Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-@@ -8,8 +8,12 @@
-
- #include <Library/ArmPlatformLib.h>
- #include <Library/BaseLib.h>
-+#include <NeoverseN1Soc.h>
- #include <Ppi/ArmMpCoreInfo.h>
-
-+UINT64 NtFwConfigDtBlob;
-+STATIC NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI mNtFwConfigDtInfoPpi;
-+
- STATIC ARM_CORE_INFO mCoreInfoTable[] = {
- { 0x0, 0x0 }, // Cluster 0, Core 0
- { 0x0, 0x1 }, // Cluster 0, Core 1
-@@ -46,6 +50,7 @@ ArmPlatformInitialize (
- IN UINTN MpId
- )
- {
-+ mNtFwConfigDtInfoPpi.NtFwConfigDtAddr = NtFwConfigDtBlob;
- return RETURN_SUCCESS;
- }
-
-@@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gArmMpCoreInfoPpiGuid,
- &mMpCoreInfoPpi
-+ },
-+ {
-+ EFI_PEI_PPI_DESCRIPTOR_PPI,
-+ &gNtFwConfigDtInfoPpiGuid,
-+ &mNtFwConfigDtInfoPpi
- }
- };
-
-diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
-index 96e590cd..78f309c3 100644
---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
-+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
-@@ -1,7 +1,7 @@
- ## @file
- # Platform Library for N1Sdp.
- #
--# Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
-+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
- #
- # SPDX-License-Identifier: BSD-2-Clause-Patent
- #
-@@ -18,10 +18,14 @@
- [Packages]
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-+ EmbeddedPkg/EmbeddedPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
-
-+[LibraryClasses]
-+ FdtLib
-+
- [Sources.common]
- PlatformLibMem.c
- PlatformLib.c
-@@ -59,7 +63,9 @@
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
-
- [Guids]
-+ gArmNeoverseN1SocPlatformInfoDescriptorGuid
- gEfiHobListGuid ## CONSUMES ## SystemTable
-
- [Ppis]
- gArmMpCoreInfoPpiGuid
-+ gNtFwConfigDtInfoPpiGuid
-diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
-index 339fa07b..1d53ec75 100644
---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
-+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
-@@ -1,6 +1,6 @@
- /** @file
-
-- Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
-+ Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-@@ -10,11 +10,95 @@
- #include <Library/DebugLib.h>
- #include <Library/HobLib.h>
- #include <Library/MemoryAllocationLib.h>
-+#include <Library/PeiServicesLib.h>
-+#include <libfdt.h>
- #include <NeoverseN1Soc.h>
-
- // The total number of descriptors, including the final "end-of-table" descriptor.
- #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
-
-+/** A helper function to locate the NtFwConfig PPI and get the base address of
-+ NT_FW_CONFIG DT from which values are obtained using FDT helper functions.
-+
-+ @param [out] plat_info Pointer to the NeoverseN1Soc PLATFORM_INFO HOB
-+
-+ @retval EFI_SUCCESS Success.
-+ returns EFI_INVALID_PARAMETER A parameter is invalid.
-+**/
-+EFI_STATUS
-+GetNeoverseN1SocPlatInfo (
-+ OUT NEOVERSEN1SOC_PLAT_INFO *plat_info
-+ )
-+{
-+ CONST UINT32 *Property;
-+ INT32 Offset;
-+ CONST VOID *NtFwCfgDtBlob;
-+ NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI *NtFwConfigInfoPpi;
-+ EFI_STATUS Status;
-+
-+ Status = PeiServicesLocatePpi (
-+ &gNtFwConfigDtInfoPpiGuid,
-+ 0,
-+ NULL,
-+ (VOID **)&NtFwConfigInfoPpi
-+ );
-+
-+ if (EFI_ERROR (Status)) {
-+ DEBUG ((
-+ DEBUG_ERROR,
-+ "PeiServicesLocatePpi failed with error %r\n",
-+ Status
-+ ));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ NtFwCfgDtBlob = (VOID *)(UINTN)NtFwConfigInfoPpi->NtFwConfigDtAddr;
-+ if (fdt_check_header (NtFwCfgDtBlob) != 0) {
-+ DEBUG ((DEBUG_ERROR, "Invalid DTB file %p passed\n", NtFwCfgDtBlob));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ Offset = fdt_subnode_offset (NtFwCfgDtBlob, 0, "platform-info");
-+ if (Offset == -FDT_ERR_NOTFOUND) {
-+ DEBUG ((DEBUG_ERROR, "Invalid DTB : platform-info node not found\n"));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "local-ddr-size", NULL);
-+ if (Property == NULL) {
-+ DEBUG ((DEBUG_ERROR, "local-ddr-size property not found\n"));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ plat_info->LocalDdrSize = fdt32_to_cpu (*Property);
-+
-+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "remote-ddr-size", NULL);
-+ if (Property == NULL) {
-+ DEBUG ((DEBUG_ERROR, "remote-ddr-size property not found\n"));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ plat_info->RemoteDdrSize = fdt32_to_cpu (*Property);
-+
-+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "secondary-chip-count", NULL);
-+ if (Property == NULL) {
-+ DEBUG ((DEBUG_ERROR, "secondary-chip-count property not found\n"));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ plat_info->SecondaryChipCount = fdt32_to_cpu (*Property);
-+
-+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "multichip-mode", NULL);
-+ if (Property == NULL) {
-+ DEBUG ((DEBUG_ERROR, "multichip-mode property not found\n"));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ plat_info->MultichipMode = fdt32_to_cpu (*Property);
-+
-+ return EFI_SUCCESS;
-+}
-+
- /**
- Returns the Virtual Memory Map of the platform.
-
-@@ -36,9 +120,24 @@ ArmPlatformGetVirtualMemoryMap (
- NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
- UINT64 DramBlock2Size;
- UINT64 RemoteDdrSize;
-+ EFI_STATUS Status;
-
- Index = 0;
-- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
-+
-+ // Create platform info HOB
-+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)BuildGuidHob (
-+ &gArmNeoverseN1SocPlatformInfoDescriptorGuid,
-+ sizeof (NEOVERSEN1SOC_PLAT_INFO)
-+ );
-+
-+ if (PlatInfo == NULL) {
-+ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n"));
-+ ASSERT (FALSE);
-+ return;
-+ }
-+
-+ Status = GetNeoverseN1SocPlatInfo (PlatInfo);
-+ ASSERT (Status == 0);
- DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize -
- NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) *
- (UINT64)SIZE_1GB);
-diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
-index d59f25a5..9e257ebd 100644
---- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
-+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
-@@ -1,7 +1,7 @@
- ## @file
- # Describes the entire platform configuration.
- #
--# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
-+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
- #
- # SPDX-License-Identifier: BSD-2-Clause-Patent
- #
-@@ -22,6 +22,8 @@
- Include # Root include for the package
-
- [Guids.common]
-+ # ARM NeoverseN1Soc Platform Info descriptor
-+ gArmNeoverseN1SocPlatformInfoDescriptorGuid = { 0x095cb024, 0x1e00, 0x4d6f, { 0xaa, 0x34, 0x4a, 0xf8, 0xaf, 0x0e, 0xad, 0x99 } }
- gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } }
-
- [PcdsFixedAtBuild]
-@@ -83,3 +85,6 @@
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
-+
-+[Ppis]
-+ gNtFwConfigDtInfoPpiGuid = { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } }
deleted file mode 100644
@@ -1,63 +0,0 @@
-From 2ccb463274d0c04f1e3253194ea6eee80c31cb49 Mon Sep 17 00:00:00 2001
-From: Himanshu Sharma <Himanshu.Sharma@arm.com>
-Date: Mon, 30 May 2022 10:53:30 +0000
-Subject: [PATCH] Platform/ARM/N1Sdp: Modify the IRQ ID of Debug UART and
- routing it to IOFPGA UART1
-
-In DBG2 table, IRQ ID was set as 0 for the UART. This overwrote the
-IPI0 trigger method to "level", which prevented SGI0 to be enabled
-again after a CPU offline/online cycle.
-
-This patch fixes the above issue by assigning a reserved IRQ ID
-for the Debug UART, other than 0 and also routing it to use IOFPGA
-UART1 by unsharing it from currently using serial terminal.
-
-Upstream-Status: Pending
-Signed-off-by: Adam Johnston <adam.johnston@arm.com>
-Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
-Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
-Change-Id: Ib35fecc57f1d8c496135c18dbebd0be0a4b76041
----
- .../ConfigurationManagerDxe/ConfigurationManager.c | 2 +-
- Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 8 ++++----
- 2 files changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
-index b11c0425..44046a00 100644
---- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
-+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
-@@ -320,7 +320,7 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = {
- // Debug Serial Port
- {
- FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress
-- 0, // Interrupt -unused
-+ 250, // Interrupt (reserved)
- FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate
- FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock
- EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART // Port subtype
-diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
-index d04b22d3..676ab677 100644
---- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
-+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
-@@ -4,7 +4,7 @@
- # This provides platform specific component descriptions and libraries that
- # conform to EFI/Framework standards.
- #
--# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
-+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
- #
- # SPDX-License-Identifier: BSD-2-Clause-Patent
- #
-@@ -136,9 +136,9 @@
- gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95
-
- # PL011 Serial Debug UART (DBG2)
-- gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
-- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
-- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000
-+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x1C0A0000
-+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200
-+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|24000000
-
- # SBSA Watchdog
- gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93
deleted file mode 100644
@@ -1,57 +0,0 @@
-From e4b0fced6f3fd3c8ce5ab4d3aae97b880e7e07b0 Mon Sep 17 00:00:00 2001
-From: sahil <sahil@arm.com>
-Date: Mon, 2 May 2022 17:43:17 +0530
-Subject: [PATCH] Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region
-
-Enable SCP QSPI flash region access by adding it in the PlatformLibMem
-
-Upstream-Status: Pending
-Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
-Signed-off-by: sahil <sahil@arm.com>
-Change-Id: I3ff832746ca94974ed72309eebe00e0024c47005
----
- Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 4 ++++
- .../NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 8 +++++++-
- 2 files changed, 11 insertions(+), 1 deletion(-)
-
-diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
-index 4966011e..c7219136 100644
---- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
-+++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
-@@ -41,6 +41,10 @@
- #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000
- #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000
-
-+// SCP QSPI flash device
-+#define NEOVERSEN1SOC_SCP_QSPI_AHB_BASE 0x18000000
-+#define NEOVERSEN1SOC_SCP_QSPI_AHB_SZ 0x2000000
-+
- /*
- * Platform information structure stored in Non-secure SRAM. Platform
- * information are passed from the trusted firmware with the below structure
-diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
-index 5cacd437..8bb94074 100644
---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
-+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
-@@ -15,7 +15,7 @@
- #include <NeoverseN1Soc.h>
-
- // The total number of descriptors, including the final "end-of-table" descriptor.
--#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
-+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 20
-
- /** A helper function to locate the NtFwConfig PPI and get the base address of
- NT_FW_CONFIG DT from which values are obtained using FDT helper functions.
-@@ -283,6 +283,12 @@ ArmPlatformGetVirtualMemoryMap (
- VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
-
-+ // SCP QSPI flash device
-+ VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
-+ VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
-+ VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_SCP_QSPI_AHB_SZ;
-+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
-+
- if (PlatInfo->MultichipMode == 1) {
- //Remote DDR (2GB)
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) +
deleted file mode 100644
@@ -1,119 +0,0 @@
-From 70e79ba5300f01a13422452c29e26c69042a0c8c Mon Sep 17 00:00:00 2001
-From: sahil <sahil@arm.com>
-Date: Mon, 2 May 2022 18:50:08 +0530
-Subject: [PATCH] Platform/ARM/N1Sdp: NOR flash library for N1Sdp
-
-Add NOR flash library, this library provides APIs for getting the list
-of NOR flash devices on the platform.
-
-Upstream-Status: Pending
-Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
-Signed-off-by: sahil <sahil@arm.com>
-Change-Id: I39ad4143b7fad7e33b3b151a019a74f23e0ed441
----
- .../Library/NorFlashLib/NorFlashLib.c | 52 +++++++++++++++++++
- .../Library/NorFlashLib/NorFlashLib.inf | 36 +++++++++++++
- 2 files changed, 88 insertions(+)
- create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c
- create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf
-
-diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c
-new file mode 100644
-index 00000000..eee3d1c6
---- /dev/null
-+++ b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c
-@@ -0,0 +1,52 @@
-+/** @file
-+ NOR flash lib for N1Sdp
-+
-+ Copyright (c) 2023, ARM Limited. All rights reserved.<BR>
-+
-+ SPDX-License-Identifier: BSD-2-Clause-Patent
-+
-+**/
-+
-+#include <Library/DebugLib.h>
-+#include <Library/IoLib.h>
-+#include <Library/NorFlashPlatformLib.h>
-+#include <NeoverseN1Soc.h>
-+#include <PiDxe.h>
-+
-+#define FW_ENV_REGION_BASE FixedPcdGet32 (PcdFlashNvStorageVariableBase)
-+#define FW_ENV_REGION_SIZE (FixedPcdGet32 (PcdFlashNvStorageVariableSize) + \
-+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + \
-+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize))
-+
-+STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {
-+ {
-+ /// Environment variable region
-+ NEOVERSEN1SOC_SCP_QSPI_AHB_BASE, ///< device base
-+ FW_ENV_REGION_BASE, ///< region base
-+ FW_ENV_REGION_SIZE, ///< region size
-+ SIZE_4KB, ///< block size
-+ },
-+};
-+
-+/**
-+ Get NOR flash region info
-+
-+ @param[out] NorFlashDevices NOR flash regions info.
-+ @param[out] Count number of flash instance.
-+
-+ @retval EFI_SUCCESS Success.
-+**/
-+EFI_STATUS
-+NorFlashPlatformGetDevices (
-+ OUT NOR_FLASH_DESCRIPTION **NorFlashDevices,
-+ OUT UINT32 *Count
-+ )
-+{
-+ if ((NorFlashDevices == NULL) || (Count == NULL)) {
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ *NorFlashDevices = mNorFlashDevices;
-+ *Count = ARRAY_SIZE (mNorFlashDevices);
-+ return EFI_SUCCESS;
-+}
-diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf
-new file mode 100644
-index 00000000..784856c8
---- /dev/null
-+++ b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf
-@@ -0,0 +1,36 @@
-+## @file
-+# NOR flash lib for N1Sdp
-+#
-+# Copyright (c) 2023, ARM Limited. All rights reserved.<BR>
-+#
-+# SPDX-License-Identifier: BSD-2-Clause-Patent
-+#
-+##
-+
-+[Defines]
-+ INF_VERSION = 0x0001001B
-+ BASE_NAME = NorFlashN1SdpLib
-+ FILE_GUID = 7006fcf1-a585-4272-92e3-b286b1dff5bb
-+ MODULE_TYPE = DXE_DRIVER
-+ VERSION_STRING = 1.0
-+ LIBRARY_CLASS = NorFlashPlatformLib
-+
-+[Sources.common]
-+ NorFlashLib.c
-+
-+[Packages]
-+ MdeModulePkg/MdeModulePkg.dec
-+ MdePkg/MdePkg.dec
-+ Platform/ARM/ARM.dec
-+ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
-+
-+[LibraryClasses]
-+ BaseLib
-+ DebugLib
-+ IoLib
-+
-+[FixedPcd]
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
deleted file mode 100644
@@ -1,2538 +0,0 @@
-From 726f4505970c82db1822b127059519044dc496c8 Mon Sep 17 00:00:00 2001
-From: sahil <sahil@arm.com>
-Date: Mon, 2 May 2022 19:00:40 +0530
-Subject: [PATCH] Platform/ARM/N1Sdp: NOR flash Dxe Driver for N1Sdp
-
-Add NOR flash DXE driver, this brings up NV storage on
-QSPI's flash device using FVB protocol.
-
-Upstream-Status: Pending
-Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
-Signed-off-by: sahil <sahil@arm.com>
-Change-Id: Ica383c2be6d1805daa19afd98d28b943816218dd
----
- .../Drivers/CadenceQspiDxe/CadenceQspiDxe.c | 366 +++++++
- .../Drivers/CadenceQspiDxe/CadenceQspiDxe.inf | 70 ++
- .../Drivers/CadenceQspiDxe/CadenceQspiReg.h | 31 +
- .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c | 930 ++++++++++++++++++
- .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h | 484 +++++++++
- .../Drivers/CadenceQspiDxe/NorFlashFvb.c | 573 +++++++++++
- Platform/ARM/N1Sdp/N1SdpPlatform.dec | 5 +-
- 7 files changed, 2458 insertions(+), 1 deletion(-)
- create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c
- create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
- create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
- create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
- create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
- create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c
-
-diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c
-new file mode 100644
-index 00000000..fb1dff3e
---- /dev/null
-+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c
-@@ -0,0 +1,366 @@
-+/** @file
-+ NOR flash DXE
-+
-+ Copyright (c) 2023, ARM Limited. All rights reserved.<BR>
-+
-+ SPDX-License-Identifier: BSD-2-Clause-Patent
-+
-+**/
-+
-+#include <Library/BaseMemoryLib.h>
-+#include <Library/DxeServicesTableLib.h>
-+#include <Library/HobLib.h>
-+#include <Library/MemoryAllocationLib.h>
-+#include <Library/NorFlashInfoLib.h>
-+#include <Library/PcdLib.h>
-+#include <Library/UefiBootServicesTableLib.h>
-+#include <Library/UefiLib.h>
-+#include <Library/UefiRuntimeLib.h>
-+#include <Library/UefiRuntimeServicesTableLib.h>
-+
-+#include "NorFlash.h"
-+
-+STATIC NOR_FLASH_INSTANCE **mNorFlashInstances;
-+STATIC UINT32 mNorFlashDeviceCount;
-+
-+STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent;
-+
-+/**
-+ Install Fv block onto variable store region
-+
-+ @param[in] Instance Instance of Nor flash variable region.
-+
-+ @retval EFI_SUCCESS The entry point is executed successfully.
-+**/
-+EFI_STATUS
-+EFIAPI
-+NorFlashFvbInitialize (
-+ IN NOR_FLASH_INSTANCE* Instance
-+ )
-+{
-+ EFI_STATUS Status;
-+ UINT32 FvbNumLba;
-+ EFI_BOOT_MODE BootMode;
-+ UINTN RuntimeMmioRegionSize;
-+ UINTN RuntimeMmioDeviceSize;
-+ UINTN BlockSize;
-+
-+ DEBUG ((DEBUG_INFO,"NorFlashFvbInitialize\n"));
-+
-+ BlockSize = Instance->BlockSize;
-+
-+ // FirmwareVolumeHeader->FvLength is declared to have the Variable area
-+ // AND the FTW working area AND the FTW Spare contiguous.
-+ ASSERT (PcdGet32 (PcdFlashNvStorageVariableBase) +
-+ PcdGet32 (PcdFlashNvStorageVariableSize) ==
-+ PcdGet32 (PcdFlashNvStorageFtwWorkingBase));
-+ ASSERT (PcdGet32 (PcdFlashNvStorageFtwWorkingBase) +
-+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) ==
-+ PcdGet32 (PcdFlashNvStorageFtwSpareBase));
-+
-+ // Check if the size of the area is at least one block size.
-+ ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) &&
-+ (PcdGet32 (PcdFlashNvStorageVariableSize) / BlockSize > 0));
-+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) &&
-+ (PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / BlockSize > 0));
-+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) &&
-+ (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / BlockSize > 0));
-+
-+ // Ensure the Variable areas are aligned on block size boundaries.
-+ ASSERT ((PcdGet32 (PcdFlashNvStorageVariableBase) % BlockSize) == 0);
-+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingBase) % BlockSize) == 0);
-+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareBase) % BlockSize) == 0);
-+
-+ Instance->Initialized = TRUE;
-+ mFlashNvStorageVariableBase = FixedPcdGet32 (PcdFlashNvStorageVariableBase);
-+
-+ // Set the index of the first LBA for the FVB.
-+ Instance->StartLba = (PcdGet32 (PcdFlashNvStorageVariableBase) -
-+ Instance->RegionBaseAddress) / BlockSize;
-+
-+ BootMode = GetBootModeHob ();
-+ if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) {
-+ Status = EFI_INVALID_PARAMETER;
-+ } else {
-+ // Determine if there is a valid header at the beginning of the NorFlash.
-+ Status = ValidateFvHeader (Instance);
-+ }
-+
-+ // Install the Default FVB header if required.
-+ if (EFI_ERROR(Status)) {
-+ // There is no valid header, so time to install one.
-+ DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__));
-+ DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n",
-+ __FUNCTION__));
-+
-+ // Erase all the NorFlash that is reserved for variable storage.
-+ FvbNumLba = (PcdGet32 (PcdFlashNvStorageVariableSize) +
-+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
-+ PcdGet32 (PcdFlashNvStorageFtwSpareSize)) /
-+ Instance->BlockSize;
-+
-+ Status = FvbEraseBlocks (
-+ &Instance->FvbProtocol,
-+ (EFI_LBA)0,
-+ FvbNumLba,
-+ EFI_LBA_LIST_TERMINATOR
-+ );
-+ if (EFI_ERROR(Status)) {
-+ return Status;
-+ }
-+
-+ // Install all appropriate headers.
-+ Status = InitializeFvAndVariableStoreHeaders (Instance);
-+ if (EFI_ERROR(Status)) {
-+ return Status;
-+ }
-+
-+ // validate FV header again if FV was created successfully.
-+ Status = ValidateFvHeader (Instance);
-+ if (EFI_ERROR(Status)) {
-+ DEBUG ((DEBUG_ERROR, "ValidateFvHeader is failed \n"));
-+ return Status;
-+ }
-+ }
-+
-+ // The driver implementing the variable read service can now be dispatched;
-+ // the varstore headers are in place.
-+ Status = gBS->InstallProtocolInterface (
-+ &gImageHandle,
-+ &gEdkiiNvVarStoreFormattedGuid,
-+ EFI_NATIVE_INTERFACE,
-+ NULL
-+ );
-+ if (EFI_ERROR (Status)) {
-+ DEBUG ((DEBUG_ERROR,
-+ "%a: Failed to install gEdkiiNvVarStoreFormattedGuid\n",
-+ __FUNCTION__));
-+ return Status;
-+ }
-+
-+ // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME.
-+ RuntimeMmioRegionSize = Instance->Size;
-+ RuntimeMmioDeviceSize = Instance->RegionBaseAddress - Instance->DeviceBaseAddress;
-+
-+ Status = gDS->AddMemorySpace (
-+ EfiGcdMemoryTypeMemoryMappedIo,
-+ Instance->RegionBaseAddress,
-+ RuntimeMmioRegionSize,
-+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
-+ );
-+ ASSERT_EFI_ERROR (Status);
-+
-+ Status = gDS->AddMemorySpace (
-+ EfiGcdMemoryTypeMemoryMappedIo,
-+ Instance->DeviceBaseAddress,
-+ RuntimeMmioDeviceSize,
-+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
-+ );
-+ ASSERT_EFI_ERROR (Status);
-+
-+ Status = gDS->SetMemorySpaceAttributes (
-+ Instance->RegionBaseAddress,
-+ RuntimeMmioRegionSize,
-+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
-+ );
-+ ASSERT_EFI_ERROR (Status);
-+
-+ Status = gDS->SetMemorySpaceAttributes (
-+ Instance->DeviceBaseAddress,
-+ RuntimeMmioDeviceSize,
-+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
-+ );
-+ ASSERT_EFI_ERROR (Status);
-+
-+ return Status;
-+}
-+
-+/**
-+ Fixup internal data so that EFI can be called in virtual mode.
-+ convert any pointers in lib to virtual mode.
-+
-+ @param[in] Event The Event that is being processed
-+ @param[in] Context Event Context
-+**/
-+STATIC
-+VOID
-+EFIAPI
-+NorFlashVirtualNotifyEvent (
-+ IN EFI_EVENT Event,
-+ IN VOID *Context
-+ )
-+{
-+ UINTN Index;
-+
-+ EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase);
-+
-+ for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
-+ EfiConvertPointer (0x0,
-+ (VOID**)&mNorFlashInstances[Index]->HostRegisterBaseAddress);
-+ EfiConvertPointer (0x0,
-+ (VOID**)&mNorFlashInstances[Index]->DeviceBaseAddress);
-+ EfiConvertPointer (0x0,
-+ (VOID**)&mNorFlashInstances[Index]->RegionBaseAddress);
-+
-+ // Convert Fvb.
-+ EfiConvertPointer (0x0,
-+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.EraseBlocks);
-+ EfiConvertPointer (0x0,
-+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetAttributes);
-+ EfiConvertPointer (0x0,
-+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetBlockSize);
-+ EfiConvertPointer (0x0,
-+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetPhysicalAddress);
-+ EfiConvertPointer (0x0,
-+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Read);
-+ EfiConvertPointer (0x0,
-+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.SetAttributes);
-+ EfiConvertPointer (0x0,
-+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Write);
-+
-+ if (mNorFlashInstances[Index]->ShadowBuffer != NULL) {
-+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->ShadowBuffer);
-+ }
-+ }
-+}
-+
-+/**
-+ Entrypoint of Platform Nor flash DXE driver
-+
-+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
-+ @param[in] SystemTable A pointer to the EFI System Table.
-+
-+ @retval EFI_SUCCESS The entry point is executed successfully.
-+**/
-+EFI_STATUS
-+EFIAPI
-+NorFlashInitialise (
-+ IN EFI_HANDLE ImageHandle,
-+ IN EFI_SYSTEM_TABLE *SystemTable
-+ )
-+{
-+ EFI_STATUS Status;
-+ EFI_PHYSICAL_ADDRESS HostRegisterBaseAddress;
-+ UINT32 Index;
-+ NOR_FLASH_DESCRIPTION* NorFlashDevices;
-+ BOOLEAN ContainVariableStorage;
-+
-+ HostRegisterBaseAddress = PcdGet32 (PcdCadenceQspiDxeRegBaseAddress);
-+
-+ Status = gDS->AddMemorySpace (
-+ EfiGcdMemoryTypeMemoryMappedIo,
-+ HostRegisterBaseAddress,
-+ SIZE_64KB,
-+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
-+ );
-+ ASSERT_EFI_ERROR (Status);
-+
-+ Status = gDS->SetMemorySpaceAttributes (
-+ HostRegisterBaseAddress,
-+ SIZE_64KB,
-+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
-+ );
-+ ASSERT_EFI_ERROR (Status);
-+
-+ // Initialize NOR flash instances.
-+ Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount);
-+ if (EFI_ERROR (Status)) {
-+ DEBUG ((DEBUG_ERROR,"NorFlashInitialise: Fail to get Nor Flash devices\n"));
-+ return Status;
-+ }
-+
-+ mNorFlashInstances = AllocateRuntimePool (sizeof (NOR_FLASH_INSTANCE*) *
-+ mNorFlashDeviceCount);
-+
-+ if(mNorFlashInstances == NULL) {
-+ DEBUG ((DEBUG_ERROR,
-+ "NorFlashInitialise: Failed to allocate mem for NorFlashInstance\n"));
-+ return EFI_OUT_OF_RESOURCES;
-+ }
-+
-+ for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
-+ // Check if this NOR Flash device contain the variable storage region.
-+ ContainVariableStorage =
-+ (NorFlashDevices[Index].RegionBaseAddress <=
-+ PcdGet32 (PcdFlashNvStorageVariableBase)) &&
-+ (PcdGet32 (PcdFlashNvStorageVariableBase) +
-+ PcdGet32 (PcdFlashNvStorageVariableSize) <=
-+ NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size);
-+
-+ Status = NorFlashCreateInstance (
-+ HostRegisterBaseAddress,
-+ NorFlashDevices[Index].DeviceBaseAddress,
-+ NorFlashDevices[Index].RegionBaseAddress,
-+ NorFlashDevices[Index].Size,
-+ Index,
-+ NorFlashDevices[Index].BlockSize,
-+ ContainVariableStorage,
-+ &mNorFlashInstances[Index]
-+ );
-+ if (EFI_ERROR (Status)) {
-+ DEBUG ((DEBUG_ERROR,
-+ "NorFlashInitialise: Fail to create instance for NorFlash[%d]\n",
-+ Index));
-+ continue;
-+ }
-+ Status = gBS->InstallMultipleProtocolInterfaces (
-+ &mNorFlashInstances[Index]->Handle,
-+ &gEfiDevicePathProtocolGuid,
-+ &mNorFlashInstances[Index]->DevicePath,
-+ &gEfiFirmwareVolumeBlockProtocolGuid,
-+ &mNorFlashInstances[Index]->FvbProtocol,
-+ NULL
-+ );
-+ ASSERT_EFI_ERROR (Status);
-+ }
-+ // Register for the virtual address change event.
-+ Status = gBS->CreateEventEx (
-+ EVT_NOTIFY_SIGNAL,
-+ TPL_NOTIFY,
-+ NorFlashVirtualNotifyEvent,
-+ NULL,
-+ &gEfiEventVirtualAddressChangeGuid,
-+ &mNorFlashVirtualAddrChangeEvent
-+ );
-+ ASSERT_EFI_ERROR (Status);
-+
-+ return Status;
-+}
-+
-+/**
-+ Lock all pending read/write to Nor flash device
-+
-+ @param[in] Context Nor flash device context structure.
-+**/
-+VOID
-+EFIAPI
-+NorFlashLock (
-+ IN NOR_FLASH_LOCK_CONTEXT *Context
-+ )
-+{
-+ if (!EfiAtRuntime ()) {
-+ // Raise TPL to TPL_HIGH to stop anyone from interrupting us.
-+ Context->OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
-+ } else {
-+ Context->InterruptsEnabled = SaveAndDisableInterrupts ();
-+ }
-+}
-+
-+/**
-+ Unlock all pending read/write to Nor flash device
-+
-+ @param[in] Context Nor flash device context structure.
-+**/
-+VOID
-+EFIAPI
-+NorFlashUnlock (
-+ IN NOR_FLASH_LOCK_CONTEXT *Context
-+ )
-+{
-+ if (!EfiAtRuntime ()) {
-+ // Interruptions can resume.
-+ gBS->RestoreTPL (Context->OriginalTPL);
-+ } else if (Context->InterruptsEnabled) {
-+ SetInterruptState (TRUE);
-+ }
-+}
-diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
-new file mode 100644
-index 00000000..4f20c3ba
---- /dev/null
-+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
-@@ -0,0 +1,70 @@
-+## @file
-+# NOR flash DXE
-+#
-+# Copyright (c) 2023, ARM Limited. All rights reserved.<BR>
-+#
-+# SPDX-License-Identifier: BSD-2-Clause-Patent
-+#
-+##
-+
-+[Defines]
-+ INF_VERSION = 0x0001001B
-+ BASE_NAME = CadenceQspiDxe
-+ FILE_GUID = CC8A9713-4442-4A6C-B389-8B46490A0641
-+ MODULE_TYPE = DXE_RUNTIME_DRIVER
-+ VERSION_STRING = 0.1
-+ ENTRY_POINT = NorFlashInitialise
-+
-+[Sources]
-+ CadenceQspiDxe.c
-+ NorFlash.c
-+ NorFlash.h
-+ NorFlashFvb.c
-+
-+[Packages]
-+ EmbeddedPkg/EmbeddedPkg.dec
-+ MdeModulePkg/MdeModulePkg.dec
-+ MdePkg/MdePkg.dec
-+ Platform/ARM/ARM.dec
-+ Platform/ARM/N1Sdp/N1SdpPlatform.dec
-+
-+[LibraryClasses]
-+ BaseLib
-+ BaseMemoryLib
-+ DebugLib
-+ DevicePathLib
-+ DxeServicesTableLib
-+ HobLib
-+ IoLib
-+ MemoryAllocationLib
-+ NorFlashInfoLib
-+ NorFlashPlatformLib
-+ UefiBootServicesTableLib
-+ UefiDriverEntryPoint
-+ UefiLib
-+ UefiRuntimeLib
-+ UefiRuntimeServicesTableLib
-+
-+[Guids]
-+ gEdkiiNvVarStoreFormattedGuid
-+ gEfiAuthenticatedVariableGuid
-+ gEfiEventVirtualAddressChangeGuid
-+ gEfiSystemNvDataFvGuid
-+ gEfiVariableGuid
-+ gEfiGlobalVariableGuid
-+
-+[Protocols]
-+ gEfiDevicePathProtocolGuid
-+ gEfiFirmwareVolumeBlockProtocolGuid
-+
-+[FixedPcd]
-+ gArmN1SdpTokenSpaceGuid.PcdCadenceQspiDxeRegBaseAddress
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
-+
-+[Depex]
-+ gEfiCpuArchProtocolGuid
-diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
-new file mode 100644
-index 00000000..fe3b327c
---- /dev/null
-+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
-@@ -0,0 +1,31 @@
-+/** @file
-+
-+ Copyright (c) 2023, ARM Limited. All rights reserved.<BR>
-+
-+ SPDX-License-Identifier: BSD-2-Clause-Patent
-+
-+**/
-+
-+#ifndef CADENCE_QSPI_REG_H_
-+#define CADENCE_QSPI_REG_H_
-+
-+// QSPI Controller defines
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET 0x90
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_EXECUTE 0x01
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE 0x01
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS 19
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS 16
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT 0x02
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_4B 0x03
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B 0x02
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS 24
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE 0x01
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_BYTE_3B 0x02
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS 23
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS 20
-+
-+#define CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET 0xA0
-+
-+#define CDNS_QSPI_FLASH_CMD_ADDR_REG_OFFSET 0x94
-+
-+#endif /* CADENCE_QSPI_REG_H_ */
-diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
-new file mode 100644
-index 00000000..188c75e2
---- /dev/null
-+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
-@@ -0,0 +1,930 @@
-+/** @file
-+
-+ Copyright (c) 2023 ARM Limited. All rights reserved.<BR>
-+
-+ SPDX-License-Identifier: BSD-2-Clause-Patent
-+
-+**/
-+
-+#include <Library/BaseMemoryLib.h>
-+#include <Library/MemoryAllocationLib.h>
-+#include <Library/NorFlashInfoLib.h>
-+#include <Library/PcdLib.h>
-+#include <Library/UefiBootServicesTableLib.h>
-+#include <Library/UefiLib.h>
-+
-+#include "NorFlash.h"
-+
-+STATIC CONST NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
-+ NOR_FLASH_SIGNATURE, // Signature
-+ NULL, // Handle
-+
-+ FALSE, // Initialized
-+ NULL, // Initialize
-+
-+ 0, // HostRegisterBaseAddress
-+ 0, // DeviceBaseAddress
-+ 0, // RegionBaseAddress
-+ 0, // Size
-+ 0, // BlockSize
-+ 0, // LastBlock
-+ 0, // StartLba
-+ 0, // OffsetLba
-+
-+ {
-+ FvbGetAttributes, // GetAttributes
-+ FvbSetAttributes, // SetAttributes
-+ FvbGetPhysicalAddress, // GetPhysicalAddress
-+ FvbGetBlockSize, // GetBlockSize
-+ FvbRead, // Read
-+ FvbWrite, // Write
-+ FvbEraseBlocks, // EraseBlocks
-+ NULL, //ParentHandle
-+ }, // FvbProtoccol;
-+ NULL, // ShadowBuffer
-+
-+ {
-+ {
-+ {
-+ HARDWARE_DEVICE_PATH,
-+ HW_VENDOR_DP,
-+ {
-+ (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End)),
-+ (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End) >> 8)
-+ }
-+ },
-+ { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } },
-+ },
-+ 0, // Index
-+
-+ {
-+ END_DEVICE_PATH_TYPE,
-+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
-+ { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
-+ }
-+
-+ }, // DevicePath
-+ 0 // Flags
-+};
-+
-+/**
-+ Execute Flash cmd ctrl and Read Status.
-+
-+ @param[in] Instance NOR flash Instance.
-+ @param[in] Val Value to be written to Flash cmd ctrl Register.
-+
-+ @retval EFI_SUCCESS Request is executed successfully.
-+
-+**/
-+STATIC
-+EFI_STATUS
-+CdnsQspiExecuteCommand (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN UINT32 Val
-+ )
-+{
-+ // Set the command
-+ MmioWrite32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET,
-+ Val);
-+ // Execute the command
-+ MmioWrite32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET,
-+ Val | CDNS_QSPI_FLASH_CMD_CTRL_REG_EXECUTE);
-+
-+ // Wait until command has been executed
-+ while ((MmioRead32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET)
-+ & CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT) == CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT)
-+ continue;
-+
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ Create Nor flash Instance for given region.
-+
-+ @param[in] HostRegisterBase Base address of Nor flash controller.
-+ @param[in] NorFlashDeviceBase Base address of flash device.
-+ @param[in] NorFlashRegionBase Base address of flash region on device.
-+ @param[in] NorFlashSize Size of flash region.
-+ @param[in] Index Index of given flash region.
-+ @param[in] BlockSize Block size of NOR flash device.
-+ @param[in] HasVarStore Boolean set for VarStore on given region.
-+ @param[out] NorFlashInstance Instance of given flash region.
-+
-+ @retval EFI_SUCCESS On successful creation of NOR flash instance.
-+**/
-+EFI_STATUS
-+NorFlashCreateInstance (
-+ IN UINTN HostRegisterBase,
-+ IN UINTN NorFlashDeviceBase,
-+ IN UINTN NorFlashRegionBase,
-+ IN UINTN NorFlashSize,
-+ IN UINT32 Index,
-+ IN UINT32 BlockSize,
-+ IN BOOLEAN HasVarStore,
-+ OUT NOR_FLASH_INSTANCE** NorFlashInstance
-+ )
-+{
-+ EFI_STATUS Status;
-+ NOR_FLASH_INSTANCE* Instance;
-+ NOR_FLASH_INFO *FlashInfo;
-+ UINT8 JedecId[3];
-+
-+ ASSERT(NorFlashInstance != NULL);
-+ Instance = AllocateRuntimeCopyPool (sizeof (mNorFlashInstanceTemplate),
-+ &mNorFlashInstanceTemplate);
-+ if (Instance == NULL) {
-+ return EFI_OUT_OF_RESOURCES;
-+ }
-+
-+ Instance->HostRegisterBaseAddress = HostRegisterBase;
-+ Instance->DeviceBaseAddress = NorFlashDeviceBase;
-+ Instance->RegionBaseAddress = NorFlashRegionBase;
-+ Instance->Size = NorFlashSize;
-+ Instance->BlockSize = BlockSize;
-+ Instance->LastBlock = (NorFlashSize / BlockSize) - 1;
-+
-+ Instance->OffsetLba = (NorFlashRegionBase - NorFlashDeviceBase) / BlockSize;
-+
-+ CopyGuid (&Instance->DevicePath.Vendor.Guid, &gEfiCallerIdGuid);
-+ Instance->DevicePath.Index = (UINT8)Index;
-+
-+ Status = NorFlashReadID (Instance, JedecId);
-+ if (EFI_ERROR (Status)) {
-+ goto FreeInstance;
-+ }
-+
-+ Status = NorFlashGetInfo (JedecId, &FlashInfo, TRUE);
-+ if (EFI_ERROR (Status)) {
-+ goto FreeInstance;
-+ }
-+
-+ NorFlashPrintInfo (FlashInfo);
-+
-+ Instance->Flags = 0;
-+ if (FlashInfo->Flags & NOR_FLASH_WRITE_FSR) {
-+ Instance->Flags = NOR_FLASH_POLL_FSR;
-+ }
-+
-+ Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);
-+ if (Instance->ShadowBuffer == NULL) {
-+ Status = EFI_OUT_OF_RESOURCES;
-+ goto FreeInstance;
-+ }
-+
-+ if (HasVarStore) {
-+ Instance->Initialize = NorFlashFvbInitialize;
-+ }
-+
-+ *NorFlashInstance = Instance;
-+ FreePool (FlashInfo);
-+ return EFI_SUCCESS;
-+
-+FreeInstance:
-+ FreePool (Instance);
-+ return Status;
-+}
-+
-+/**
-+ Check whether NOR flash opertions are Locked.
-+
-+ @param[in] Instance NOR flash Instance.
-+ @param[in] BlockAddress BlockAddress in NOR flash device.
-+
-+ @retval FALSE If NOR flash is not locked.
-+**/
-+STATIC
-+BOOLEAN
-+NorFlashBlockIsLocked (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN UINTN BlockAddress
-+ )
-+{
-+ return FALSE;
-+}
-+
-+/**
-+ Unlock NOR flash operations on given block.
-+
-+ @param[in] Instance NOR flash instance.
-+ @param[in] BlockAddress BlockAddress in NOR flash device.
-+
-+ @retval EFI_SUCCESS NOR flash operations is unlocked.
-+**/
-+STATIC
-+EFI_STATUS
-+NorFlashUnlockSingleBlock (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN UINTN BlockAddress
-+ )
-+{
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ Unlock NOR flash operations if it is necessary.
-+
-+ @param[in] Instance NOR flash instance.
-+ @param[in] BlockAddress BlockAddress in NOR flash device.
-+
-+ @retval EFI_SUCCESS Request is executed successfully.
-+**/
-+STATIC
-+EFI_STATUS
-+NorFlashUnlockSingleBlockIfNecessary (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN UINTN BlockAddress
-+ )
-+{
-+ EFI_STATUS Status;
-+
-+ Status = EFI_SUCCESS;
-+
-+ if (!NorFlashBlockIsLocked (Instance, BlockAddress)) {
-+ Status = NorFlashUnlockSingleBlock (Instance, BlockAddress);
-+ }
-+
-+ return Status;
-+}
-+
-+/**
-+ Enable write to NOR flash device.
-+
-+ @param[in] Instance NOR flash instance.
-+
-+ @retval EFI_SUCCESS Request is executed successfully.
-+**/
-+STATIC
-+EFI_STATUS
-+NorFlashEnableWrite (
-+ IN NOR_FLASH_INSTANCE *Instance
-+ )
-+{
-+
-+ UINT32 val;
-+
-+ DEBUG ((DEBUG_INFO, "NorFlashEnableWrite()\n"));
-+ val = (SPINOR_OP_WREN << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS);
-+ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) {
-+ return EFI_DEVICE_ERROR;
-+ }
-+
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ The following function presumes that the block has already been unlocked.
-+
-+ @param[in] Instance NOR flash instance.
-+ @param[in] BlockAddress Block address within the variable region.
-+
-+ @retval EFI_SUCCESS Request is executed successfully.
-+ **/
-+EFI_STATUS
-+NorFlashEraseSingleBlock (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN UINTN BlockAddress
-+ )
-+{
-+
-+ UINT32 DevConfigVal;
-+ UINT32 EraseOffset;
-+
-+ EraseOffset = 0x0;
-+
-+ DEBUG ((DEBUG_INFO, "NorFlashEraseSingleBlock(BlockAddress=0x%08x)\n",
-+ BlockAddress));
-+
-+ if (EFI_ERROR (NorFlashEnableWrite (Instance))) {
-+ return EFI_DEVICE_ERROR;
-+ }
-+
-+ EraseOffset = BlockAddress - Instance->DeviceBaseAddress;
-+
-+ MmioWrite32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_ADDR_REG_OFFSET,
-+ EraseOffset);
-+
-+ DevConfigVal = SPINOR_OP_BE_4K << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
-+ CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS |
-+ CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS;
-+
-+ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, DevConfigVal))) {
-+ return EFI_DEVICE_ERROR;
-+ }
-+
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ This function unlock and erase an entire NOR Flash block.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] BlockAddress Block address within the variable store region.
-+
-+ @retval EFI_SUCCESS The erase and unlock successfully completed.
-+**/
-+EFI_STATUS
-+NorFlashUnlockAndEraseSingleBlock (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN UINTN BlockAddress
-+ )
-+{
-+ EFI_STATUS Status;
-+ UINTN Index;
-+ NOR_FLASH_LOCK_CONTEXT Lock;
-+ NorFlashLock (&Lock);
-+
-+ Index = 0;
-+ do {
-+ // Unlock the block if we have to
-+ Status = NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddress);
-+ if (EFI_ERROR (Status)) {
-+ break;
-+ }
-+ Status = NorFlashEraseSingleBlock (Instance, BlockAddress);
-+ if (EFI_ERROR (Status)) {
-+ break;
-+ }
-+ Index++;
-+ } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED));
-+
-+ if (Index == NOR_FLASH_ERASE_RETRY) {
-+ DEBUG ((DEBUG_ERROR,
-+ "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n",
-+ BlockAddress,Index));
-+ }
-+
-+ NorFlashUnlock (&Lock);
-+
-+ return Status;
-+}
-+
-+/**
-+ Write a single word to given location.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] WordAddress The address in NOR flash to write given word.
-+ @param[in] WriteData The data to write into NOR flash location.
-+
-+ @retval EFI_SUCCESS The write is completed.
-+**/
-+STATIC
-+EFI_STATUS
-+NorFlashWriteSingleWord (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN UINTN WordAddress,
-+ IN UINT32 WriteData
-+ )
-+{
-+ DEBUG ((DEBUG_INFO,
-+ "NorFlashWriteSingleWord(WordAddress=0x%08x, WriteData=0x%08x)\n",
-+ WordAddress, WriteData));
-+
-+ if (EFI_ERROR (NorFlashEnableWrite (Instance))) {
-+ return EFI_DEVICE_ERROR;
-+ }
-+ MmioWrite32 (WordAddress, WriteData);
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ Write a full block to given location.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] Lba The logical block address in NOR flash.
-+ @param[in] DataBuffer The data to write into NOR flash location.
-+ @param[in] BlockSizeInWords The number of bytes to write.
-+
-+ @retval EFI_SUCCESS The write is completed.
-+**/
-+STATIC
-+EFI_STATUS
-+NorFlashWriteFullBlock (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN EFI_LBA Lba,
-+ IN UINT32 *DataBuffer,
-+ IN UINT32 BlockSizeInWords
-+ )
-+{
-+ EFI_STATUS Status;
-+ UINTN WordAddress;
-+ UINT32 WordIndex;
-+ UINTN BlockAddress;
-+ NOR_FLASH_LOCK_CONTEXT Lock;
-+
-+ Status = EFI_SUCCESS;
-+
-+ // Get the physical address of the block
-+ BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
-+ BlockSizeInWords * 4);
-+
-+ // Start writing from the first address at the start of the block
-+ WordAddress = BlockAddress;
-+
-+ NorFlashLock (&Lock);
-+
-+ Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
-+ if (EFI_ERROR (Status)) {
-+ DEBUG ((DEBUG_ERROR,
-+ "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single block at 0x%X\n",
-+ BlockAddress));
-+ goto EXIT;
-+ }
-+
-+ for (WordIndex=0;
-+ WordIndex < BlockSizeInWords;
-+ WordIndex++, DataBuffer++, WordAddress += 4) {
-+ Status = NorFlashWriteSingleWord (Instance, WordAddress, *DataBuffer);
-+ if (EFI_ERROR (Status)) {
-+ goto EXIT;
-+ }
-+ }
-+
-+EXIT:
-+ NorFlashUnlock (&Lock);
-+
-+ if (EFI_ERROR (Status)) {
-+ DEBUG ((DEBUG_ERROR,
-+ "NOR FLASH Programming [WriteSingleBlock] failed at address 0x%08x. Exit Status = %r.\n",
-+ WordAddress, Status));
-+ }
-+ return Status;
-+}
-+
-+/**
-+ Write a full block.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] Lba The starting logical block index.
-+ @param[in] BufferSizeInBytes The number of bytes to read.
-+ @param[in] Buffer The pointer to a caller-allocated buffer that
-+ contains the source for the write.
-+
-+ @retval EFI_SUCCESS The write is completed.
-+**/
-+EFI_STATUS
-+NorFlashWriteBlocks (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN EFI_LBA Lba,
-+ IN UINTN BufferSizeInBytes,
-+ IN VOID *Buffer
-+ )
-+{
-+ UINT32 *pWriteBuffer;
-+ EFI_STATUS Status;
-+ EFI_LBA CurrentBlock;
-+ UINT32 BlockSizeInWords;
-+ UINT32 NumBlocks;
-+ UINT32 BlockCount;
-+
-+ Status = EFI_SUCCESS;
-+ // The buffer must be valid
-+ if (Buffer == NULL) {
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ // We must have some bytes to read
-+ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: BufferSizeInBytes=0x%x\n",
-+ BufferSizeInBytes));
-+ if (BufferSizeInBytes == 0) {
-+ return EFI_BAD_BUFFER_SIZE;
-+ }
-+
-+ // The size of the buffer must be a multiple of the block size
-+ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: BlockSize in bytes =0x%x\n",
-+ Instance->BlockSize));
-+ if ((BufferSizeInBytes % Instance->BlockSize) != 0) {
-+ return EFI_BAD_BUFFER_SIZE;
-+ }
-+
-+ // All blocks must be within the device
-+ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->BlockSize;
-+
-+ DEBUG ((DEBUG_INFO,
-+ "NorFlashWriteBlocks: NumBlocks=%d, LastBlock=%ld, Lba=%ld.\n", NumBlocks,
-+ Instance->LastBlock, Lba));
-+
-+ if ((Lba + NumBlocks) > (Instance->LastBlock + 1)) {
-+ DEBUG ((DEBUG_ERROR,
-+ "NorFlashWriteBlocks: ERROR - Write will exceed last block.\n"));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ ASSERT (((UINTN)Buffer % sizeof (UINT32)) == 0);
-+
-+ BlockSizeInWords = Instance->BlockSize / 4;
-+
-+ // Because the target *Buffer is a pointer to VOID, we must put
-+ // all the data into a pointer to a proper data type, so use *ReadBuffer
-+ pWriteBuffer = (UINT32 *)Buffer;
-+
-+ CurrentBlock = Lba;
-+ for (BlockCount = 0;
-+ BlockCount < NumBlocks;
-+ BlockCount++, CurrentBlock++, pWriteBuffer += BlockSizeInWords) {
-+
-+ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: Writing block #%d\n",
-+ (UINTN)CurrentBlock));
-+
-+ Status = NorFlashWriteFullBlock (
-+ Instance,
-+ CurrentBlock,
-+ pWriteBuffer,
-+ BlockSizeInWords
-+ );
-+
-+ if (EFI_ERROR (Status)) {
-+ break;
-+ }
-+ }
-+
-+ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: Exit Status = %r.\n", Status));
-+ return Status;
-+}
-+
-+/**
-+ Read a full block.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] Lba The starting logical block index to read from.
-+ @param[in] BufferSizeInBytes The number of bytes to read.
-+ @param[out] Buffer The pointer to a caller-allocated buffer that
-+ should be copied with read data.
-+
-+ @retval EFI_SUCCESS The read is completed.
-+**/
-+EFI_STATUS
-+NorFlashReadBlocks (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN EFI_LBA Lba,
-+ IN UINTN BufferSizeInBytes,
-+ OUT VOID *Buffer
-+ )
-+{
-+ UINT32 NumBlocks;
-+ UINTN StartAddress;
-+ DEBUG ((DEBUG_INFO,
-+ "NorFlashReadBlocks: BufferSize=0x%xB BlockSize=0x%xB LastBlock=%ld, Lba=%ld.\n",
-+ BufferSizeInBytes, Instance->BlockSize, Instance->LastBlock,
-+ Lba));
-+
-+ // The buffer must be valid
-+ if (Buffer == NULL) {
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ // Return if we do not have any byte to read
-+ if (BufferSizeInBytes == 0) {
-+ return EFI_SUCCESS;
-+ }
-+
-+ // The size of the buffer must be a multiple of the block size
-+ if ((BufferSizeInBytes % Instance->BlockSize) != 0) {
-+ return EFI_BAD_BUFFER_SIZE;
-+ }
-+
-+ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->BlockSize;
-+
-+ if ((Lba + NumBlocks) > (Instance->LastBlock + 1)) {
-+ DEBUG ((DEBUG_ERROR,
-+ "NorFlashReadBlocks: ERROR - Read will exceed last block\n"));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ // Get the address to start reading from
-+ StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
-+ Instance->BlockSize);
-+
-+ // Readout the data
-+ CopyMem(Buffer, (UINTN *)StartAddress, BufferSizeInBytes);
-+
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ Read from nor flash.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] Lba The starting logical block index to read from.
-+ @param[in] Offset Offset into the block at which to begin reading.
-+ @param[in] BufferSizeInBytes The number of bytes to read.
-+ @param[out] Buffer The pointer to a caller-allocated buffer that
-+ should copied with read data.
-+
-+ @retval EFI_SUCCESS The read is completed.
-+**/
-+EFI_STATUS
-+NorFlashRead (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN EFI_LBA Lba,
-+ IN UINTN Offset,
-+ IN UINTN BufferSizeInBytes,
-+ OUT VOID *Buffer
-+ )
-+{
-+ UINTN StartAddress;
-+ // The buffer must be valid
-+ if (Buffer == NULL) {
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ // Return if we do not have any byte to read
-+ if (BufferSizeInBytes == 0) {
-+ return EFI_SUCCESS;
-+ }
-+
-+ if (((Lba * Instance->BlockSize) + Offset + BufferSizeInBytes) >
-+ Instance->Size) {
-+ DEBUG ((DEBUG_ERROR,
-+ "NorFlashRead: ERROR - Read will exceed device size.\n"));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ // Get the address to start reading from
-+ StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
-+ Instance->BlockSize);
-+
-+ // Readout the data
-+ CopyMem (Buffer, (UINTN *)(StartAddress + Offset), BufferSizeInBytes);
-+
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ Write a full or portion of a block.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] Lba The starting logical block index to write to.
-+ @param[in] Offset Offset into the block at which to begin writing.
-+ @param[in, out] NumBytes The total size of the buffer.
-+ @param[in] Buffer The pointer to a caller-allocated buffer that
-+ contains the source for the write.
-+
-+ @retval EFI_SUCCESS The write is completed.
-+**/
-+EFI_STATUS
-+NorFlashWriteSingleBlock (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN EFI_LBA Lba,
-+ IN UINTN Offset,
-+ IN OUT UINTN *NumBytes,
-+ IN UINT8 *Buffer
-+ )
-+{
-+ EFI_STATUS Status;
-+ UINT32 Tmp;
-+ UINT32 TmpBuf;
-+ UINT32 WordToWrite;
-+ UINT32 Mask;
-+ BOOLEAN DoErase;
-+ UINTN BytesToWrite;
-+ UINTN CurOffset;
-+ UINTN WordAddr;
-+ UINTN BlockSize;
-+ UINTN BlockAddress;
-+ UINTN PrevBlockAddress;
-+
-+ if (Buffer == NULL) {
-+ DEBUG ((DEBUG_ERROR,
-+ "NorFlashWriteSingleBlock: ERROR - Buffer is invalid\n" ));
-+ return EFI_OUT_OF_RESOURCES;
-+ }
-+
-+ PrevBlockAddress = 0;
-+ if (!Instance->Initialized && Instance->Initialize) {
-+ Instance->Initialize(Instance);
-+ }
-+
-+ DEBUG ((DEBUG_INFO,
-+ "NorFlashWriteSingleBlock(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n",
-+ Lba, Offset, *NumBytes, Buffer));
-+
-+ // Localise the block size to avoid de-referencing pointers all the time
-+ BlockSize = Instance->BlockSize;
-+
-+ // The write must not span block boundaries.
-+ // We need to check each variable individually because adding two large
-+ // values together overflows.
-+ if (Offset >= BlockSize ||
-+ *NumBytes > BlockSize ||
-+ (Offset + *NumBytes) > BlockSize) {
-+ DEBUG ((DEBUG_ERROR,
-+ "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
-+ Offset, *NumBytes, BlockSize ));
-+ return EFI_BAD_BUFFER_SIZE;
-+ }
-+
-+ // We must have some bytes to write
-+ if (*NumBytes == 0) {
-+ DEBUG ((DEBUG_ERROR,
-+ "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
-+ Offset, *NumBytes, BlockSize ));
-+ return EFI_BAD_BUFFER_SIZE;
-+ }
-+
-+ // Pick 128bytes as a good start for word operations as opposed to erasing the
-+ // block and writing the data regardless if an erase is really needed.
-+ // It looks like most individual NV variable writes are smaller than 128bytes.
-+ if (*NumBytes <= 128) {
-+ // Check to see if we need to erase before programming the data into NOR.
-+ // If the destination bits are only changing from 1s to 0s we can just write.
-+ // After a block is erased all bits in the block is set to 1.
-+ // If any byte requires us to erase we just give up and rewrite all of it.
-+ DoErase = FALSE;
-+ BytesToWrite = *NumBytes;
-+ CurOffset = Offset;
-+
-+ while (BytesToWrite > 0) {
-+ // Read full word from NOR, splice as required. A word is the smallest
-+ // unit we can write.
-+ Status = NorFlashRead (
-+ Instance,
-+ Lba,
-+ CurOffset & ~(0x3),
-+ sizeof(Tmp),
-+ &Tmp
-+ );
-+ if (EFI_ERROR (Status)) {
-+ return EFI_DEVICE_ERROR;
-+ }
-+
-+ // Physical address of word in NOR to write.
-+ WordAddr = (CurOffset & ~(0x3)) +
-+ GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
-+ BlockSize);
-+
-+ // The word of data that is to be written.
-+ TmpBuf = ReadUnaligned32 ((UINT32 *)(Buffer + (*NumBytes - BytesToWrite)));
-+
-+ // First do word aligned chunks.
-+ if ((CurOffset & 0x3) == 0) {
-+ if (BytesToWrite >= 4) {
-+ // Is the destination still in 'erased' state?
-+ if (~Tmp != 0) {
-+ // Check to see if we are only changing bits to zero.
-+ if ((Tmp ^ TmpBuf) & TmpBuf) {
-+ DoErase = TRUE;
-+ break;
-+ }
-+ }
-+ // Write this word to NOR
-+ WordToWrite = TmpBuf;
-+ CurOffset += sizeof(TmpBuf);
-+ BytesToWrite -= sizeof(TmpBuf);
-+ } else {
-+ // BytesToWrite < 4. Do small writes and left-overs
-+ Mask = ~((~0) << (BytesToWrite * 8));
-+ // Mask out the bytes we want.
-+ TmpBuf &= Mask;
-+ // Is the destination still in 'erased' state?
-+ if ((Tmp & Mask) != Mask) {
-+ // Check to see if we are only changing bits to zero.
-+ if ((Tmp ^ TmpBuf) & TmpBuf) {
-+ DoErase = TRUE;
-+ break;
-+ }
-+ }
-+ // Merge old and new data. Write merged word to NOR
-+ WordToWrite = (Tmp & ~Mask) | TmpBuf;
-+ CurOffset += BytesToWrite;
-+ BytesToWrite = 0;
-+ }
-+ } else {
-+ // Do multiple words, but starting unaligned.
-+ if (BytesToWrite > (4 - (CurOffset & 0x3))) {
-+ Mask = ((~0) << ((CurOffset & 0x3) * 8));
-+ // Mask out the bytes we want.
-+ TmpBuf &= Mask;
-+ // Is the destination still in 'erased' state?
-+ if ((Tmp & Mask) != Mask) {
-+ // Check to see if we are only changing bits to zero.
-+ if ((Tmp ^ TmpBuf) & TmpBuf) {
-+ DoErase = TRUE;
-+ break;
-+ }
-+ }
-+ // Merge old and new data. Write merged word to NOR
-+ WordToWrite = (Tmp & ~Mask) | TmpBuf;
-+ BytesToWrite -= (4 - (CurOffset & 0x3));
-+ CurOffset += (4 - (CurOffset & 0x3));
-+ } else {
-+ // Unaligned and fits in one word.
-+ Mask = (~((~0) << (BytesToWrite * 8))) << ((CurOffset & 0x3) * 8);
-+ // Mask out the bytes we want.
-+ TmpBuf = (TmpBuf << ((CurOffset & 0x3) * 8)) & Mask;
-+ // Is the destination still in 'erased' state?
-+ if ((Tmp & Mask) != Mask) {
-+ // Check to see if we are only changing bits to zero.
-+ if ((Tmp ^ TmpBuf) & TmpBuf) {
-+ DoErase = TRUE;
-+ break;
-+ }
-+ }
-+ // Merge old and new data. Write merged word to NOR
-+ WordToWrite = (Tmp & ~Mask) | TmpBuf;
-+ CurOffset += BytesToWrite;
-+ BytesToWrite = 0;
-+ }
-+ }
-+
-+ BlockAddress = GET_NOR_BLOCK_ADDRESS (
-+ Instance->RegionBaseAddress,
-+ Lba,
-+ BlockSize
-+ );
-+ if (BlockAddress != PrevBlockAddress) {
-+ Status = NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddress);
-+ if (EFI_ERROR (Status)) {
-+ return EFI_DEVICE_ERROR;
-+ }
-+ PrevBlockAddress = BlockAddress;
-+ }
-+ Status = NorFlashWriteSingleWord (Instance, WordAddr, WordToWrite);
-+ if (EFI_ERROR (Status)) {
-+ return EFI_DEVICE_ERROR;
-+ }
-+ }
-+ // Exit if we got here and could write all the data. Otherwise do the
-+ // Erase-Write cycle.
-+ if (!DoErase) {
-+ return EFI_SUCCESS;
-+ }
-+ }
-+
-+ // Check we did get some memory. Buffer is BlockSize.
-+ if (Instance->ShadowBuffer == NULL) {
-+ DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n"));
-+ return EFI_DEVICE_ERROR;
-+ }
-+
-+ // Read NOR Flash data into shadow buffer
-+ Status = NorFlashReadBlocks (
-+ Instance,
-+ Lba,
-+ BlockSize,
-+ Instance->ShadowBuffer
-+ );
-+ if (EFI_ERROR (Status)) {
-+ // Return one of the pre-approved error statuses
-+ return EFI_DEVICE_ERROR;
-+ }
-+
-+ // Put the data at the appropriate location inside the buffer area
-+ CopyMem ((VOID*)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumBytes);
-+
-+ // Write the modified buffer back to the NorFlash
-+ Status = NorFlashWriteBlocks (
-+ Instance,
-+ Lba,
-+ BlockSize,
-+ Instance->ShadowBuffer
-+ );
-+ if (EFI_ERROR (Status)) {
-+ // Return one of the pre-approved error statuses
-+ return EFI_DEVICE_ERROR;
-+ }
-+
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ Read JEDEC ID of NOR flash device.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[out] JedecId JEDEC ID of NOR flash device.
-+
-+ @retval EFI_SUCCESS The write is completed.
-+**/
-+EFI_STATUS
-+NorFlashReadID (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ OUT UINT8 JedecId[3]
-+ )
-+{
-+ UINT32 val;
-+ if (Instance == NULL || JedecId == NULL) {
-+ return EFI_INVALID_PARAMETER;
-+ }
-+
-+ val = SPINOR_OP_RDID << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
-+ CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS |
-+ CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS;
-+
-+ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) {
-+ return EFI_DEVICE_ERROR;
-+ }
-+
-+ val = MmioRead32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET);
-+
-+ // Manu.ID field
-+ JedecId[0] = (UINT8) val;
-+ // Type field
-+ JedecId[1] = (UINT8) (val >> 8);
-+ // Capacity field
-+ JedecId[2] = (UINT8) (val >> 16);
-+
-+ DEBUG ((DEBUG_INFO,
-+ "Nor flash detected, Jedec ID, Manu.Id=%x Type=%x Capacity=%x \n",
-+ JedecId[0],JedecId[1],JedecId[2]));
-+
-+ return EFI_SUCCESS;
-+}
-diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
-new file mode 100644
-index 00000000..e720937e
---- /dev/null
-+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
-@@ -0,0 +1,484 @@
-+/** @file
-+
-+ Copyright (c) 2023, ARM Limited. All rights reserved.<BR>
-+
-+ SPDX-License-Identifier: BSD-2-Clause-Patent
-+
-+**/
-+
-+#ifndef NOR_FLASH_DXE_H_
-+#define NOR_FLASH_DXE_H_
-+
-+#include <Guid/EventGroup.h>
-+#include <Library/DebugLib.h>
-+#include <Library/IoLib.h>
-+#include <Library/NorFlashPlatformLib.h>
-+#include <PiDxe.h>
-+#include <Protocol/BlockIo.h>
-+#include <Protocol/DiskIo.h>
-+#include <Protocol/FirmwareVolumeBlock.h>
-+
-+#include "CadenceQspiReg.h"
-+
-+#define NOR_FLASH_ERASE_RETRY 10
-+
-+#define GET_NOR_BLOCK_ADDRESS(BaseAddr, Lba, LbaSize) \
-+ ((BaseAddr) + (UINTN)((Lba) * (LbaSize)))
-+
-+#define NOR_FLASH_SIGNATURE SIGNATURE_32('S', 'n', 'o', 'r')
-+#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, \
-+ NOR_FLASH_SIGNATURE)
-+
-+#define NOR_FLASH_POLL_FSR BIT0
-+
-+typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
-+
-+typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
-+
-+#pragma pack(1)
-+typedef struct {
-+ VENDOR_DEVICE_PATH Vendor;
-+ UINT8 Index;
-+ EFI_DEVICE_PATH_PROTOCOL End;
-+} NOR_FLASH_DEVICE_PATH;
-+#pragma pack()
-+
-+struct _NOR_FLASH_INSTANCE {
-+ UINT32 Signature;
-+ EFI_HANDLE Handle;
-+
-+ BOOLEAN Initialized;
-+ NOR_FLASH_INITIALIZE Initialize;
-+
-+ UINTN HostRegisterBaseAddress;
-+ UINTN DeviceBaseAddress;
-+ UINTN RegionBaseAddress;
-+ UINTN Size;
-+ UINTN BlockSize;
-+ UINTN LastBlock;
-+ EFI_LBA StartLba;
-+ EFI_LBA OffsetLba;
-+
-+ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
-+ VOID* ShadowBuffer;
-+
-+ NOR_FLASH_DEVICE_PATH DevicePath;
-+
-+ UINT32 Flags;
-+};
-+
-+typedef struct {
-+ EFI_TPL OriginalTPL;
-+ BOOLEAN InterruptsEnabled;
-+} NOR_FLASH_LOCK_CONTEXT;
-+
-+/**
-+ Lock all pending read/write to Nor flash device
-+
-+ @param[in] Context Nor flash device context structure.
-+**/
-+VOID
-+EFIAPI
-+NorFlashLock (
-+ IN NOR_FLASH_LOCK_CONTEXT *Context
-+ );
-+
-+/**
-+ Unlock all pending read/write to Nor flash device
-+
-+ @param[in] Context Nor flash device context structure.
-+**/
-+VOID
-+EFIAPI
-+NorFlashUnlock (
-+ IN NOR_FLASH_LOCK_CONTEXT *Context
-+ );
-+
-+extern UINTN mFlashNvStorageVariableBase;
-+
-+/**
-+ Create Nor flash Instance for given region.
-+
-+ @param[in] HostRegisterBase Base address of Nor flash controller.
-+ @param[in] NorFlashDeviceBase Base address of flash device.
-+ @param[in] NorFlashRegionBase Base address of flash region on device.
-+ @param[in] NorFlashSize Size of flash region.
-+ @param[in] Index Index of given flash region.
-+ @param[in] BlockSize Block size of NOR flash device.
-+ @param[in] HasVarStore Boolean set for VarStore on given region.
-+ @param[out] NorFlashInstance Instance of given flash region.
-+
-+ @retval EFI_SUCCESS On successful creation of NOR flash instance.
-+**/
-+EFI_STATUS
-+NorFlashCreateInstance (
-+ IN UINTN HostRegisterBase,
-+ IN UINTN NorFlashDeviceBase,
-+ IN UINTN NorFlashRegionBase,
-+ IN UINTN NorFlashSize,
-+ IN UINT32 Index,
-+ IN UINT32 BlockSize,
-+ IN BOOLEAN HasVarStore,
-+ OUT NOR_FLASH_INSTANCE** NorFlashInstance
-+ );
-+
-+/**
-+ Install Fv block on to variable store region
-+
-+ @param[in] Instance Instance of Nor flash variable region.
-+
-+ @retval EFI_SUCCESS The entry point is executed successfully.
-+**/
-+EFI_STATUS
-+EFIAPI
-+NorFlashFvbInitialize (
-+ IN NOR_FLASH_INSTANCE* Instance
-+ );
-+
-+/**
-+ Check the integrity of firmware volume header.
-+
-+ @param[in] Instance Instance of Nor flash variable region.
-+
-+ @retval EFI_SUCCESS The firmware volume is consistent.
-+ @retval EFI_NOT_FOUND The firmware volume has been corrupted.
-+
-+**/
-+EFI_STATUS
-+ValidateFvHeader (
-+ IN NOR_FLASH_INSTANCE *Instance
-+ );
-+
-+/**
-+ Initialize the FV Header and Variable Store Header
-+ to support variable operations.
-+
-+ @param[in] Instance Location to Initialize the headers
-+
-+ @retval EFI_SUCCESS Fv init is done
-+
-+**/
-+EFI_STATUS
-+InitializeFvAndVariableStoreHeaders (
-+ IN NOR_FLASH_INSTANCE *Instance
-+ );
-+
-+/**
-+ Retrieves the attributes and current settings of the block.
-+
-+ @param[in] This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[out] Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
-+ current settings are returned.
-+ Type EFI_FVB_ATTRIBUTES_2 is defined in
-+ EFI_FIRMWARE_VOLUME_HEADER.
-+
-+ @retval EFI_SUCCESS The firmware volume attributes were returned.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbGetAttributes(
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
-+ );
-+
-+/**
-+ Sets configurable firmware volume attributes and returns the
-+ new settings of the firmware volume.
-+
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[in, out] Attributes On input, Attributes is a pointer to
-+ EFI_FVB_ATTRIBUTES_2 that contains the desired
-+ firmware volume settings.
-+ On successful return, it contains the new
-+ settings of the firmware volume.
-+
-+ @retval EFI_UNSUPPORTED The firmware volume attributes are not supported.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbSetAttributes(
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
-+ );
-+
-+/**
-+ Retrieves the base address of a memory-mapped firmware volume.
-+ This function should be called only for memory-mapped firmware volumes.
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[out] Address Pointer to a caller-allocated
-+ EFI_PHYSICAL_ADDRESS that, on successful
-+ return from GetPhysicalAddress(), contains the
-+ base address of the firmware volume.
-+
-+ @retval EFI_SUCCESS The firmware volume base address was returned.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbGetPhysicalAddress(
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ OUT EFI_PHYSICAL_ADDRESS *Address
-+ );
-+
-+/**
-+ Retrieves the size of the requested block.
-+ It also returns the number of additional blocks with the identical size.
-+ The GetBlockSize() function is used to retrieve the block map
-+ (see EFI_FIRMWARE_VOLUME_HEADER).
-+
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[in] Lba Indicates the block whose size to return
-+
-+ @param[out] BlockSize Pointer to a caller-allocated UINTN in which
-+ the size of the block is returned.
-+
-+ @param[out] NumberOfBlocks Pointer to a caller-allocated UINTN in
-+ which the number of consecutive blocks,
-+ starting with Lba, is returned. All
-+ blocks in this range have a size of
-+ BlockSize.
-+
-+ @retval EFI_SUCCESS The firmware volume base address was returned.
-+
-+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbGetBlockSize(
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ IN EFI_LBA Lba,
-+ OUT UINTN *BlockSize,
-+ OUT UINTN *NumberOfBlocks
-+ );
-+
-+/**
-+ Reads the specified number of bytes into a buffer from the specified block.
-+
-+ The Read() function reads the requested number of bytes from the
-+ requested block and stores them in the provided buffer.
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[in] Lba The starting logical block index from which to read
-+
-+ @param[in] Offset Offset into the block at which to begin reading.
-+
-+ @param[in, out] NumBytes Pointer to a UINTN.
-+ At entry, *NumBytes contains the total size of the
-+ buffer. *NumBytes should have a non zero value.
-+ At exit, *NumBytes contains the total number of
-+ bytes read.
-+
-+ @param[in out] Buffer Pointer to a caller-allocated buffer that will be
-+ used to hold the data that is read.
-+
-+ @retval EFI_SUCCESS The firmware volume was read successfully, and
-+ contents are in Buffer.
-+
-+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
-+
-+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and
-+ could not be read.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbRead(
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ IN EFI_LBA Lba,
-+ IN UINTN Offset,
-+ IN OUT UINTN *NumBytes,
-+ IN OUT UINT8 *Buffer
-+ );
-+
-+/**
-+ Writes the specified number of bytes from the input buffer to the block.
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[in] Lba The starting logical block index to write to.
-+
-+ @param[in] Offset Offset into the block at which to begin writing.
-+
-+ @param[in, out] NumBytes The pointer to a UINTN.
-+ At entry, *NumBytes contains the total size of the
-+ buffer.
-+ At exit, *NumBytes contains the total number of
-+ bytes actually written.
-+
-+ @param[in] Buffer The pointer to a caller-allocated buffer that
-+ contains the source for the write.
-+
-+ @retval EFI_SUCCESS The firmware volume was written successfully.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbWrite(
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ IN EFI_LBA Lba,
-+ IN UINTN Offset,
-+ IN OUT UINTN *NumBytes,
-+ IN UINT8 *Buffer
-+ );
-+
-+/**
-+ Erases and initialises a firmware volume block.
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
-+
-+ @param[in] ... The variable argument list is a list of tuples.
-+ Each tuple describes a range of LBAs to erase
-+ and consists of the following:
-+ - An EFI_LBA that indicates the starting LBA
-+ - A UINTN that indicates the number of blocks
-+ to erase.
-+
-+ The list is terminated with an
-+ EFI_LBA_LIST_TERMINATOR.
-+
-+ @retval EFI_SUCCESS The erase request successfully completed.
-+
-+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
-+ state.
-+
-+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly
-+ and could not be written.
-+ The firmware device may have been partially
-+ erased.
-+
-+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable
-+ argument list do not exist in the firmware
-+ volume.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbEraseBlocks(
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ ...
-+ );
-+
-+/**
-+ This function unlock and erase an entire NOR Flash block.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] BlockAddress Block address within the variable store region.
-+
-+ @retval EFI_SUCCESS The erase and unlock successfully completed.
-+**/
-+EFI_STATUS
-+NorFlashUnlockAndEraseSingleBlock (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN UINTN BlockAddress
-+ );
-+
-+/**
-+ Write a full or portion of a block.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] Lba The starting logical block index to write to.
-+ @param[in] Offset Offset into the block at which to begin writing.
-+ @param[in,out] NumBytes The total size of the buffer.
-+ @param[in] Buffer The pointer to a caller-allocated buffer that
-+ contains the source for the write.
-+
-+ @retval EFI_SUCCESS The write is completed.
-+**/
-+EFI_STATUS
-+NorFlashWriteSingleBlock (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN EFI_LBA Lba,
-+ IN UINTN Offset,
-+ IN OUT UINTN *NumBytes,
-+ IN UINT8 *Buffer
-+ );
-+
-+/**
-+ Write a full block.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] Lba The starting logical block index to write to.
-+ @param[in] BufferSizeInBytes The number of bytes to write.
-+ @param[in] Buffer The pointer to a caller-allocated buffer that
-+ contains the source for the write.
-+
-+ @retval EFI_SUCCESS The write is completed.
-+**/
-+EFI_STATUS
-+NorFlashWriteBlocks (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN EFI_LBA Lba,
-+ IN UINTN BufferSizeInBytes,
-+ IN VOID *Buffer
-+ );
-+
-+/**
-+ Read a full block.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] Lba The starting logical block index to read from.
-+ @param[in] BufferSizeInBytes The number of bytes to read.
-+ @param[out] Buffer The pointer to a caller-allocated buffer that
-+ should be copied with read data.
-+
-+ @retval EFI_SUCCESS The read is completed.
-+**/
-+EFI_STATUS
-+NorFlashReadBlocks (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN EFI_LBA Lba,
-+ IN UINTN BufferSizeInBytes,
-+ OUT VOID *Buffer
-+ );
-+
-+/**
-+ Read from nor flash.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[in] Lba The starting logical block index to read from.
-+ @param[in] Offset Offset into the block at which to begin reading.
-+ @param[in] BufferSizeInBytes The number of bytes to read.
-+ @param[out] Buffer The pointer to a caller-allocated buffer that
-+ should copied with read data.
-+
-+ @retval EFI_SUCCESS The read is completed.
-+**/
-+EFI_STATUS
-+NorFlashRead (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ IN EFI_LBA Lba,
-+ IN UINTN Offset,
-+ IN UINTN BufferSizeInBytes,
-+ OUT VOID *Buffer
-+ );
-+
-+/**
-+ Read JEDEC ID of NOR flash device.
-+
-+ @param[in] Instance NOR flash Instance of variable store region.
-+ @param[out] JedecId JEDEC ID of NOR flash device.
-+
-+ @retval EFI_SUCCESS The write is completed.
-+**/
-+EFI_STATUS
-+NorFlashReadID (
-+ IN NOR_FLASH_INSTANCE *Instance,
-+ OUT UINT8 JedecId[3]
-+ );
-+
-+#define SPINOR_OP_WREN 0x06 // Write enable
-+#define SPINOR_OP_BE_4K 0x20 // Erase 4KiB block
-+#define SPINOR_OP_RDID 0x9f // Read JEDEC ID
-+
-+#endif /* NOR_FLASH_DXE_H_ */
-diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c
-new file mode 100644
-index 00000000..edd84c07
---- /dev/null
-+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c
-@@ -0,0 +1,573 @@
-+/** @file
-+
-+ Copyright (c) 2023, ARM Limited. All rights reserved.<BR>
-+
-+ SPDX-License-Identifier: BSD-2-Clause-Patent
-+
-+**/
-+
-+#include <Guid/VariableFormat.h>
-+#include <Guid/SystemNvDataGuid.h>
-+
-+#include <Library/BaseLib.h>
-+#include <Library/BaseMemoryLib.h>
-+#include <Library/MemoryAllocationLib.h>
-+#include <Library/PcdLib.h>
-+#include <Library/UefiBootServicesTableLib.h>
-+#include <Library/UefiLib.h>
-+
-+#include <PiDxe.h>
-+
-+#include "NorFlash.h"
-+
-+UINTN mFlashNvStorageVariableBase;
-+
-+/**
-+ Initialize the FV Header and Variable Store Header
-+ to support variable operations.
-+
-+ @param[in] Instance Location to initialise the headers.
-+
-+ @retval EFI_SUCCESS Fv init is done.
-+
-+**/
-+EFI_STATUS
-+InitializeFvAndVariableStoreHeaders (
-+ IN NOR_FLASH_INSTANCE *Instance
-+ )
-+{
-+ EFI_STATUS Status;
-+ VOID* Headers;
-+ UINTN HeadersLength;
-+ EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;
-+ VARIABLE_STORE_HEADER *VariableStoreHeader;
-+
-+ if (!Instance->Initialized && Instance->Initialize) {
-+ Instance->Initialize (Instance);
-+ }
-+
-+ HeadersLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) +
-+ sizeof (EFI_FV_BLOCK_MAP_ENTRY) +
-+ sizeof (VARIABLE_STORE_HEADER);
-+ Headers = AllocateZeroPool (HeadersLength);
-+
-+ FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers;
-+ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
-+ FirmwareVolumeHeader->FvLength =
-+ PcdGet32 (PcdFlashNvStorageVariableSize) +
-+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
-+ PcdGet32 (PcdFlashNvStorageFtwSpareSize);
-+ FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
-+ FirmwareVolumeHeader->Attributes = EFI_FVB2_READ_ENABLED_CAP |
-+ EFI_FVB2_READ_STATUS |
-+ EFI_FVB2_STICKY_WRITE |
-+ EFI_FVB2_MEMORY_MAPPED |
-+ EFI_FVB2_ERASE_POLARITY |
-+ EFI_FVB2_WRITE_STATUS |
-+ EFI_FVB2_WRITE_ENABLED_CAP;
-+
-+ FirmwareVolumeHeader->HeaderLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) +
-+ sizeof (EFI_FV_BLOCK_MAP_ENTRY);
-+ FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
-+ FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->LastBlock + 1;
-+ FirmwareVolumeHeader->BlockMap[0].Length = Instance->BlockSize;
-+ FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
-+ FirmwareVolumeHeader->BlockMap[1].Length = 0;
-+ FirmwareVolumeHeader->Checksum = CalculateCheckSum16 (
-+ (UINT16*)FirmwareVolumeHeader,
-+ FirmwareVolumeHeader->HeaderLength);
-+
-+ VariableStoreHeader = (VOID *)((UINTN)Headers +
-+ FirmwareVolumeHeader->HeaderLength);
-+ CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid);
-+ VariableStoreHeader->Size = PcdGet32 (PcdFlashNvStorageVariableSize) -
-+ FirmwareVolumeHeader->HeaderLength;
-+ VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
-+ VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
-+
-+ // Install the combined super-header in the NorFlash
-+ Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
-+
-+ FreePool (Headers);
-+ return Status;
-+}
-+
-+/**
-+ Check the integrity of firmware volume header.
-+
-+ @param[in] Instance Instance of Nor flash variable region.
-+
-+ @retval EFI_SUCCESS The firmware volume is consistent.
-+ @retval EFI_NOT_FOUND The firmware volume has been corrupted.
-+
-+**/
-+EFI_STATUS
-+ValidateFvHeader (
-+ IN NOR_FLASH_INSTANCE *Instance
-+ )
-+{
-+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
-+ VARIABLE_STORE_HEADER *VariableStoreHeader;
-+ UINTN VariableStoreLength;
-+ UINTN FvLength;
-+
-+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Instance->RegionBaseAddress;
-+
-+ FvLength = PcdGet32 (PcdFlashNvStorageVariableSize) +
-+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
-+ PcdGet32 (PcdFlashNvStorageFtwSpareSize);
-+
-+ if ((FwVolHeader->Revision != EFI_FVH_REVISION)
-+ || (FwVolHeader->Signature != EFI_FVH_SIGNATURE)
-+ || (FwVolHeader->FvLength != FvLength)
-+ )
-+ {
-+ DEBUG ((DEBUG_ERROR, "%a: No Firmware Volume header present\n",
-+ __FUNCTION__));
-+ return EFI_NOT_FOUND;
-+ }
-+
-+ // Check the Firmware Volume Guid
-+ if (!CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)) {
-+ DEBUG ((DEBUG_ERROR, "%a: Firmware Volume Guid non-compatible\n",
-+ __FUNCTION__));
-+ return EFI_NOT_FOUND;
-+ }
-+
-+ VariableStoreHeader = (VOID *)((UINTN)FwVolHeader +
-+ FwVolHeader->HeaderLength);
-+
-+ // Check the Variable Store Guid
-+ if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) &&
-+ !CompareGuid (&VariableStoreHeader->Signature,
-+ &gEfiAuthenticatedVariableGuid)) {
-+ DEBUG ((DEBUG_ERROR, "%a: Variable Store Guid non-compatible\n",
-+ __FUNCTION__));
-+ return EFI_NOT_FOUND;
-+ }
-+
-+ VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) -
-+ FwVolHeader->HeaderLength;
-+ if (VariableStoreHeader->Size != VariableStoreLength) {
-+ DEBUG ((DEBUG_ERROR, "%a: Variable Store Length does not match\n",
-+ __FUNCTION__));
-+ return EFI_NOT_FOUND;
-+ }
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ Retrieves the attributes and current settings of the block.
-+
-+ @param[in] This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[out] Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
-+ current settings are returned.
-+ Type EFI_FVB_ATTRIBUTES_2 is defined in
-+ EFI_FIRMWARE_VOLUME_HEADER.
-+
-+ @retval EFI_SUCCESS The firmware volume attributes were returned.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbGetAttributes(
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
-+ )
-+{
-+ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
-+
-+ FlashFvbAttributes = EFI_FVB2_READ_ENABLED_CAP | EFI_FVB2_READ_STATUS |
-+ EFI_FVB2_WRITE_ENABLED_CAP | EFI_FVB2_WRITE_STATUS |
-+ EFI_FVB2_STICKY_WRITE | EFI_FVB2_MEMORY_MAPPED |
-+ EFI_FVB2_ERASE_POLARITY;
-+
-+ *Attributes = FlashFvbAttributes;
-+
-+ DEBUG ((DEBUG_INFO, "FvbGetAttributes(0x%X)\n", *Attributes));
-+
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ Sets configurable firmware volume attributes and returns the
-+ new settings of the firmware volume.
-+
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[in, out] Attributes On input, Attributes is a pointer to
-+ EFI_FVB_ATTRIBUTES_2 that contains the desired
-+ firmware volume settings.
-+ On successful return, it contains the new
-+ settings of the firmware volume.
-+
-+ @retval EFI_UNSUPPORTED The firmware volume attributes are not supported.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbSetAttributes(
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
-+ )
-+{
-+ DEBUG ((DEBUG_INFO, "FvbSetAttributes(0x%X) is not supported\n",
-+ *Attributes));
-+ return EFI_UNSUPPORTED;
-+}
-+
-+/**
-+ Retrieves the base address of a memory-mapped firmware volume.
-+ This function should be called only for memory-mapped firmware volumes.
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[out] Address Pointer to a caller-allocated
-+ EFI_PHYSICAL_ADDRESS that, on successful
-+ return from GetPhysicalAddress(), contains the
-+ base address of the firmware volume.
-+
-+ @retval EFI_SUCCESS The firmware volume base address was returned.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbGetPhysicalAddress (
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ OUT EFI_PHYSICAL_ADDRESS *Address
-+ )
-+{
-+ NOR_FLASH_INSTANCE *Instance;
-+
-+ Instance = INSTANCE_FROM_FVB_THIS (This);
-+
-+ DEBUG ((DEBUG_INFO, "FvbGetPhysicalAddress(BaseAddress=0x%08x)\n",
-+ Instance->RegionBaseAddress));
-+
-+ ASSERT(Address != NULL);
-+
-+ *Address = Instance->RegionBaseAddress;
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ Retrieves the size of the requested block.
-+ It also returns the number of additional blocks with the identical size.
-+ The GetBlockSize() function is used to retrieve the block map
-+ (see EFI_FIRMWARE_VOLUME_HEADER).
-+
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[in] Lba Indicates the block whose size to return
-+
-+ @param[out] BlockSize Pointer to a caller-allocated UINTN in which
-+ the size of the block is returned.
-+
-+ @param[out] NumberOfBlocks Pointer to a caller-allocated UINTN in
-+ which the number of consecutive blocks,
-+ starting with Lba, is returned. All
-+ blocks in this range have a size of
-+ BlockSize.
-+
-+ @retval EFI_SUCCESS The firmware volume base address was returned.
-+
-+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbGetBlockSize (
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ IN EFI_LBA Lba,
-+ OUT UINTN *BlockSize,
-+ OUT UINTN *NumberOfBlocks
-+ )
-+{
-+ EFI_STATUS Status;
-+ NOR_FLASH_INSTANCE *Instance;
-+
-+ Instance = INSTANCE_FROM_FVB_THIS (This);
-+
-+ DEBUG ((DEBUG_INFO,
-+ "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n", Lba,
-+ Instance->BlockSize, Instance->LastBlock));
-+
-+ if (Lba > Instance->LastBlock) {
-+ DEBUG ((DEBUG_ERROR,
-+ "FvbGetBlockSize: ERROR - Parameter LBA %ld is beyond the last Lba (%ld).\n",
-+ Lba, Instance->LastBlock));
-+ Status = EFI_INVALID_PARAMETER;
-+ } else {
-+ // This is easy because in this platform each NorFlash device has equal sized blocks.
-+ *BlockSize = (UINTN) Instance->BlockSize;
-+ *NumberOfBlocks = (UINTN) (Instance->LastBlock - Lba + 1);
-+
-+ DEBUG ((DEBUG_INFO,
-+ "FvbGetBlockSize: *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n", *BlockSize,
-+ *NumberOfBlocks));
-+
-+ Status = EFI_SUCCESS;
-+ }
-+
-+ return Status;
-+}
-+
-+/**
-+ Reads the specified number of bytes into a buffer from the specified block.
-+
-+ The Read() function reads the requested number of bytes from the
-+ requested block and stores them in the provided buffer.
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[in] Lba The starting logical block index from which to read
-+
-+ @param[in] Offset Offset into the block at which to begin reading.
-+
-+ @param[in, out] NumBytes Pointer to a UINTN.
-+ At entry, *NumBytes contains the total size of the
-+ buffer. *NumBytes should have a non zero value.
-+ At exit, *NumBytes contains the total number of
-+ bytes read.
-+
-+ @param[in, out] Buffer Pointer to a caller-allocated buffer that will be
-+ used to hold the data that is read.
-+
-+ @retval EFI_SUCCESS The firmware volume was read successfully, and
-+ contents are in Buffer.
-+
-+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
-+
-+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and
-+ could not be read.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbRead (
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ IN EFI_LBA Lba,
-+ IN UINTN Offset,
-+ IN OUT UINTN *NumBytes,
-+ IN OUT UINT8 *Buffer
-+ )
-+{
-+ EFI_STATUS Status;
-+ UINTN BlockSize;
-+ NOR_FLASH_INSTANCE *Instance;
-+
-+ Instance = INSTANCE_FROM_FVB_THIS (This);
-+
-+ DEBUG ((DEBUG_INFO,
-+ "FvbRead(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n",
-+ Instance->StartLba + Lba, Offset, *NumBytes, Buffer));
-+
-+ if (!Instance->Initialized && Instance->Initialize) {
-+ Instance->Initialize(Instance);
-+ }
-+
-+ BlockSize = Instance->BlockSize;
-+
-+ DEBUG ((DEBUG_INFO,
-+ "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= BlockSize=0x%x\n",
-+ Offset, *NumBytes, BlockSize ));
-+
-+ // The read must not span block boundaries.
-+ // We need to check each variable individually because adding two large
-+ // values together overflows.
-+ if (Offset >= BlockSize ||
-+ *NumBytes > BlockSize ||
-+ (Offset + *NumBytes) > BlockSize) {
-+ DEBUG ((DEBUG_ERROR,
-+ "FvbRead: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
-+ Offset, *NumBytes, BlockSize ));
-+ return EFI_BAD_BUFFER_SIZE;
-+ }
-+
-+ // We must have some bytes to read
-+ if (*NumBytes == 0) {
-+ return EFI_BAD_BUFFER_SIZE;
-+ }
-+
-+ // Decide if we are doing full block reads or not.
-+ if (*NumBytes % BlockSize != 0) {
-+ Status = NorFlashRead (Instance, Instance->StartLba + Lba, Offset,
-+ *NumBytes, Buffer);
-+ } else {
-+ // Read NOR Flash data into shadow buffer
-+ Status = NorFlashReadBlocks (Instance, Instance->StartLba + Lba,
-+ BlockSize, Buffer);
-+ }
-+ if (EFI_ERROR (Status)) {
-+ // Return one of the pre-approved error statuses
-+ return EFI_DEVICE_ERROR;
-+ }
-+ return EFI_SUCCESS;
-+}
-+
-+/**
-+ Writes the specified number of bytes from the input buffer to the block.
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-+
-+ @param[in] Lba The starting logical block index to write to.
-+
-+ @param[in] Offset Offset into the block at which to begin writing.
-+
-+ @param[in, out] NumBytes The pointer to a UINTN.
-+ At entry, *NumBytes contains the total size of the
-+ buffer.
-+ At exit, *NumBytes contains the total number of
-+ bytes actually written.
-+
-+ @param[in] Buffer The pointer to a caller-allocated buffer that
-+ contains the source for the write.
-+
-+ @retval EFI_SUCCESS The firmware volume was written successfully.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbWrite (
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ IN EFI_LBA Lba,
-+ IN UINTN Offset,
-+ IN OUT UINTN *NumBytes,
-+ IN UINT8 *Buffer
-+ )
-+{
-+ NOR_FLASH_INSTANCE *Instance;
-+
-+ Instance = INSTANCE_FROM_FVB_THIS (This);
-+
-+ return NorFlashWriteSingleBlock (Instance, Instance->StartLba + Lba, Offset,
-+ NumBytes, Buffer);
-+}
-+
-+/**
-+ Erases and initialises a firmware volume block.
-+
-+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
-+
-+ @param[in] ... The variable argument list is a list of tuples.
-+ Each tuple describes a range of LBAs to erase
-+ and consists of the following:
-+ - An EFI_LBA that indicates the starting LBA
-+ - A UINTN that indicates the number of blocks
-+ to erase.
-+
-+ The list is terminated with an
-+ EFI_LBA_LIST_TERMINATOR.
-+
-+ @retval EFI_SUCCESS The erase request successfully completed.
-+
-+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
-+ state.
-+
-+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly
-+ and could not be written.
-+ The firmware device may have been partially
-+ erased.
-+
-+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable
-+ argument list do not exist in the firmware
-+ volume.
-+
-+**/
-+EFI_STATUS
-+EFIAPI
-+FvbEraseBlocks (
-+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-+ ...
-+ )
-+{
-+ EFI_STATUS Status;
-+ VA_LIST Args;
-+ UINTN BlockAddress; // Physical address of Lba to erase
-+ EFI_LBA StartingLba; // Lba from which we start erasing
-+ UINTN NumOfLba; // Number of Lba blocks to erase
-+ NOR_FLASH_INSTANCE *Instance;
-+
-+ Instance = INSTANCE_FROM_FVB_THIS (This);
-+
-+ DEBUG ((DEBUG_INFO, "FvbEraseBlocks()\n"));
-+
-+ Status = EFI_SUCCESS;
-+
-+ // Before erasing, check the entire list of parameters to ensure
-+ // all specified blocks are valid
-+
-+ VA_START (Args, This);
-+ do {
-+ // Get the Lba from which we start erasing
-+ StartingLba = VA_ARG (Args, EFI_LBA);
-+
-+ // Have we reached the end of the list?
-+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
-+ break;
-+ }
-+
-+ // How many Lba blocks are we requested to erase?
-+ NumOfLba = VA_ARG (Args, UINT32);
-+
-+ // All blocks must be within range
-+ DEBUG ((DEBUG_INFO,
-+ "FvbEraseBlocks: Check if: ( StartingLba=%ld + NumOfLba=%d - 1 ) > LastBlock=%ld.\n",
-+ Instance->StartLba + StartingLba, NumOfLba, Instance->LastBlock));
-+ if (NumOfLba == 0 ||
-+ (Instance->StartLba + StartingLba + NumOfLba - 1) >
-+ Instance->LastBlock) {
-+ VA_END (Args);
-+ DEBUG ((DEBUG_ERROR,
-+ "FvbEraseBlocks: ERROR - Lba range goes past the last Lba.\n"));
-+ return EFI_INVALID_PARAMETER;
-+ }
-+ } while (TRUE);
-+ VA_END (Args);
-+
-+ VA_START (Args, This);
-+ do {
-+ // Get the Lba from which we start erasing
-+ StartingLba = VA_ARG (Args, EFI_LBA);
-+
-+ // Have we reached the end of the list?
-+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
-+ // Exit the while loop
-+ break;
-+ }
-+
-+ // How many Lba blocks are we requested to erase?
-+ NumOfLba = VA_ARG (Args, UINT32);
-+
-+ // Go through each one and erase it
-+ while (NumOfLba > 0) {
-+
-+ // Get the physical address of Lba to erase
-+ BlockAddress = GET_NOR_BLOCK_ADDRESS (
-+ Instance->RegionBaseAddress,
-+ Instance->StartLba + StartingLba,
-+ Instance->BlockSize
-+ );
-+
-+ // Erase it
-+ DEBUG ((DEBUG_INFO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n",
-+ Instance->StartLba + StartingLba, BlockAddress));
-+ Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
-+ if (EFI_ERROR(Status)) {
-+ VA_END (Args);
-+ return EFI_DEVICE_ERROR;
-+ }
-+
-+ // Move to the next Lba
-+ StartingLba++;
-+ NumOfLba--;
-+ }
-+ } while (TRUE);
-+ VA_END (Args);
-+
-+ return Status;
-+
-+}
-diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
-index 16937197..986a078f 100644
---- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
-+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
-@@ -1,7 +1,7 @@
- ## @file
- # Describes the N1Sdp configuration.
- #
--# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
-+# Copyright (c) 2021-2022, ARM Limited. All rights reserved.<BR>
- #
- # SPDX-License-Identifier: BSD-2-Clause-Patent
- ##
-@@ -89,3 +89,6 @@
- # unmapped reserved region results in a DECERR response.
- #
- gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049
-+
-+ # Base address of Cadence QSPI controller configuration registers
-+ gArmN1SdpTokenSpaceGuid.PcdCadenceQspiDxeRegBaseAddress|0x1C0C0000|UINT32|0x0000004A
deleted file mode 100644
@@ -1,88 +0,0 @@
-From e79fd5cfa3190eb27a9637facc9891cab55b5e09 Mon Sep 17 00:00:00 2001
-From: sahil <sahil@arm.com>
-Date: Mon, 2 May 2022 19:24:47 +0530
-Subject: [PATCH] Platform/ARM/N1Sdp: Persistent storage for N1Sdp
-
-Enable persistent storage on QSPI flash device.
-
-Upstream-Status: Pending
-Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
-Signed-off-by: sahil <sahil@arm.com>
-Change-Id: I403113bb885d1d411d433a7f266715d007509a5e
----
- Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 18 +++++++++++++-----
- Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 4 +++-
- 2 files changed, 16 insertions(+), 6 deletions(-)
-
-diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
-index 676ab677..80bc875a 100644
---- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
-+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
-@@ -44,6 +44,9 @@
- # file explorer library support
- FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
-
-+ # NOR flash support
-+ NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf
-+
- [LibraryClasses.common.SEC]
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
-@@ -161,11 +164,9 @@
- # ACPI Table Version
- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
-
-- # Runtime Variable storage
-- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
-- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
-- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
-- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
-+ # NOR flash support
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x18F00000
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00020000
-
- ################################################################################
- #
-@@ -197,6 +198,12 @@
- gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
- }
-
-+ # NOR flash support
-+ Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf {
-+ <LibraryClasses>
-+ NorFlashPlatformLib|Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf
-+ }
-+
- # Architectural Protocols
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
-@@ -217,6 +224,7 @@
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
- <LibraryClasses>
- NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
-+ NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
- }
-
-diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
-index e5e24ea5..4329f892 100644
---- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
-+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
-@@ -1,7 +1,7 @@
- ## @file
- # FDF file of N1Sdp
- #
--# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
-+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
- #
- # SPDX-License-Identifier: BSD-2-Clause-Patent
- ##
-@@ -140,6 +140,8 @@ READ_LOCK_STATUS = TRUE
- INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-
-+ INF Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
-+
- INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
-
deleted file mode 100644
@@ -1,50 +0,0 @@
-From 5e8fbb3ba0f634f7fc873c6577269845f9e243db Mon Sep 17 00:00:00 2001
-From: sahil <sahil@arm.com>
-Date: Mon, 2 May 2022 19:28:19 +0530
-Subject: [PATCH] Platform/ARM/N1Sdp: Enable FaultTolerantWrite Dxe driver for
- N1Sdp
-
-Upstream-Status: Pending
-Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
-Signed-off-by: sahil <sahil@arm.com>
-Change-Id: If448ad95b2e72cef31ce1e1e5ab2504d607f0545
----
- Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +++++
- Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 1 +
- 2 files changed, 6 insertions(+)
-
-diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
-index 80bc875a..90a0d5b6 100644
---- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
-+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
-@@ -165,6 +165,10 @@
- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
-
- # NOR flash support
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x18F40000
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00020000
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x18F20000
-+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00020000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x18F00000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00020000
-
-@@ -227,6 +231,7 @@
- NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
- }
-+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
-
- # ACPI Support
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
-diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
-index 4329f892..17d370a3 100644
---- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
-+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
-@@ -90,6 +90,7 @@ READ_LOCK_STATUS = TRUE
- INF MdeModulePkg/Universal/Metronome/Metronome.inf
- INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
deleted file mode 100644
@@ -1,197 +0,0 @@
-From 6d274379f584a638c1f2b4b8a19014d4baef1d9f Mon Sep 17 00:00:00 2001
-From: sahil <sahil@arm.com>
-Date: Thu, 11 Aug 2022 11:26:29 +0530
-Subject: [PATCH] Platform/ARM/N1Sdp: manually poll QSPI status bit after
- erase/write
-
-This patch adds a function to poll Nor flash memory's status register
-bit (WIP bit) to wait for an erase/write operation to complete.
-The polling timeout is set to 1 second.
-
-Upstream-Status: Pending
-Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
-Signed-off-by: sahil <sahil@arm.com>
-Change-Id: Ie678b7586671964ae0f8506a0542d73cbddddfe4
----
- .../Drivers/CadenceQspiDxe/CadenceQspiDxe.inf | 1 +
- .../Drivers/CadenceQspiDxe/CadenceQspiReg.h | 6 +-
- .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c | 80 ++++++++++++++++++-
- .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h | 5 ++
- 4 files changed, 88 insertions(+), 4 deletions(-)
-
-diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
-index 4f20c3ba..7a39eb2d 100644
---- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
-+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
-@@ -39,6 +39,7 @@
- MemoryAllocationLib
- NorFlashInfoLib
- NorFlashPlatformLib
-+ TimerLib
- UefiBootServicesTableLib
- UefiDriverEntryPoint
- UefiLib
-diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
-index fe3b327c..1971631d 100644
---- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
-+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
-@@ -16,13 +16,15 @@
- #define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS 19
- #define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS 16
- #define CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT 0x02
--#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_4B 0x03
--#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B 0x02
- #define CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS 24
- #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE 0x01
- #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_BYTE_3B 0x02
- #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS 23
- #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS 20
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_8C 0x8
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_BIT_POS 7
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(x) ((x - 1) << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS)
-+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES(x) ((x - 1) << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS)
-
- #define CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET 0xA0
-
-diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
-index 188c75e2..6832351a 100644
---- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
-+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
-@@ -10,6 +10,7 @@
- #include <Library/MemoryAllocationLib.h>
- #include <Library/NorFlashInfoLib.h>
- #include <Library/PcdLib.h>
-+#include <Library/TimerLib.h>
- #include <Library/UefiBootServicesTableLib.h>
- #include <Library/UefiLib.h>
-
-@@ -184,6 +185,74 @@ FreeInstance:
- return Status;
- }
-
-+/**
-+ Converts milliseconds into number of ticks of the performance counter.
-+
-+ @param[in] Milliseconds Milliseconds to convert into ticks.
-+
-+ @retval Milliseconds expressed as number of ticks.
-+
-+**/
-+STATIC
-+UINT64
-+MilliSecondsToTicks (
-+ IN UINTN Milliseconds
-+ )
-+{
-+ CONST UINT64 NanoSecondsPerTick = GetTimeInNanoSecond (1);
-+
-+ return (Milliseconds * 1000000) / NanoSecondsPerTick;
-+}
-+
-+/**
-+ Poll Status register for NOR flash erase/write completion.
-+
-+ @param[in] Instance NOR flash Instance.
-+
-+ @retval EFI_SUCCESS Request is executed successfully.
-+ @retval EFI_TIMEOUT Operation timed out.
-+ @retval EFI_DEVICE_ERROR Controller operartion failed.
-+
-+**/
-+STATIC
-+EFI_STATUS
-+NorFlashPollStatusRegister (
-+ IN NOR_FLASH_INSTANCE *Instance
-+ )
-+{
-+ BOOLEAN SRegDone;
-+ UINT32 val;
-+
-+ val = SPINOR_OP_RDSR << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
-+ CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS |
-+ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(1) |
-+ CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_8C << CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_BIT_POS;
-+
-+ CONST UINT64 TickOut =
-+ GetPerformanceCounter () + MilliSecondsToTicks (SPINOR_SR_WIP_POLL_TIMEOUT_MS);
-+
-+ do {
-+ if (GetPerformanceCounter () > TickOut) {
-+ DEBUG ((
-+ DEBUG_ERROR,
-+ "NorFlashPollStatusRegister: Timeout waiting for erase/write.\n"
-+ ));
-+ return EFI_TIMEOUT;
-+ }
-+
-+ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) {
-+ return EFI_DEVICE_ERROR;
-+ }
-+
-+ SRegDone =
-+ (MmioRead8 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET)
-+ & SPINOR_SR_WIP) == 0;
-+
-+ } while (!SRegDone);
-+
-+ return EFI_SUCCESS;
-+}
-+
- /**
- Check whether NOR flash opertions are Locked.
-
-@@ -305,12 +374,16 @@ NorFlashEraseSingleBlock (
-
- DevConfigVal = SPINOR_OP_BE_4K << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
- CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS |
-- CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS;
-+ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES(3);
-
- if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, DevConfigVal))) {
- return EFI_DEVICE_ERROR;
- }
-
-+ if (EFI_ERROR (NorFlashPollStatusRegister (Instance))) {
-+ return EFI_DEVICE_ERROR;
-+ }
-+
- return EFI_SUCCESS;
- }
-
-@@ -383,6 +456,9 @@ NorFlashWriteSingleWord (
- return EFI_DEVICE_ERROR;
- }
- MmioWrite32 (WordAddress, WriteData);
-+ if (EFI_ERROR (NorFlashPollStatusRegister (Instance))) {
-+ return EFI_DEVICE_ERROR;
-+ }
- return EFI_SUCCESS;
- }
-
-@@ -907,7 +983,7 @@ NorFlashReadID (
-
- val = SPINOR_OP_RDID << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
- CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS |
-- CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS;
-+ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(3);
-
- if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) {
- return EFI_DEVICE_ERROR;
-diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
-index e720937e..eb0afc60 100644
---- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
-+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
-@@ -477,8 +477,13 @@ NorFlashReadID (
- OUT UINT8 JedecId[3]
- );
-
-+#define SPINOR_SR_WIP BIT0 // Write in progress
-+
- #define SPINOR_OP_WREN 0x06 // Write enable
- #define SPINOR_OP_BE_4K 0x20 // Erase 4KiB block
- #define SPINOR_OP_RDID 0x9f // Read JEDEC ID
-+#define SPINOR_OP_RDSR 0x05 // Read status register
-+
-+#define SPINOR_SR_WIP_POLL_TIMEOUT_MS 1000u // Status Register read timeout
-
- #endif /* NOR_FLASH_DXE_H_ */
deleted file mode 100644
@@ -1,72 +0,0 @@
-From 60dfd5bb8f25fa5f0b6c07c3098836bec1668c19 Mon Sep 17 00:00:00 2001
-From: Mariam Elshakfy <mariam.elshakfy@arm.com>
-Date: Thu, 14 Mar 2024 14:47:27 +0000
-Subject: [PATCH] Platform/ARM/N1Sdp: Reserve OP-TEE Region from UEFI
-
-To enable cache on N1SDP, OP-TEE has to be moved
-to run from DDR4 memory. Since this memory is
-known to application side, it must be reserved
-
-Upstream-Status: Inappropriate [will not be submitted as it's a workaround to address hardware issue]
-Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
----
- .../Library/PlatformLib/PlatformLib.inf | 3 +++
- .../Library/PlatformLib/PlatformLibMem.c | 13 +++++++++++++
- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 4 ++++
- 3 files changed, 20 insertions(+)
-
-diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
-index 78f309c3aa..dc82d5bd87 100644
---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
-+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
-@@ -62,6 +62,9 @@
-
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
-
-+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemoryBase
-+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemorySize
-+
- [Guids]
- gArmNeoverseN1SocPlatformInfoDescriptorGuid
- gEfiHobListGuid ## CONSUMES ## SystemTable
-diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
-index 8bb9407490..d8ad0f975c 100644
---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
-+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
-@@ -150,6 +150,19 @@ ArmPlatformGetVirtualMemoryMap (
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED;
-
-+ // Reserved OP-TEE region
-+ BuildResourceDescriptorHob (
-+ EFI_RESOURCE_SYSTEM_MEMORY,
-+ ResourceAttributes,
-+ PcdGet64 (PcdOpteeMemoryBase),
-+ PcdGet64 (PcdOpteeMemorySize)
-+ );
-+ BuildMemoryAllocationHob (
-+ PcdGet64 (PcdOpteeMemoryBase),
-+ PcdGet64 (PcdOpteeMemorySize),
-+ EfiReservedMemoryType
-+ );
-+
- BuildResourceDescriptorHob (
- EFI_RESOURCE_SYSTEM_MEMORY,
- ResourceAttributes,
-diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
-index 9e257ebde0..587319262a 100644
---- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
-+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
-@@ -86,5 +86,9 @@
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
-
-+ # Base Address of OP-TEE
-+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemoryBase|0xDE000000|UINT64|0x00000052
-+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemorySize|0x02000000|UINT64|0x00000053
-+
- [Ppis]
- gNtFwConfigDtInfoPpiGuid = { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } }
-2.38.1
-
deleted file mode 100644
@@ -1,6 +0,0 @@
-define KMACHINE n1sdp
-define KTYPE preempt-rt
-define KARCH arm64
-
-include ktypes/preempt-rt/preempt-rt.scc
-include n1sdp/disable-kvm.cfg
deleted file mode 100644
@@ -1,5 +0,0 @@
-define KMACHINE n1sdp
-define KTYPE standard
-define KARCH arm64
-
-include ktypes/standard/standard.scc
deleted file mode 100644
@@ -1 +0,0 @@
-# CONFIG_KVM is not set
@@ -15,7 +15,6 @@ ARMBSPFILESPATHS := "${THISDIR}:${THISDIR}/files:"
SRC_URI_KMETA = "file://arm-platforms-kmeta;type=kmeta;name=arm-platforms-kmeta;destsuffix=arm-platforms-kmeta"
SRC_URI:append:fvp-base = " ${SRC_URI_KMETA}"
SRC_URI:append:juno = " ${SRC_URI_KMETA}"
-SRC_URI:append:n1sdp = " ${SRC_URI_KMETA}"
#
# Corstone1000 KMACHINE
@@ -76,30 +75,6 @@ FILESEXTRAPATHS:prepend:juno := "${ARMBSPFILESPATHS}"
COMPATIBLE_MACHINE:musca-b1 = "(^$)"
COMPATIBLE_MACHINE:musca-s1 = "(^$)"
-#
-# N1SDP KMACHINE
-#
-FILESEXTRAPATHS:prepend:n1sdp := "${THISDIR}/linux-yocto-6.6/n1sdp:"
-COMPATIBLE_MACHINE:n1sdp = "n1sdp"
-KBUILD_DEFCONFIG:n1sdp = "defconfig"
-KCONFIG_MODE:n1sdp = "--alldefconfig"
-FILESEXTRAPATHS:prepend:n1sdp := "${ARMBSPFILESPATHS}"
-SRC_URI:append:n1sdp = " \
- file://0001-iommu-arm-smmu-v3-workaround-for-ATC_INV_SIZE_ALL-in.patch \
- file://0002-n1sdp-pci_quirk-add-acs-override-for-PCI-devices.patch \
- file://0003-pcie-Add-quirk-for-the-Arm-Neoverse-N1SDP-platform.patch \
- file://0004-n1sdp-pcie-add-quirk-support-enabling-remote-chip-PC.patch \
- file://0005-arm64-kpti-Whitelist-early-Arm-Neoverse-N1-revisions.patch \
- file://0006-arm64-defconfig-disable-config-options-that-does-not.patch \
- file://enable-nvme.cfg \
- file://enable-realtek-R8169.cfg \
- file://enable-usb_conn_gpio.cfg \
- file://usb_xhci_pci_renesas.cfg \
- "
-# Since we use the intree defconfig and the preempt-rt turns off some configs
-# do_kernel_configcheck will display warnings. So, lets disable it.
-KCONF_AUDIT_LEVEL:n1sdp:pn-linux-yocto-rt = "0"
-
#
# SGI575 KMACHINE
#
deleted file mode 100644
@@ -1,47 +0,0 @@
-From 32ae4539865e64bcfb0c6955bdac8db5904e493d Mon Sep 17 00:00:00 2001
-From: Manoj Kumar <manoj.kumar3@arm.com>
-Date: Mon, 1 Feb 2021 21:36:43 +0530
-Subject: [PATCH] iommu/arm-smmu-v3: workaround for ATC_INV_SIZE_ALL in N1SDP
-
-ATC_INV_SIZE_ALL request should automatically translate to ATS
-address which is not happening in SMMUv3 version gone into
-N1SDP platform. This workaround manually sets the ATS address
-field to proper value for ATC_INV_SIZE_ALL command.
-
-Change-Id: If89465be94720a62be85e1e6612f17e93fa9b8a5
-Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
-Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
-
-Upstream-Status: Inappropriate [Workaround]
-Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-Signed-off-by: Adam Johnston <adam.johnston@arm.com>
----
- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 +
- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 +
- 2 files changed, 2 insertions(+)
-
-diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
-index d4d8bfee9feb..0524bf2ec021 100644
---- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
-+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
-@@ -1738,6 +1738,7 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,
- };
-
- if (!size) {
-+ cmd->atc.addr = ATC_INV_ADDR_ALL;
- cmd->atc.size = ATC_INV_SIZE_ALL;
- return;
- }
-diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
-index cd48590ada30..20892b2bfe1d 100644
---- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
-+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
-@@ -472,6 +472,7 @@ struct arm_smmu_cmdq_ent {
-
- #define CMDQ_OP_ATC_INV 0x40
- #define ATC_INV_SIZE_ALL 52
-+ #define ATC_INV_ADDR_ALL 0x7FFFFFFFFFFFF000UL
- struct {
- u32 sid;
- u32 ssid;
deleted file mode 100644
@@ -1,159 +0,0 @@
-From fc8605e74b51d9e0ab8efd0489eca2e11d807f07 Mon Sep 17 00:00:00 2001
-From: Manoj Kumar <manoj.kumar3@arm.com>
-Date: Tue, 31 Aug 2021 16:15:38 +0000
-Subject: [PATCH] n1sdp: pci_quirk: add acs override for PCI devices
-
-Patch taken from:
-https://gitlab.com/Queuecumber/linux-acs-override/raw/master/workspaces/5.4/acso.patch
-
-Change-Id: Ib926bf50524ce9990fbaa2f2f8670fe84bd571f9
-Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
-
-Upstream-Status: Inappropriate [will not be submitted as its a workaround to address hardware issue]
-Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-Signed-off-by: Adam Johnston <adam.johnston@arm.com>
----
- .../admin-guide/kernel-parameters.txt | 8 ++
- drivers/pci/quirks.c | 102 ++++++++++++++++++
- 2 files changed, 110 insertions(+)
-
-diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
-index 963cdaecabcb..8e94af513b9f 100644
---- a/Documentation/admin-guide/kernel-parameters.txt
-+++ b/Documentation/admin-guide/kernel-parameters.txt
-@@ -4162,6 +4162,14 @@
- nomsi [MSI] If the PCI_MSI kernel config parameter is
- enabled, this kernel boot option can be used to
- disable the use of MSI interrupts system-wide.
-+ pcie_acs_override [PCIE] Override missing PCIe ACS support for
-+ downstream
-+ All downstream ports - full ACS capabilities
-+ multfunction
-+ All multifunction devices - multifunction ACS subset
-+ id:nnnn:nnnn
-+ Specfic device - full ACS capabilities
-+ Specified as vid:did (vendor/device ID) in hex
- noioapicquirk [APIC] Disable all boot interrupt quirks.
- Safety option to keep boot IRQs enabled. This
- should never be necessary.
-diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
-index 285acc4aaccc..d6ebef1f30db 100644
---- a/drivers/pci/quirks.c
-+++ b/drivers/pci/quirks.c
-@@ -3612,6 +3612,107 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
- dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
- }
-
-+static bool acs_on_downstream;
-+static bool acs_on_multifunction;
-+
-+#define NUM_ACS_IDS 16
-+struct acs_on_id {
-+ unsigned short vendor;
-+ unsigned short device;
-+};
-+static struct acs_on_id acs_on_ids[NUM_ACS_IDS];
-+static u8 max_acs_id;
-+
-+static __init int pcie_acs_override_setup(char *p)
-+{
-+ if (!p)
-+ return -EINVAL;
-+
-+ while (*p) {
-+ if (!strncmp(p, "downstream", 10))
-+ acs_on_downstream = true;
-+ if (!strncmp(p, "multifunction", 13))
-+ acs_on_multifunction = true;
-+ if (!strncmp(p, "id:", 3)) {
-+ char opt[5];
-+ int ret;
-+ long val;
-+
-+ if (max_acs_id >= NUM_ACS_IDS - 1) {
-+ pr_warn("Out of PCIe ACS override slots (%d)\n",
-+ NUM_ACS_IDS);
-+ goto next;
-+ }
-+
-+ p += 3;
-+ snprintf(opt, 5, "%s", p);
-+ ret = kstrtol(opt, 16, &val);
-+ if (ret) {
-+ pr_warn("PCIe ACS ID parse error %d\n", ret);
-+ goto next;
-+ }
-+ acs_on_ids[max_acs_id].vendor = val;
-+
-+ p += strcspn(p, ":");
-+ if (*p != ':') {
-+ pr_warn("PCIe ACS invalid ID\n");
-+ goto next;
-+ }
-+
-+ p++;
-+ snprintf(opt, 5, "%s", p);
-+ ret = kstrtol(opt, 16, &val);
-+ if (ret) {
-+ pr_warn("PCIe ACS ID parse error %d\n", ret);
-+ goto next;
-+ }
-+ acs_on_ids[max_acs_id].device = val;
-+ max_acs_id++;
-+ }
-+next:
-+ p += strcspn(p, ",");
-+ if (*p == ',')
-+ p++;
-+ }
-+
-+ if (acs_on_downstream || acs_on_multifunction || max_acs_id)
-+ pr_warn("Warning: PCIe ACS overrides enabled; This may allow non-IOMMU protected peer-to-peer DMA\n");
-+
-+ return 0;
-+}
-+early_param("pcie_acs_override", pcie_acs_override_setup);
-+
-+static int pcie_acs_overrides(struct pci_dev *dev, u16 acs_flags)
-+{
-+ int i;
-+
-+ /* Never override ACS for legacy devices or devices with ACS caps */
-+ if (!pci_is_pcie(dev) ||
-+ pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS))
-+ return -ENOTTY;
-+
-+ for (i = 0; i < max_acs_id; i++)
-+ if (acs_on_ids[i].vendor == dev->vendor &&
-+ acs_on_ids[i].device == dev->device)
-+ return 1;
-+
-+ switch (pci_pcie_type(dev)) {
-+ case PCI_EXP_TYPE_DOWNSTREAM:
-+ case PCI_EXP_TYPE_ROOT_PORT:
-+ if (acs_on_downstream)
-+ return 1;
-+ break;
-+ case PCI_EXP_TYPE_ENDPOINT:
-+ case PCI_EXP_TYPE_UPSTREAM:
-+ case PCI_EXP_TYPE_LEG_END:
-+ case PCI_EXP_TYPE_RC_END:
-+ if (acs_on_multifunction && dev->multifunction)
-+ return 1;
-+ }
-+
-+ return -ENOTTY;
-+}
-+
- /*
- * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
- * prevented for those affected devices.
-@@ -4980,6 +5081,7 @@ static const struct pci_dev_acs_enabled {
- { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
- /* Wangxun nics */
- { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
-+ { PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
- { 0 }
- };
-
deleted file mode 100644
@@ -1,324 +0,0 @@
-From 5aa5769af625c79589fd84b8afc06149c2362218 Mon Sep 17 00:00:00 2001
-From: Deepak Pandey <Deepak.Pandey@arm.com>
-Date: Fri, 31 May 2019 16:42:43 +0100
-Subject: [PATCH] pcie: Add quirk for the Arm Neoverse N1SDP platform
-
-The Arm N1SDP SoC suffers from some PCIe integration issues, most
-prominently config space accesses to not existing BDFs being answered
-with a bus abort, resulting in an SError.
-To mitigate this, the firmware scans the bus before boot (catching the
-SErrors) and creates a table with valid BDFs, which acts as a filter for
-Linux' config space accesses.
-
-Add code consulting the table as an ACPI PCIe quirk, also register the
-corresponding device tree based description of the host controller.
-Also fix the other two minor issues on the way, namely not being fully
-ECAM compliant and config space accesses being restricted to 32-bit
-accesses only.
-
-This allows the Arm Neoverse N1SDP board to boot Linux without crashing
-and to access *any* devices (there are no platform devices except UART).
-
-Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
-[Sudipto: extend to cover the CCIX root port as well]
-Signed-off-by: Sudipto Paul <sudipto.paul@arm.com>
-[Andre: fix coding style issues, rewrite some parts, add DT support]
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-
-Change-Id: I1d3a4b9bf6b3b883d262e3c4ff1f88a0eb81c1fe
-Upstream-Status: Inappropriate [will not be submitted as its a workaround to address hardware issue]
-Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-Signed-off-by: Adam Johnston <adam.johnston@arm.com>
----
- arch/arm64/configs/defconfig | 1 +
- drivers/acpi/pci_mcfg.c | 7 +
- drivers/pci/controller/Kconfig | 11 ++
- drivers/pci/controller/Makefile | 2 +-
- drivers/pci/controller/pcie-n1sdp.c | 198 ++++++++++++++++++++++++++++
- include/linux/pci-ecam.h | 2 +
- 6 files changed, 220 insertions(+), 1 deletion(-)
- create mode 100644 drivers/pci/controller/pcie-n1sdp.c
-
-diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
-index bbbc31391a65..973aa3b4d407 100644
---- a/arch/arm64/configs/defconfig
-+++ b/arch/arm64/configs/defconfig
-@@ -214,6 +214,7 @@ CONFIG_NFC_S3FWRN5_I2C=m
- CONFIG_PCI=y
- CONFIG_PCIEPORTBUS=y
- CONFIG_PCIEAER=y
-+CONFIG_PCI_QUIRKS=y
- CONFIG_PCI_IOV=y
- CONFIG_PCI_PASID=y
- CONFIG_HOTPLUG_PCI=y
-diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
-index 860014b89b8e..2d4c1c699ffe 100644
---- a/drivers/acpi/pci_mcfg.c
-+++ b/drivers/acpi/pci_mcfg.c
-@@ -171,6 +171,13 @@ static struct mcfg_fixup mcfg_quirks[] = {
- ALTRA_ECAM_QUIRK(1, 13),
- ALTRA_ECAM_QUIRK(1, 14),
- ALTRA_ECAM_QUIRK(1, 15),
-+
-+#define N1SDP_ECAM_MCFG(rev, seg, ops) \
-+ {"ARMLTD", "ARMN1SDP", rev, seg, MCFG_BUS_ANY, ops }
-+
-+ /* N1SDP SoC with v1 PCIe controller */
-+ N1SDP_ECAM_MCFG(0x20181101, 0, &pci_n1sdp_pcie_ecam_ops),
-+ N1SDP_ECAM_MCFG(0x20181101, 1, &pci_n1sdp_ccix_ecam_ops),
- #endif /* ARM64 */
-
- #ifdef CONFIG_LOONGARCH
-diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
-index bfd9bac37e24..7a65799dded7 100644
---- a/drivers/pci/controller/Kconfig
-+++ b/drivers/pci/controller/Kconfig
-@@ -50,6 +50,17 @@ config PCI_IXP4XX
- Say Y here if you want support for the PCI host controller found
- in the Intel IXP4xx XScale-based network processor SoC.
-
-+config PCIE_HOST_N1SDP_ECAM
-+ bool "ARM N1SDP PCIe Controller"
-+ depends on ARM64
-+ depends on OF || (ACPI && PCI_QUIRKS)
-+ select PCI_HOST_COMMON
-+ default y if ARCH_VEXPRESS
-+ help
-+ Say Y here if you want PCIe support for the Arm N1SDP platform.
-+ The controller is ECAM compliant, but needs a quirk to workaround
-+ an integration issue.
-+
- config PCI_TEGRA
- bool "NVIDIA Tegra PCIe controller"
- depends on ARCH_TEGRA || COMPILE_TEST
-diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
-index 37c8663de7fe..08e5afcf6e86 100644
---- a/drivers/pci/controller/Makefile
-+++ b/drivers/pci/controller/Makefile
-@@ -39,7 +39,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
- obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
- obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
- obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
--
-+obj-$(CONFIG_PCIE_HOST_N1SDP_ECAM) += pcie-n1sdp.o
- # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
- obj-y += dwc/
- obj-y += mobiveil/
-diff --git a/drivers/pci/controller/pcie-n1sdp.c b/drivers/pci/controller/pcie-n1sdp.c
-new file mode 100644
-index 000000000000..408699b9dcb1
---- /dev/null
-+++ b/drivers/pci/controller/pcie-n1sdp.c
-@@ -0,0 +1,198 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2018/2019 ARM Ltd.
-+ *
-+ * This quirk is to mask the following issues:
-+ * - PCIE SLVERR: config space accesses to invalid PCIe BDFs cause a bus
-+ * error (signalled as an asynchronous SError)
-+ * - MCFG BDF mapping: the root complex is mapped separately from the device
-+ * config space
-+ * - Non 32-bit accesses to config space are not supported.
-+ *
-+ * At boot time the SCP board firmware creates a discovery table with
-+ * the root complex' base address and the valid BDF values, discovered while
-+ * scanning the config space and catching the SErrors.
-+ * Linux responds only to the EPs listed in this table, returning NULL
-+ * for the rest.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/ioport.h>
-+#include <linux/sizes.h>
-+#include <linux/of_pci.h>
-+#include <linux/of.h>
-+#include <linux/pci-ecam.h>
-+#include <linux/platform_device.h>
-+#include <linux/module.h>
-+
-+#include "../pci.h"
-+
-+/* Platform specific values as hardcoded in the firmware. */
-+#define AP_NS_SHARED_MEM_BASE 0x06000000
-+#define MAX_SEGMENTS 2 /* Two PCIe root complexes. */
-+#define BDF_TABLE_SIZE SZ_16K
-+
-+/*
-+ * Shared memory layout as written by the SCP upon boot time:
-+ * ----
-+ * Discover data header --> RC base address
-+ * \-> BDF Count
-+ * Discover data --> BDF 0...n
-+ * ----
-+ */
-+struct pcie_discovery_data {
-+ u32 rc_base_addr;
-+ u32 nr_bdfs;
-+ u32 valid_bdfs[0];
-+} *pcie_discovery_data[MAX_SEGMENTS];
-+
-+void __iomem *rc_remapped_addr[MAX_SEGMENTS];
-+
-+/*
-+ * map_bus() is called before we do a config space access for a certain
-+ * device. We use this to check whether this device is valid, avoiding
-+ * config space accesses which would result in an SError otherwise.
-+ */
-+static void __iomem *pci_n1sdp_map_bus(struct pci_bus *bus, unsigned int devfn,
-+ int where)
-+{
-+ struct pci_config_window *cfg = bus->sysdata;
-+ unsigned int devfn_shift = cfg->ops->bus_shift - 8;
-+ unsigned int busn = bus->number;
-+ unsigned int segment = bus->domain_nr;
-+ unsigned int bdf_addr;
-+ unsigned int table_count, i;
-+ struct pci_dev *dev;
-+
-+ if (segment >= MAX_SEGMENTS ||
-+ busn < cfg->busr.start || busn > cfg->busr.end)
-+ return NULL;
-+
-+ /* The PCIe root complex has a separate config space mapping. */
-+ if (busn == 0 && devfn == 0)
-+ return rc_remapped_addr[segment] + where;
-+
-+ dev = pci_get_domain_bus_and_slot(segment, busn, devfn);
-+ if (dev && dev->is_virtfn)
-+ return pci_ecam_map_bus(bus, devfn, where);
-+
-+ /* Accesses beyond the vendor ID always go to existing devices. */
-+ if (where > 0)
-+ return pci_ecam_map_bus(bus, devfn, where);
-+
-+ busn -= cfg->busr.start;
-+ bdf_addr = (busn << cfg->ops->bus_shift) + (devfn << devfn_shift);
-+ table_count = pcie_discovery_data[segment]->nr_bdfs;
-+ for (i = 0; i < table_count; i++) {
-+ if (bdf_addr == pcie_discovery_data[segment]->valid_bdfs[i])
-+ return pci_ecam_map_bus(bus, devfn, where);
-+ }
-+
-+ return NULL;
-+}
-+
-+static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
-+{
-+ phys_addr_t table_base;
-+ struct device *dev = cfg->parent;
-+ struct pcie_discovery_data *shared_data;
-+ size_t bdfs_size;
-+
-+ if (segment >= MAX_SEGMENTS)
-+ return -ENODEV;
-+
-+ table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
-+
-+ if (!request_mem_region(table_base, BDF_TABLE_SIZE,
-+ "PCIe valid BDFs")) {
-+ dev_err(dev, "PCIe BDF shared region request failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ shared_data = devm_ioremap(dev,
-+ table_base, BDF_TABLE_SIZE);
-+ if (!shared_data)
-+ return -ENOMEM;
-+
-+ /* Copy the valid BDFs structure to allocated normal memory. */
-+ bdfs_size = sizeof(struct pcie_discovery_data) +
-+ sizeof(u32) * shared_data->nr_bdfs;
-+ pcie_discovery_data[segment] = devm_kmalloc(dev, bdfs_size, GFP_KERNEL);
-+ if (!pcie_discovery_data[segment])
-+ return -ENOMEM;
-+
-+ memcpy_fromio(pcie_discovery_data[segment], shared_data, bdfs_size);
-+
-+ rc_remapped_addr[segment] = devm_ioremap(dev,
-+ shared_data->rc_base_addr,
-+ PCI_CFG_SPACE_EXP_SIZE);
-+ if (!rc_remapped_addr[segment]) {
-+ dev_err(dev, "Cannot remap root port base\n");
-+ return -ENOMEM;
-+ }
-+
-+ devm_iounmap(dev, shared_data);
-+
-+ return 0;
-+}
-+
-+/* Called for ACPI segment 0, and for all segments when using DT. */
-+static int pci_n1sdp_pcie_init(struct pci_config_window *cfg)
-+{
-+ struct platform_device *pdev = to_platform_device(cfg->parent);
-+ int segment = 0;
-+
-+ if (pdev->dev.of_node)
-+ segment = of_get_pci_domain_nr(pdev->dev.of_node);
-+ if (segment < 0 || segment > MAX_SEGMENTS) {
-+ dev_err(&pdev->dev, "N1SDP PCI controllers require linux,pci-domain property\n");
-+ dev_err(&pdev->dev, "Or invalid segment number, must be smaller than %d\n",
-+ MAX_SEGMENTS);
-+ return -EINVAL;
-+ }
-+
-+ return pci_n1sdp_init(cfg, segment);
-+}
-+
-+/* Called for ACPI segment 1. */
-+static int pci_n1sdp_ccix_init(struct pci_config_window *cfg)
-+{
-+ return pci_n1sdp_init(cfg, 1);
-+}
-+
-+const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops = {
-+ .bus_shift = 20,
-+ .init = pci_n1sdp_pcie_init,
-+ .pci_ops = {
-+ .map_bus = pci_n1sdp_map_bus,
-+ .read = pci_generic_config_read32,
-+ .write = pci_generic_config_write32,
-+ }
-+};
-+
-+const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops = {
-+ .bus_shift = 20,
-+ .init = pci_n1sdp_ccix_init,
-+ .pci_ops = {
-+ .map_bus = pci_n1sdp_map_bus,
-+ .read = pci_generic_config_read32,
-+ .write = pci_generic_config_write32,
-+ }
-+};
-+
-+static const struct of_device_id n1sdp_pcie_of_match[] = {
-+ { .compatible = "arm,n1sdp-pcie", .data = &pci_n1sdp_pcie_ecam_ops },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, n1sdp_pcie_of_match);
-+
-+static struct platform_driver n1sdp_pcie_driver = {
-+ .driver = {
-+ .name = KBUILD_MODNAME,
-+ .of_match_table = n1sdp_pcie_of_match,
-+ .suppress_bind_attrs = true,
-+ },
-+ .probe = pci_host_common_probe,
-+};
-+builtin_platform_driver(n1sdp_pcie_driver);
-diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
-index 6b1301e2498e..b3cf3adeab28 100644
---- a/include/linux/pci-ecam.h
-+++ b/include/linux/pci-ecam.h
-@@ -88,6 +88,8 @@ extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x
- extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
- extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
- extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
-+extern const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops; /* Arm N1SDP PCIe */
-+extern const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops; /* Arm N1SDP PCIe */
- #endif
-
- #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
deleted file mode 100644
@@ -1,136 +0,0 @@
-From b59e0d6c6035db80fc9044df0333f96ede53ad7a Mon Sep 17 00:00:00 2001
-From: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
-Date: Wed, 9 Feb 2022 20:37:43 +0530
-Subject: [PATCH] n1sdp: pcie: add quirk support enabling remote chip PCIe
-
-Base address mapping for remote chip Root PCIe ECAM space.
-
-When two N1SDP boards are coupled via the CCIX connection, the PCI host
-complex of the remote board appears as PCIe segment 2 on the primary board.
-The resources of the secondary board, including the host complex, are
-mapped at offset 0x40000000000 into the address space of the primary
-board, so take that into account when accessing the remote PCIe segment.
-
-Change-Id: I0e8d1eb119aef6444b9df854a39b24441c12195a
-Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
-Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: sahil <sahil@arm.com>
-
-Upstream-Status: Inappropriate [will not be submitted as its an hack required to fix the hardware issue]
-Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-Signed-off-by: Adam Johnston <adam.johnston@arm.com>
----
- drivers/acpi/pci_mcfg.c | 1 +
- drivers/pci/controller/pcie-n1sdp.c | 32 +++++++++++++++++++++++++----
- include/linux/pci-ecam.h | 1 +
- 3 files changed, 30 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
-index 2d4c1c699ffe..27f1e9a45c17 100644
---- a/drivers/acpi/pci_mcfg.c
-+++ b/drivers/acpi/pci_mcfg.c
-@@ -178,6 +178,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
- /* N1SDP SoC with v1 PCIe controller */
- N1SDP_ECAM_MCFG(0x20181101, 0, &pci_n1sdp_pcie_ecam_ops),
- N1SDP_ECAM_MCFG(0x20181101, 1, &pci_n1sdp_ccix_ecam_ops),
-+ N1SDP_ECAM_MCFG(0x20181101, 2, &pci_n1sdp_remote_pcie_ecam_ops),
- #endif /* ARM64 */
-
- #ifdef CONFIG_LOONGARCH
-diff --git a/drivers/pci/controller/pcie-n1sdp.c b/drivers/pci/controller/pcie-n1sdp.c
-index 408699b9dcb1..b3b02417fd7d 100644
---- a/drivers/pci/controller/pcie-n1sdp.c
-+++ b/drivers/pci/controller/pcie-n1sdp.c
-@@ -30,8 +30,10 @@
-
- /* Platform specific values as hardcoded in the firmware. */
- #define AP_NS_SHARED_MEM_BASE 0x06000000
--#define MAX_SEGMENTS 2 /* Two PCIe root complexes. */
-+/* Two PCIe root complexes in One Chip + One PCIe RC in Remote Chip */
-+#define MAX_SEGMENTS 3
- #define BDF_TABLE_SIZE SZ_16K
-+#define REMOTE_CHIP_ADDR_OFFSET 0x40000000000
-
- /*
- * Shared memory layout as written by the SCP upon boot time:
-@@ -97,12 +99,17 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
- phys_addr_t table_base;
- struct device *dev = cfg->parent;
- struct pcie_discovery_data *shared_data;
-- size_t bdfs_size;
-+ size_t bdfs_size, rc_base_addr = 0;
-
- if (segment >= MAX_SEGMENTS)
- return -ENODEV;
-
-- table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
-+ if (segment > 1) {
-+ rc_base_addr = REMOTE_CHIP_ADDR_OFFSET;
-+ table_base = AP_NS_SHARED_MEM_BASE + REMOTE_CHIP_ADDR_OFFSET;
-+ } else {
-+ table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
-+ }
-
- if (!request_mem_region(table_base, BDF_TABLE_SIZE,
- "PCIe valid BDFs")) {
-@@ -114,6 +121,7 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
- table_base, BDF_TABLE_SIZE);
- if (!shared_data)
- return -ENOMEM;
-+ rc_base_addr += shared_data->rc_base_addr;
-
- /* Copy the valid BDFs structure to allocated normal memory. */
- bdfs_size = sizeof(struct pcie_discovery_data) +
-@@ -125,7 +133,7 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
- memcpy_fromio(pcie_discovery_data[segment], shared_data, bdfs_size);
-
- rc_remapped_addr[segment] = devm_ioremap(dev,
-- shared_data->rc_base_addr,
-+ rc_base_addr,
- PCI_CFG_SPACE_EXP_SIZE);
- if (!rc_remapped_addr[segment]) {
- dev_err(dev, "Cannot remap root port base\n");
-@@ -161,6 +169,12 @@ static int pci_n1sdp_ccix_init(struct pci_config_window *cfg)
- return pci_n1sdp_init(cfg, 1);
- }
-
-+/* Called for ACPI segment 2. */
-+static int pci_n1sdp_remote_pcie_init(struct pci_config_window *cfg)
-+{
-+ return pci_n1sdp_init(cfg, 2);
-+}
-+
- const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops = {
- .bus_shift = 20,
- .init = pci_n1sdp_pcie_init,
-@@ -181,6 +195,16 @@ const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops = {
- }
- };
-
-+const struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops = {
-+ .bus_shift = 20,
-+ .init = pci_n1sdp_remote_pcie_init,
-+ .pci_ops = {
-+ .map_bus = pci_n1sdp_map_bus,
-+ .read = pci_generic_config_read32,
-+ .write = pci_generic_config_write32,
-+ }
-+};
-+
- static const struct of_device_id n1sdp_pcie_of_match[] = {
- { .compatible = "arm,n1sdp-pcie", .data = &pci_n1sdp_pcie_ecam_ops },
- { },
-diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
-index b3cf3adeab28..d4316795c00d 100644
---- a/include/linux/pci-ecam.h
-+++ b/include/linux/pci-ecam.h
-@@ -90,6 +90,7 @@ extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
- extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
- extern const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops; /* Arm N1SDP PCIe */
- extern const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops; /* Arm N1SDP PCIe */
-+extern const struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops; /* Arm N1SDP PCIe */
- #endif
-
- #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
deleted file mode 100644
@@ -1,33 +0,0 @@
-From ff02f77788f8c01e9d675912c063e89415804b7d Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Fri, 17 May 2019 17:39:27 +0100
-Subject: [PATCH] arm64: kpti: Whitelist early Arm Neoverse N1 revisions
-
-Early revisions (r1p0) of the Neoverse N1 core did not feature the
-CSV3 field in ID_AA64PFR0_EL1 to advertise they are not affected by
-the Spectre variant 3 (aka Meltdown) vulnerability.
-
-Add this particular revision to the whitelist to avoid enabling KPTI.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Change-Id: I78df055a3e674aefd195d41cc6dc4ee08b0af099
-Upstream-Status: Inappropriate
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-Signed-off-by: Adam Johnston <adam.johnston@arm.com>
----
- arch/arm64/kernel/cpufeature.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
-index b3f37e2209ad..b74210f38cd8 100644
---- a/arch/arm64/kernel/cpufeature.c
-+++ b/arch/arm64/kernel/cpufeature.c
-@@ -1646,6 +1646,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
- MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
- MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
- MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
-+ MIDR_REV(MIDR_NEOVERSE_N1, 1, 0), /* missing CSV3 */
- { /* sentinel */ }
- };
- char const *str = "kpti command line option";
deleted file mode 100644
@@ -1,57 +0,0 @@
-From afdd5ae3eeb44381f906b6227422373d4af2811d Mon Sep 17 00:00:00 2001
-From: Vishnu Banavath <vishnu.banavath@arm.com>
-Date: Wed, 21 Sep 2022 15:54:14 +0100
-Subject: [PATCH] arm64: defconfig: disable config options that does not apply
- anymore
-
-Following config options should be not set to be more accurate and
-works with build system like yocto
-CONFIG_BT_HCIBTUSB
-CONFIG_BT_HCIBTUSB_MTK
-CONFIG_BT_HCIUART_MRVL
-CONFIG_BT_MRVL
-CONFIG_BT_MRVL_SDIO
-CONFIG_BT_QCOMSMD
-CONFIG_BT_NXPUART
-
-Upstream-Status: Pending [not submitted upstream yet]
-Signed-off-by: Adam Johnston <adam.johnston@arm.com>
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
-Signed-off-by: Anusmita Dutta Mazumder <anusmita.duttamazumder@arm.com>
----
- arch/arm64/configs/defconfig | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
-index d2b5208eb55d..b3028113de25 100644
---- a/arch/arm64/configs/defconfig
-+++ b/arch/arm64/configs/defconfig
-@@ -186,17 +186,17 @@ CONFIG_BT_HIDP=m
- # CONFIG_BT_LE is not set
- CONFIG_BT_LEDS=y
- # CONFIG_BT_DEBUGFS is not set
--CONFIG_BT_HCIBTUSB=m
--CONFIG_BT_HCIBTUSB_MTK=y
-+# CONFIG_BT_HCIBTUSB is not set
-+# CONFIG_BT_HCIBTUSB_MTK is not set
- CONFIG_BT_HCIUART=m
- CONFIG_BT_HCIUART_LL=y
- CONFIG_BT_HCIUART_BCM=y
- CONFIG_BT_HCIUART_QCA=y
--CONFIG_BT_HCIUART_MRVL=y
--CONFIG_BT_MRVL=m
--CONFIG_BT_MRVL_SDIO=m
--CONFIG_BT_QCOMSMD=m
--CONFIG_BT_NXPUART=m
-+# CONFIG_BT_HCIUART_MRVL is not set
-+# CONFIG_BT_MRVL is not set
-+# CONFIG_BT_MRVL_SDIO is not set
-+# CONFIG_BT_QCOMSMD is not set
-+# CONFIG_BT_NXPUART is not set
- CONFIG_CFG80211=m
- CONFIG_MAC80211=m
- CONFIG_MAC80211_LEDS=y
-2.38.1
-
deleted file mode 100644
@@ -1,3 +0,0 @@
-# Enable NVMe flash storage support
-CONFIG_NVME_CORE=y
-CONFIG_BLK_DEV_NVME=y
deleted file mode 100644
@@ -1,3 +0,0 @@
-# Enable Realtek Gigabit Ethernet adapter
-CONFIG_REALTEK_PHY=y
-CONFIG_R8169=y
deleted file mode 100644
@@ -1,2 +0,0 @@
-# PHY_TEGRA_XUSB sets this to y, but its set as m in defconfig
-CONFIG_USB_CONN_GPIO=y
deleted file mode 100644
@@ -1,2 +0,0 @@
-# CONFIG_USB_XHCI_PCI is not set
-# CONFIG_USB_XHCI_PCI_RENESAS is not set
deleted file mode 100644
@@ -1,237 +0,0 @@
-From 56f2afcd10e8404a3c4efed6277a005fc4099e48 Mon Sep 17 00:00:00 2001
-From: Vishnu Banavath <vishnu.banavath@arm.com>
-Date: Thu, 30 Jun 2022 18:36:26 +0100
-Subject: [PATCH] plat-n1sdp: add N1SDP platform support
-
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-
-These changes are to add N1SDP platform to optee-os
-
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
-Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
----
- core/arch/arm/plat-n1sdp/conf.mk | 41 +++++++++++++++++
- core/arch/arm/plat-n1sdp/main.c | 53 ++++++++++++++++++++++
- core/arch/arm/plat-n1sdp/n1sdp_core_pos.S | 32 +++++++++++++
- core/arch/arm/plat-n1sdp/platform_config.h | 49 ++++++++++++++++++++
- core/arch/arm/plat-n1sdp/sub.mk | 3 ++
- 5 files changed, 178 insertions(+)
- create mode 100644 core/arch/arm/plat-n1sdp/conf.mk
- create mode 100644 core/arch/arm/plat-n1sdp/main.c
- create mode 100644 core/arch/arm/plat-n1sdp/n1sdp_core_pos.S
- create mode 100644 core/arch/arm/plat-n1sdp/platform_config.h
- create mode 100644 core/arch/arm/plat-n1sdp/sub.mk
-
-diff --git a/core/arch/arm/plat-n1sdp/conf.mk b/core/arch/arm/plat-n1sdp/conf.mk
-new file mode 100644
-index 000000000..3dc79fe20
---- /dev/null
-+++ b/core/arch/arm/plat-n1sdp/conf.mk
-@@ -0,0 +1,41 @@
-+include core/arch/arm/cpu/cortex-armv8-0.mk
-+
-+CFG_DEBUG_INFO = y
-+CFG_TEE_CORE_LOG_LEVEL = 4
-+
-+# Workaround 808870: Unconditional VLDM instructions might cause an
-+# alignment fault even though the address is aligned
-+# Either hard float must be disabled for AArch32 or strict alignment checks
-+# must be disabled
-+ifeq ($(CFG_SCTLR_ALIGNMENT_CHECK),y)
-+$(call force,CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT,y)
-+else
-+$(call force,CFG_SCTLR_ALIGNMENT_CHECK,n)
-+endif
-+
-+CFG_ARM64_core ?= y
-+
-+CFG_ARM_GICV3 = y
-+
-+# ARM debugger needs this
-+platform-cflags-debug-info = -gdwarf-4
-+platform-aflags-debug-info = -gdwarf-4
-+
-+CFG_CORE_SEL1_SPMC = y
-+CFG_WITH_ARM_TRUSTED_FW = y
-+
-+$(call force,CFG_GIC,y)
-+$(call force,CFG_PL011,y)
-+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
-+
-+CFG_CORE_HEAP_SIZE = 0x32000 # 200kb
-+
-+CFG_TEE_CORE_NB_CORE = 4
-+CFG_TZDRAM_START ?= 0xDE000000
-+CFG_TZDRAM_SIZE ?= 0x02000000
-+
-+CFG_SHMEM_START ?= 0x83000000
-+CFG_SHMEM_SIZE ?= 0x00210000
-+# DRAM1 is defined above 4G
-+$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
-+$(call force,CFG_CORE_ARM64_PA_BITS,36)
-diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c
-new file mode 100644
-index 000000000..38212d84c
---- /dev/null
-+++ b/core/arch/arm/plat-n1sdp/main.c
-@@ -0,0 +1,53 @@
-+// SPDX-License-Identifier: BSD-2-Clause
-+/*
-+ * Copyright (c) 2022, Arm Limited.
-+ */
-+
-+#include <arm.h>
-+#include <console.h>
-+#include <drivers/gic.h>
-+#include <drivers/pl011.h>
-+#include <drivers/tzc400.h>
-+#include <initcall.h>
-+#include <keep.h>
-+#include <kernel/boot.h>
-+#include <kernel/interrupt.h>
-+#include <kernel/misc.h>
-+#include <kernel/notif.h>
-+#include <kernel/panic.h>
-+#include <kernel/spinlock.h>
-+#include <kernel/tee_time.h>
-+#include <mm/core_memprot.h>
-+#include <mm/core_mmu.h>
-+#include <platform_config.h>
-+#include <sm/psci.h>
-+#include <stdint.h>
-+#include <string.h>
-+#include <trace.h>
-+
-+static struct pl011_data console_data __nex_bss;
-+
-+register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
-+
-+register_ddr(DRAM0_BASE, DRAM0_SIZE);
-+
-+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
-+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
-+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE);
-+
-+void main_init_gic(void)
-+{
-+ gic_init(GICC_BASE, GICD_BASE);
-+}
-+
-+void main_secondary_init_gic(void)
-+{
-+ gic_init_per_cpu();
-+}
-+
-+void console_init(void)
-+{
-+ pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
-+ CONSOLE_BAUDRATE);
-+ register_serial_console(&console_data.chip);
-+}
-diff --git a/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S b/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S
-new file mode 100644
-index 000000000..439d4e675
---- /dev/null
-+++ b/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: BSD-2-Clause */
-+/*
-+ * Copyright (c) 2022, Arm Limited
-+ */
-+
-+#include <asm.S>
-+#include <arm.h>
-+#include "platform_config.h"
-+
-+FUNC get_core_pos_mpidr , :
-+ mov x4, x0
-+
-+ /*
-+ * The MT bit in MPIDR is always set for n1sdp and the
-+ * affinity level 0 corresponds to thread affinity level.
-+ */
-+
-+ /* Extract individual affinity fields from MPIDR */
-+ ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
-+ ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
-+ ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
-+ ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
-+
-+ /* Compute linear position */
-+ mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP
-+ madd x2, x3, x4, x2
-+ mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER
-+ madd x1, x2, x4, x1
-+ mov x4, #N1SDP_MAX_PE_PER_CPU
-+ madd x0, x1, x4, x0
-+ ret
-+END_FUNC get_core_pos_mpidr
-diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h
-new file mode 100644
-index 000000000..81b994091
---- /dev/null
-+++ b/core/arch/arm/plat-n1sdp/platform_config.h
-@@ -0,0 +1,49 @@
-+/* SPDX-License-Identifier: BSD-2-Clause */
-+/*
-+ * Copyright (c) 2022, Arm Limited
-+ */
-+
-+#ifndef PLATFORM_CONFIG_H
-+#define PLATFORM_CONFIG_H
-+
-+#include <mm/generic_ram_layout.h>
-+#include <stdint.h>
-+
-+/* Make stacks aligned to data cache line length */
-+#define STACK_ALIGNMENT 64
-+
-+ /* N1SDP topology related constants */
-+#define N1SDP_MAX_CPUS_PER_CLUSTER U(2)
-+#define PLAT_ARM_CLUSTER_COUNT U(2)
-+#define PLAT_N1SDP_CHIP_COUNT U(2)
-+#define N1SDP_MAX_CLUSTERS_PER_CHIP U(2)
-+#define N1SDP_MAX_PE_PER_CPU U(1)
-+
-+#define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \
-+ PLAT_ARM_CLUSTER_COUNT * \
-+ N1SDP_MAX_CPUS_PER_CLUSTER * \
-+ N1SDP_MAX_PE_PER_CPU)
-+
-+#define GIC_BASE 0x2c010000
-+
-+#define UART1_BASE 0x1C0A0000
-+#define UART1_CLK_IN_HZ 24000000 /*24MHz*/
-+
-+#define CONSOLE_UART_BASE UART1_BASE
-+#define CONSOLE_UART_CLK_IN_HZ UART1_CLK_IN_HZ
-+
-+#define DRAM0_BASE 0x80000000
-+#define DRAM0_SIZE 0x80000000
-+
-+#define GICD_BASE 0x30000000
-+#define GICC_BASE 0x2C000000
-+#define GICR_BASE 0x300C0000
-+
-+#ifndef UART_BAUDRATE
-+#define UART_BAUDRATE 115200
-+#endif
-+#ifndef CONSOLE_BAUDRATE
-+#define CONSOLE_BAUDRATE UART_BAUDRATE
-+#endif
-+
-+#endif /*PLATFORM_CONFIG_H*/
-diff --git a/core/arch/arm/plat-n1sdp/sub.mk b/core/arch/arm/plat-n1sdp/sub.mk
-new file mode 100644
-index 000000000..a0b49da14
---- /dev/null
-+++ b/core/arch/arm/plat-n1sdp/sub.mk
-@@ -0,0 +1,3 @@
-+global-incdirs-y += .
-+srcs-y += main.c
-+srcs-y += n1sdp_core_pos.S
-2.25.1
-
deleted file mode 100644
@@ -1,32 +0,0 @@
-Upstream-Status: Pending [upstreamed differently in 280b6a3]
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-
-From b3fde6c2e1a950214f760ab9f194f3a6572292a8 Mon Sep 17 00:00:00 2001
-From: Balint Dobszay <balint.dobszay@arm.com>
-Date: Fri, 15 Jul 2022 13:45:54 +0200
-Subject: [PATCH] Handle logging syscall
-
-Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
-Change-Id: Ib8151cc9c66aea8bcc8fe8b1ecdc3f9f9c5f14e4
-
-
-diff --git a/core/arch/arm/kernel/spmc_sp_handler.c b/core/arch/arm/kernel/spmc_sp_handler.c
-index e0fa0aa6..c7a45387 100644
---- a/core/arch/arm/kernel/spmc_sp_handler.c
-+++ b/core/arch/arm/kernel/spmc_sp_handler.c
-@@ -1277,6 +1277,13 @@ void spmc_sp_msg_handler(struct thread_smc_args *args,
- sp_enter(args, caller_sp);
- break;
-
-+ case 0xdeadbeef:
-+ ts_push_current_session(&caller_sp->ts_sess);
-+ IMSG("%s", (char *)args->a1);
-+ ts_pop_current_session();
-+ sp_enter(args, caller_sp);
-+ break;
-+
- default:
- EMSG("Unhandled FFA function ID %#"PRIx32,
- (uint32_t)args->a0);
-2.17.1
deleted file mode 100644
@@ -1,52 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-
-From 2eb1da30564428551ca687d456d848129105abac Mon Sep 17 00:00:00 2001
-From: Vishnu Banavath <vishnu.banavath@arm.com>
-Date: Tue, 25 Oct 2022 19:08:49 +0100
-Subject: [PATCH] plat-n1sdp: register DRAM1 to optee-os
-
-N1SDP supports two DRAM's. This change is to add 2nd DRAM
-starting at 0x8080000000 address.
-
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-
-diff --git a/core/arch/arm/plat-n1sdp/conf.mk b/core/arch/arm/plat-n1sdp/conf.mk
-index 06b4975a..5374e406 100644
---- a/core/arch/arm/plat-n1sdp/conf.mk
-+++ b/core/arch/arm/plat-n1sdp/conf.mk
-@@ -38,4 +38,4 @@ CFG_SHMEM_START ?= 0x83000000
- CFG_SHMEM_SIZE ?= 0x00210000
- # DRAM1 is defined above 4G
- $(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
--$(call force,CFG_CORE_ARM64_PA_BITS,36)
-+$(call force,CFG_CORE_ARM64_PA_BITS,42)
-diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c
-index cfb7f19b..bb951ce6 100644
---- a/core/arch/arm/plat-n1sdp/main.c
-+++ b/core/arch/arm/plat-n1sdp/main.c
-@@ -33,6 +33,7 @@ static struct pl011_data console_data __nex_bss;
- register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
-
- register_ddr(DRAM0_BASE, DRAM0_SIZE);
-+register_ddr(DRAM1_BASE, DRAM1_SIZE);
-
- register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
- register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
-diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h
-index 81b99409..bf0a3c83 100644
---- a/core/arch/arm/plat-n1sdp/platform_config.h
-+++ b/core/arch/arm/plat-n1sdp/platform_config.h
-@@ -35,6 +35,9 @@
- #define DRAM0_BASE 0x80000000
- #define DRAM0_SIZE 0x80000000
-
-+#define DRAM1_BASE 0x8080000000ULL
-+#define DRAM1_SIZE 0x80000000ULL
-+
- #define GICD_BASE 0x30000000
- #define GICC_BASE 0x2C000000
- #define GICR_BASE 0x300C0000
-2.17.1
-
deleted file mode 100644
@@ -1,44 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
-
-From 1a9aeedda58228893add545e49d2d6cd4c316b4f Mon Sep 17 00:00:00 2001
-From: Emekcan <emekcan.aras@arm.com>
-Date: Tue, 13 Dec 2022 13:45:06 +0000
-Subject: [PATCH] plat-n1sdp: add external device tree base and size
-
-Adds external device tree address and size. It also
-register this physical memory so optee can read the device tree.
----
- core/arch/arm/plat-n1sdp/main.c | 1 +
- core/arch/arm/plat-n1sdp/platform_config.h | 3 +++
- 2 files changed, 4 insertions(+)
-
-diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c
-index bb951ce6b..ab76f60c6 100644
---- a/core/arch/arm/plat-n1sdp/main.c
-+++ b/core/arch/arm/plat-n1sdp/main.c
-@@ -31,6 +31,7 @@ static struct gic_data gic_data __nex_bss;
- static struct pl011_data console_data __nex_bss;
-
- register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
-+register_phys_mem_pgdir(MEM_AREA_EXT_DT, EXT_DT_BASE, EXT_DT_SIZE);
-
- register_ddr(DRAM0_BASE, DRAM0_SIZE);
- register_ddr(DRAM1_BASE, DRAM1_SIZE);
-diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h
-index bf0a3c834..8741a2503 100644
---- a/core/arch/arm/plat-n1sdp/platform_config.h
-+++ b/core/arch/arm/plat-n1sdp/platform_config.h
-@@ -42,6 +42,9 @@
- #define GICC_BASE 0x2C000000
- #define GICR_BASE 0x300C0000
-
-+#define EXT_DT_BASE 0x04001600
-+#define EXT_DT_SIZE 0x200
-+
- #ifndef UART_BAUDRATE
- #define UART_BAUDRATE 115200
- #endif
-2.17.1
-
deleted file mode 100644
@@ -1,2 +0,0 @@
-COMPATIBLE_MACHINE:n1sdp = "n1sdp"
-OPTEEMACHINE:n1sdp = "n1sdp"
deleted file mode 100644
@@ -1,29 +0,0 @@
-# N1 SDP specific configuration for optee-os
-
-require optee-os-generic-n1sdp.inc
-
-TS_INSTALL_PREFIX_PATH = "${RECIPE_SYSROOT}/firmware/sp/opteesp"
-
-FILESEXTRAPATHS:prepend := "${THISDIR}/files/optee-os/n1sdp:"
-SRC_URI:append = " \
- file://0001-plat-n1sdp-add-N1SDP-platform-support.patch \
- file://0002-Handle-logging-syscall.patch \
- file://0003-plat-n1sdp-register-DRAM1-to-optee-os.patch \
- file://0004-plat-n1sdp-add-external-device-tree-base-and-size.patch \
- "
-
-EXTRA_OEMAKE += " CFG_TEE_CORE_LOG_LEVEL=4"
-
-EXTRA_OEMAKE += " CFG_TEE_BENCHMARK=n"
-
-EXTRA_OEMAKE += " CFG_CORE_SEL1_SPMC=y CFG_CORE_FFA=y"
-
-EXTRA_OEMAKE += " CFG_WITH_SP=y"
-
-EXTRA_OEMAKE += " CFG_DT=y"
-
-EXTRA_OEMAKE += " CFG_SECURE_PARTITION=y"
-
-EXTRA_OEMAKE += " CFG_MAP_EXT_DT_SECURE=y"
-
-EXTRA_OEMAKE += " CFG_ENABLE_EMBEDDED_TESTS=y"
@@ -1,7 +1,6 @@
# Machine specific configurations
MACHINE_OPTEE_OS_TADEVKIT_REQUIRE ?= ""
-MACHINE_OPTEE_OS_TADEVKIT_REQUIRE:n1sdp = "optee-os-n1sdp.inc"
MACHINE_OPTEE_OS_TADEVKIT_REQUIRE:fvp-base = "optee-os-fvp-base.inc"
require ${MACHINE_OPTEE_OS_TADEVKIT_REQUIRE}
@@ -3,7 +3,6 @@
MACHINE_OPTEE_OS_REQUIRE ?= ""
MACHINE_OPTEE_OS_REQUIRE:corstone1000 = "optee-os-corstone1000-common.inc"
MACHINE_OPTEE_OS_REQUIRE:fvp-base = "optee-os-fvp-base.inc"
-MACHINE_OPTEE_OS_REQUIRE:n1sdp = "optee-os-n1sdp.inc"
MACHINE_OPTEE_OS_REQUIRE:sbsa-ref = "optee-os-sbsa-ref.inc"
require ${MACHINE_OPTEE_OS_REQUIRE}
@@ -1,7 +1,6 @@
# Machine specific configurations
MACHINE_OPTEE_TEST_REQUIRE ?= ""
-MACHINE_OPTEE_TEST_REQUIRE:n1sdp = "optee-os-generic-n1sdp.inc"
MACHINE_OPTEE_TEST_REQUIRE:fvp-base = "optee-test-fvp-base.inc"
require ${MACHINE_OPTEE_TEST_REQUIRE}
@@ -1,3 +1,2 @@
COMPATIBLE_MACHINE:corstone1000 = "corstone1000"
-COMPATIBLE_MACHINE:n1sdp = "n1sdp"
COMPATIBLE_MACHINE:fvp-base = "fvp-base"
@@ -13,8 +13,5 @@ SRC_URI:append:corstone1000 = " \
file://0009-Remove-Werror-flag.patch \
"
-
-COMPATIBLE_MACHINE:n1sdp = "n1sdp"
-
COMPATIBLE_MACHINE:fvp-base = "fvp-base"
TS_PLATFORM:fvp-base = "arm/fvp/fvp_base_revc-2xaemv8a"
@@ -5,5 +5,4 @@ SRC_URI:append:corstone1000 = " \
file://0001-newlib-memcpy-remove-optimized-version.patch;patchdir=../newlib \
"
-COMPATIBLE_MACHINE:n1sdp = "n1sdp"
COMPATIBLE_MACHINE:fvp-base = "fvp-base"
deleted file mode 100644
@@ -1,9 +0,0 @@
-# short-description: Create an EFI disk image
-# long-description: Creates a partitioned EFI disk image that the user
-# can directly dd to boot media. Uses a custom grub.cfg file to configure the boot.
-
-part /boot --source bootimg-efi --sourceparams="loader=grub-efi" --ondisk sda --label msdos --active --align 1024
-
-part / --source rootfs --ondisk sda --fstype=ext4 --label root --align 1024 --uuid=6a60524d-061d-454a-bfd1-38989910eccd
-
-bootloader --ptable gpt --configfile="n1sdp-grub.cfg" --timeout=5
deleted file mode 100644
@@ -1,18 +0,0 @@
-set debug="loader,mm"
-set term="vt100"
-set default="0"
-set timeout="5"
-
-menuentry 'Arm reference image boot on N1SDP (ACPI)' {
- linux /Image earlycon=pl011,0x2A400000 console=ttyAMA0,115200 root=PARTUUID=6a60524d-061d-454a-bfd1-38989910eccd rootwait rootfstype=ext4 acpi=force
-}
-
-menuentry 'Arm reference image boot on Single-Chip N1SDP (Device Tree)' {
- devicetree /n1sdp-single-chip.dtb
- linux /Image earlycon=pl011,0x2A400000 console=ttyAMA0,115200 root=PARTUUID=6a60524d-061d-454a-bfd1-38989910eccd rootwait rootfstype=ext4
-}
-
-menuentry 'Arm reference image boot on Multi-Chip N1SDP (Device Tree)' {
- devicetree /n1sdp-multi-chip.dtb
- linux /Image earlycon=pl011,0x2A400000 console=ttyAMA0,115200 root=PARTUUID=6a60524d-061d-454a-bfd1-38989910eccd rootwait rootfstype=ext4
-}
Signed-off-by: Jon Mason <jon.mason@arm.com> --- .gitlab-ci.yml | 6 - README.md | 2 +- ci/n1sdp-optee.yml | 14 - ci/n1sdp-ts.yml | 16 - ci/n1sdp.yml | 12 - documentation/trusted-services.md | 6 +- meta-arm-bsp/conf/machine/n1sdp.conf | 51 - meta-arm-bsp/documentation/n1sdp.md | 78 - meta-arm-bsp/documentation/template.md | 2 +- .../images/n1sdp-board-firmware_2022.06.22.bb | 37 - .../images/sdcard-image-n1sdp_0.1.bb | 85 - .../scp-firmware/scp-firmware-n1sdp.inc | 35 - .../scp-firmware/scp-firmware_%.bbappend | 1 - .../0001-Reserve-OP-TEE-memory-from-nwd.patch | 42 - .../n1sdp/0001-n1sdp-tftf-tests-to-skip.patch | 46 - .../0002-Modify-BL32-Location-to-DDR4.patch | 30 - .../n1sdp/0003-Modify-SPMC-Base-to-DDR4.patch | 28 - .../trusted-firmware-a/tf-a-tests_%.bbappend | 10 - .../trusted-firmware-a-n1sdp.inc | 41 - .../trusted-firmware-a_%.bbappend | 1 - .../recipes-bsp/uefi/edk2-firmware-n1sdp.inc | 30 - .../recipes-bsp/uefi/edk2-firmware_%.bbappend | 1 - ...dp-Add-support-to-parse-NT_FW_CONFIG.patch | 471 --- ...dp-Modify-the-IRQ-ID-of-Debug-UART-a.patch | 63 - ...erseN1Soc-Enable-SCP-QSPI-flash-regi.patch | 57 - ...RM-N1Sdp-NOR-flash-library-for-N1Sdp.patch | 119 - ...N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch | 2538 ----------------- ...M-N1Sdp-Persistent-storage-for-N1Sdp.patch | 88 - ...dp-Enable-FaultTolerantWrite-Dxe-dri.patch | 50 - ...dp-manually-poll-QSPI-status-bit-aft.patch | 197 -- ...1Sdp-Reserve-OP-TEE-Region-from-UEFI.patch | 72 - .../bsp/arm-platforms/n1sdp-preempt-rt.scc | 6 - .../bsp/arm-platforms/n1sdp-standard.scc | 5 - .../bsp/arm-platforms/n1sdp/disable-kvm.cfg | 1 - .../linux/linux-arm-platforms.inc | 25 - ...3-workaround-for-ATC_INV_SIZE_ALL-in.patch | 47 - ...irk-add-acs-override-for-PCI-devices.patch | 159 -- ...-for-the-Arm-Neoverse-N1SDP-platform.patch | 324 --- ...uirk-support-enabling-remote-chip-PC.patch | 136 - ...list-early-Arm-Neoverse-N1-revisions.patch | 33 - ...disable-config-options-that-does-not.patch | 57 - .../linux-yocto-6.6/n1sdp/enable-nvme.cfg | 3 - .../n1sdp/enable-realtek-R8169.cfg | 3 - .../n1sdp/enable-usb_conn_gpio.cfg | 2 - .../n1sdp/usb_xhci_pci_renesas.cfg | 2 - ...lat-n1sdp-add-N1SDP-platform-support.patch | 237 -- .../n1sdp/0002-Handle-logging-syscall.patch | 32 - ...lat-n1sdp-register-DRAM1-to-optee-os.patch | 52 - ...d-external-device-tree-base-and-size.patch | 44 - .../optee/optee-os-generic-n1sdp.inc | 2 - .../recipes-security/optee/optee-os-n1sdp.inc | 29 - .../optee/optee-os-tadevkit_4.%.bbappend | 1 - .../optee/optee-os_4.%.bbappend | 1 - .../optee/optee-test_4.%.bbappend | 1 - .../packagegroup-ts-tests.bbappend | 1 - .../trusted-services/ts-arm-platforms.inc | 3 - .../trusted-services/ts-newlib_%.bbappend | 1 - meta-arm-bsp/wic/n1sdp-efidisk.wks | 9 - meta-arm-bsp/wic/n1sdp-grub.cfg | 18 - 59 files changed, 4 insertions(+), 5459 deletions(-) delete mode 100644 ci/n1sdp-optee.yml delete mode 100644 ci/n1sdp-ts.yml delete mode 100644 ci/n1sdp.yml delete mode 100644 meta-arm-bsp/conf/machine/n1sdp.conf delete mode 100644 meta-arm-bsp/documentation/n1sdp.md delete mode 100644 meta-arm-bsp/recipes-bsp/images/n1sdp-board-firmware_2022.06.22.bb delete mode 100644 meta-arm-bsp/recipes-bsp/images/sdcard-image-n1sdp_0.1.bb delete mode 100644 meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware-n1sdp.inc delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/n1sdp/0001-Reserve-OP-TEE-memory-from-nwd.patch delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/n1sdp/0001-n1sdp-tftf-tests-to-skip.patch delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/n1sdp/0002-Modify-BL32-Location-to-DDR4.patch delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/n1sdp/0003-Modify-SPMC-Base-to-DDR4.patch delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-n1sdp.inc delete mode 100644 meta-arm-bsp/recipes-bsp/uefi/edk2-firmware-n1sdp.inc delete mode 100644 meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch delete mode 100644 meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0002-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch delete mode 100644 meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0003-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch delete mode 100644 meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0004-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch delete mode 100644 meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0005-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch delete mode 100644 meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0006-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch delete mode 100644 meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0007-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch delete mode 100644 meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch delete mode 100644 meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0009-Platform-ARM-N1Sdp-Reserve-OP-TEE-Region-from-UEFI.patch delete mode 100644 meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/n1sdp-preempt-rt.scc delete mode 100644 meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/n1sdp-standard.scc delete mode 100644 meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/n1sdp/disable-kvm.cfg delete mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto-6.6/n1sdp/0001-iommu-arm-smmu-v3-workaround-for-ATC_INV_SIZE_ALL-in.patch delete mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto-6.6/n1sdp/0002-n1sdp-pci_quirk-add-acs-override-for-PCI-devices.patch delete mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto-6.6/n1sdp/0003-pcie-Add-quirk-for-the-Arm-Neoverse-N1SDP-platform.patch delete mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto-6.6/n1sdp/0004-n1sdp-pcie-add-quirk-support-enabling-remote-chip-PC.patch delete mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto-6.6/n1sdp/0005-arm64-kpti-Whitelist-early-Arm-Neoverse-N1-revisions.patch delete mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto-6.6/n1sdp/0006-arm64-defconfig-disable-config-options-that-does-not.patch delete mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto-6.6/n1sdp/enable-nvme.cfg delete mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto-6.6/n1sdp/enable-realtek-R8169.cfg delete mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto-6.6/n1sdp/enable-usb_conn_gpio.cfg delete mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto-6.6/n1sdp/usb_xhci_pci_renesas.cfg delete mode 100644 meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0001-plat-n1sdp-add-N1SDP-platform-support.patch delete mode 100644 meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0002-Handle-logging-syscall.patch delete mode 100644 meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0003-plat-n1sdp-register-DRAM1-to-optee-os.patch delete mode 100644 meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0004-plat-n1sdp-add-external-device-tree-base-and-size.patch delete mode 100644 meta-arm-bsp/recipes-security/optee/optee-os-generic-n1sdp.inc delete mode 100644 meta-arm-bsp/recipes-security/optee/optee-os-n1sdp.inc delete mode 100644 meta-arm-bsp/wic/n1sdp-efidisk.wks delete mode 100644 meta-arm-bsp/wic/n1sdp-grub.cfg