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From: emekcan.aras@arm.com
To: meta-arm@lists.yoctoproject.org
Cc: Emekcan Aras <Emekcan.Aras@arm.com>
Subject: [PATCH 0/1] arm-bsp/trusted-firmware-a: corstone1000: fix reset
sequence
Date: Thu, 16 May 2024 15:03:23 +0100
Message-Id: <20240516140324.67124-1-emekcan.aras@arm.com>
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From: Emekcan Aras <Emekcan.Aras@arm.com>
Corstone1000 does not properly clean the cache and disable gic interrupts
before the reset. This causes a race condition especially in FVP after reset.
This adds proper sequence before resetting the platform.
Emekcan Aras (1):
arm-bsp/trusted-firmware-a: corstone1000: fix reset sequence
...-clean-the-cache-and-disable-interru.patch | 46 +++++++++++++++++++
.../trusted-firmware-a-corstone1000.inc | 1 +
2 files changed, 47 insertions(+)
create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0005-fix-corstone1000-clean-the-cache-and-disable-interru.patch
From: Emekcan Aras <Emekcan.Aras@arm.com> Corstone1000 does not properly clean the cache and disable gic interrupts before the reset. This causes a race condition especially in FVP after reset. This adds proper sequence before resetting the platform. Emekcan Aras (1): arm-bsp/trusted-firmware-a: corstone1000: fix reset sequence ...-clean-the-cache-and-disable-interru.patch | 46 +++++++++++++++++++ .../trusted-firmware-a-corstone1000.inc | 1 + 2 files changed, 47 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0005-fix-corstone1000-clean-the-cache-and-disable-interru.patch