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[93.89.130.18]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4756636cf98sm12680161f8f.22.2026.07.01.04.58.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jul 2026 04:58:34 -0700 (PDT) From: Alex Kiernan Date: Wed, 01 Jul 2026 12:58:11 +0100 Subject: [PATCH 1/3] rust-target-config: armv8a AArch32 Thumb build fixes MIME-Version: 1.0 Message-Id: <20260701-tune-a32-v1-1-a43f28b1d7a4@gmail.com> References: <20260701-tune-a32-v1-0-a43f28b1d7a4@gmail.com> In-Reply-To: <20260701-tune-a32-v1-0-a43f28b1d7a4@gmail.com> To: openembedded-core@lists.openembedded.org Cc: Alex Kiernan , Alex Kiernan X-Mailer: b4 0.15.2 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 01 Jul 2026 11:58:40 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/239978 From: Alex Kiernan llvm_features_from_tune() calls target_is_armv7() to gate both the +v7 LLVM feature and the +thumb2 feature. target_is_armv7() (in rust-common.bbclass) only recognises armv7a/armv7r/armv7m/armv7ve -- it returns False for armv8a. As a result an ARMv8-A AArch32 Thumb build gets "+neon,+thumb-mode" in the target JSON but neither "+v8" nor "+thumb2". LLVM's ParseARMTriple() returns "" for "arm-..." triples (ARM::parseArch("arm") = INVALID), leaving HasV4TOps unset in the MCSubtargetInfo used for module-level inline asm parsing. The ARM ASM parser's hasThumb() then returns false and ".thumb" directives in compiler_builtins naked-function trampolines (__aeabi_uldivmod etc.) are rejected. This produces two failures when building libstd-rs / compiler_builtins: 1. core: "LLVM ERROR: Cannot select: br" in core::fmt::num -- LLVM ARM ISel patterns for Thumb-2 unconditional branches (t2B) are gated on HasV8Ops as well as IsThumb2; without +v8 the pattern never fires. 2. compiler_builtins: "target does not support Thumb mode" on .thumb directives in naked-function trampolines (__aeabi_uldivmod etc.) -- two separate paths both require +thumb2: HasV4TOps in the MCSubtargetInfo (set transitively via ParseARMTriple) and FeatureThumb2 in the code-gen ARMSubtarget. The natural fix would be to change RUST_TARGET_SYS to "armv8a-...", but "armv8a" is not a recognised Rust target architecture so the triple is not valid there. Instead rust_sys_to_llvm_target() rewrites only the JSON llvm-target field, leaving RUST_TARGET_SYS and rust-common.bbclass unchanged. - Add +v8 to llvm_features_from_tune for armv8a AArch32. - Add +thumb2 to llvm_features_from_tune for armv8a AArch32 Thumb. - Extend rust_sys_to_llvm_target() to accept the datastore and rewrite the "arm-..." triple to "armv8a-..." for armv8a AArch32 targets, so the JSON llvm-target field uses "armv8a-..." while RUST_TARGET_SYS keeps "arm-...". ParseARMTriple then adds "+armv8-a" to the MCSubtargetInfo, transitively setting HasV4TOps and making hasThumb() return true. The TARGET_ARCH == 'arm' guard is required because AArch64 tunes also carry armv8a in TUNE_FEATURES (via arch-armv8a.inc) but must not be affected. AI-Generated: Claude Code (Claude Opus 4.8) Signed-off-by: Alex Kiernan Signed-off-by: Alex Kiernan --- meta/classes-recipe/rust-target-config.bbclass | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/meta/classes-recipe/rust-target-config.bbclass b/meta/classes-recipe/rust-target-config.bbclass index 941fe1958361..6acbe5e68834 100644 --- a/meta/classes-recipe/rust-target-config.bbclass +++ b/meta/classes-recipe/rust-target-config.bbclass @@ -19,6 +19,8 @@ def llvm_features_from_tune(d): mach_overrides = d.getVar('MACHINEOVERRIDES') mach_overrides = frozenset(mach_overrides.split(':')) + target_arch = d.getVar('TARGET_ARCH') + if 'vfpv4' in feat: f.append("+vfp4") elif 'vfpv4d16' in feat: @@ -46,6 +48,9 @@ def llvm_features_from_tune(d): if target_is_armv7(d): f.append('+v7') + if 'armv8a' in feat and target_arch == 'arm': + f.append('+v8') + if ('armv6' in mach_overrides) or ('armv6' in feat): f.append("+v6") if 'armv5te' in feat: @@ -63,7 +68,8 @@ def llvm_features_from_tune(d): if 'thumb' in feat: if d.getVar('ARM_THUMB_OPT') == "thumb": - if target_is_armv7(d): + if target_is_armv7(d) or \ + ('armv8a' in feat and target_arch == 'arm'): f.append('+thumb2') f.append("+thumb-mode") @@ -302,7 +308,16 @@ def arch_to_rust_target_arch(arch): return arch # Convert a rust target string to a llvm-compatible triplet -def rust_sys_to_llvm_target(sys): +def rust_sys_to_llvm_target(sys, d): + # For AArch32 ARMv8-A, RUST_TARGET_SYS stays "arm-..." because "armv8a" is not a + # valid Rust target architecture. Rewrite llvm-target to "armv8a-..." here so + # ParseARMTriple adds "+armv8-a" and transitively sets HasV4TOps in the + # MCSubtargetInfo used for module-level inline asm parsing, making hasThumb() + # return true for .thumb directives. + if sys.startswith('arm-') and \ + 'armv8a' in (d.getVar('TUNE_FEATURES') or '').split() and \ + d.getVar('TARGET_ARCH') == 'arm': + return 'armv8a-' + sys[4:] return sys # generates our target CPU value @@ -382,7 +397,7 @@ def rust_gen_target(d, thing, wd, arch): # build tspec tspec = {} - tspec['llvm-target'] = rust_sys_to_llvm_target(rustsys) + tspec['llvm-target'] = rust_sys_to_llvm_target(rustsys, d) tspec['data-layout'] = d.getVarFlag('DATA_LAYOUT', arch_abi) if tspec['data-layout'] is None: bb.fatal("No rust target defined for %s" % arch_abi) From patchwork Wed Jul 1 11:58:12 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Kiernan X-Patchwork-Id: 91501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA659C43327 for ; Wed, 1 Jul 2026 11:58:40 +0000 (UTC) Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.groups.io with SMTP id smtpd.msgproc02-g2.43270.1782907117355857824 for ; Wed, 01 Jul 2026 04:58:37 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20251104 header.b=ckP38LlW; spf=pass (domain: gmail.com, ip: 209.85.221.48, mailfrom: alex.kiernan@gmail.com) Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-4745492ed3aso332916f8f.1 for ; Wed, 01 Jul 2026 04:58:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1782907115; x=1783511915; darn=lists.openembedded.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Xi59yU2SD11/K7leMDXhuashplqtw/UHNq7fzaxoEQ4=; b=ckP38LlWTqR1orGW+TROaPmLlUkGnQT0qCFwq9HKa4RNHB8Y643qPcGxYQscMw1WjB kfB/IZX/Wbxn/YYIlVETmC/illjZDIWH11einr9ZYFnIqQFNwqmqT0bkQg4Z0gmsVzlO uPrhZVvSJpwxh2a+/Za116RXbFLu0qy02zWz3eLLAWWcszaBfJ72l1rEKkBfTawAtbee wVL6cmgWWTqr92ymTGk2rPcLFsbnN1HvutWJVtIaYCOwhjvc1kKXqP/Qg4WwVrwSv42l 5D3IMxT7CmvI9KsijCOy+DbuAFDDhaPf6gJcfN8zQSSm/XA5faN74V0Q6B2DoqzAzAXL FLrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782907115; x=1783511915; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Xi59yU2SD11/K7leMDXhuashplqtw/UHNq7fzaxoEQ4=; b=gUuEV32i7InfRlJt7buCBHoz0/tJDs78k9Yk6yApLFLvqGWYwtYt/08Pth8LCj5DJp 4OCgvmq23EKjCF/1nVQBqOH5IohPSG0WhW+ak6s64yDjEPyztoyDGZLlLyOyBuhRrkw4 7YUIZ76KDwofVtk5CmmtBYwBi+yFefOuS68LGKYOobnrGBtY5AsO1cU+hLssaBEIWLur OUpnTvL4Ge8hDR8Q7/hiIsA51HBs4Pyo3wGsu8T9sRAqN52Re+xIf+dg6xxLmbdUEFnQ CUps89Pbhp94+g/xQeHuc5/zCLLJoR1coUNqCR90CuWKqxHjyYcQkdDDtlIStg6BZ2po MxKQ== X-Gm-Message-State: AOJu0YxWbmY/G2E90SoujsTLW76swrnuX+dDlkHD4qDowLld2jKA4LN4 fnx79vS1AgXo7CeWp2g6MfazBz9JO+uSOeQjlrASoLlg2q6X5VwXsE0C+4h1sw== X-Gm-Gg: AfdE7cncSHf6kPVUh9XHOhUooOZx3w1DBc2Qjs6coCD2iy3zYyu22jX4f1ajchitXms mmll77Mokb/9KLQrTmlWezGfkvfP5aFQxLYlaAEYGNj+nIcVs/MbGaYXW1evtzdLGKk+51fZB1m YZ5Utd6tWN0njHxHOeEfIjaYiYDVO+Z1CT3y2mU8a4yZpq/Lw1tYICix7ZsQV/JBJ1lFxjAJvs6 RbexzgRt35xK39QP3D7aIkHdMsQ8u8OnsbCnXotqAJ7Gw1xKFjKMeO/JN4h5KOTblog8sOPUOnU gd+Aw5osx99bTgn/4wIzb6Klv3hc6M8I6WEd0NLtC1QlgawqjZSgAFWmVBlWwPJWymiMhwah7cr a0CzlkDLo4C2wxyUw3yJsNRsu1MdiIwSyKuZRAakpG578E5n+rC0vyDkUUkXn5z2maruMRRz3du Wx05+IdZhPbD75Lred+v2379CKds7dnNjY5GJp8rNyXp5HzTSU4V0J68kVuLGlP9Y= X-Received: by 2002:a05:6000:604:b0:460:70ae:f1af with SMTP id ffacd0b85a97d-47757e57d4emr2284899f8f.27.1782907115368; Wed, 01 Jul 2026 04:58:35 -0700 (PDT) Received: from [192.168.5.15] (cust18-dsl93-89-130.idnet.net. [93.89.130.18]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4756636cf98sm12680161f8f.22.2026.07.01.04.58.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jul 2026 04:58:35 -0700 (PDT) From: Alex Kiernan Date: Wed, 01 Jul 2026 12:58:12 +0100 Subject: [PATCH 2/3] tune-cortexa32: enable Thumb-2 and fix AArch32 crypto FPU selection MIME-Version: 1.0 Message-Id: <20260701-tune-a32-v1-2-a43f28b1d7a4@gmail.com> References: <20260701-tune-a32-v1-0-a43f28b1d7a4@gmail.com> In-Reply-To: <20260701-tune-a32-v1-0-a43f28b1d7a4@gmail.com> To: openembedded-core@lists.openembedded.org Cc: Alex Kiernan , Alex Kiernan X-Mailer: b4 0.15.2 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 01 Jul 2026 11:58:40 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/239979 Cortex-A32 is an AArch32-only ARMv8-A core, but its tune was configured as if it were a plain 64-bit-style tune: TUNE_FEATURES lacked both 'arm' and 'thumb', so userspace and the kernel were built as fixed-width ARM rather than Thumb-2, and the package architecture names did not match a Thumb-2 build. Add 'thumb' so the core is built as Thumb-2, and 'arm' so that feature-arm-thumb.inc honours a recipe's explicit ARM_INSTRUCTION_SET = "arm" instead of silently forcing it to thumb. Without 'arm', ARM_M_OPT is pinned to "thumb" and recipes that request ARM warn, e.g.: Recipe 'libmad' selects ARM_INSTRUCTION_SET to be 'arm', but tune configuration overrides it to 'thumb' On AArch32 the ARMv8 crypto extensions (AES/SHA) are part of the FPU, not just the -march ISA. The 'crypto' feature only appends '+crypto' to -march and leaves -mfpu at plain 'neon', so building the AES intrinsics (e.g. mbedtls aesce.c) fails: error: inlining failed in call to 'always_inline' 'vaesdq_u8': target specific option mismatch Select the crypto FPU by appending crypto-neon-fp-armv8 as the last word of TUNE_CCARGS_MFPU when both 'crypto' and 'neon' are active, mirroring the vfpv4+neon -> neon-vfpv4 idiom in feature-arm-neon.inc. Update PACKAGE_EXTRA_ARCHS to match the resulting package arches: cortexa32hf-neon becomes cortexa32t2hf-neon, and the crypto variant becomes cortexa32t2hf-neon plus cortexa32t2hf-crypto-neon-fp-armv8. AI-Generated: Claude Code (Claude Opus 4.8) Signed-off-by: Alex Kiernan Signed-off-by: Alex Kiernan --- meta/conf/machine/include/arm/armv8a/tune-cortexa32.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/meta/conf/machine/include/arm/armv8a/tune-cortexa32.inc b/meta/conf/machine/include/arm/armv8a/tune-cortexa32.inc index 0eb938a2403a..f8f876813302 100644 --- a/meta/conf/machine/include/arm/armv8a/tune-cortexa32.inc +++ b/meta/conf/machine/include/arm/armv8a/tune-cortexa32.inc @@ -5,14 +5,22 @@ TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa32', ' -mcpu=corte require conf/machine/include/arm/arch-armv8a.inc +# On AArch32 the ARMv8 crypto extensions (AES/SHA) live in the FPU, not just +# -march. OE-Core's 'crypto' feature only adds '+crypto' to -march, leaving the +# FPU at plain 'neon', so GCC refuses to inline the AES intrinsics used by e.g. +# mbedtls' aesce.c ("target specific option mismatch"). Select the crypto FPU by +# making it the last word of TUNE_CCARGS_MFPU - the same idiom OE-Core uses for +# the vfpv4+neon -> neon-vfpv4 combination in feature-arm-neon.inc. +TUNE_CCARGS_MFPU .= "${@bb.utils.contains('TUNE_FEATURES', [ 'crypto', 'neon' ], ' crypto-neon-fp-armv8', '', d)}" + # Little Endian base configs AVAILTUNES += "cortexa32 cortexa32-crypto" ARMPKGARCH:tune-cortexa32 = "cortexa32" ARMPKGARCH:tune-cortexa32-crypto = "cortexa32" # We do not want -march since -mcpu is added above to cover for it -TUNE_FEATURES:tune-cortexa32 = "armv8a cortexa32 crc callconvention-hard neon" +TUNE_FEATURES:tune-cortexa32 = "arm armv8a cortexa32 crc callconvention-hard neon thumb" TUNE_FEATURES:tune-cortexa32-crypto = "${TUNE_FEATURES:tune-cortexa32} crypto" -PACKAGE_EXTRA_ARCHS:tune-cortexa32 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa32 cortexa32hf-neon" -PACKAGE_EXTRA_ARCHS:tune-cortexa32-crypto = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc-crypto} cortexa32 cortexa32hf-neon cortexa32hf-neon-crypto" +PACKAGE_EXTRA_ARCHS:tune-cortexa32 = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc} cortexa32 cortexa32t2hf-neon" +PACKAGE_EXTRA_ARCHS:tune-cortexa32-crypto = "${PACKAGE_EXTRA_ARCHS:tune-armv8a-crc-crypto} cortexa32 cortexa32t2hf-neon cortexa32t2hf-crypto-neon-fp-armv8" BASE_LIB:tune-cortexa32 = "lib" BASE_LIB:tune-cortexa32-crypto = "lib" From patchwork Wed Jul 1 11:58:13 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Kiernan X-Patchwork-Id: 91499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC72AC43458 for ; Wed, 1 Jul 2026 11:58:40 +0000 (UTC) Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.groups.io with SMTP id smtpd.msgproc02-g2.43271.1782907117698373607 for ; Wed, 01 Jul 2026 04:58:38 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20251104 header.b=oV2FIwXl; spf=pass (domain: gmail.com, ip: 209.85.128.52, mailfrom: alex.kiernan@gmail.com) Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-493b27c7451so17397025e9.0 for ; Wed, 01 Jul 2026 04:58:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1782907116; x=1783511916; darn=lists.openembedded.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FYgOMk5gfSwcM6S9B3hRpmvSjppXFnUuJF8I+jCMLj8=; b=oV2FIwXl5qpVYYcqRu02PPVM2oNpozIOfk/pc7JhLpP/XXjLccGh7ymaG+xaaq2WXo CA76U24NOWj/PX3pTWx11YmQN61B5uL7j8D3bCAWo26C5PSJc6NyZEjLyweAXqrBhZmM OSlm0KNMBkf82Tm76BTBIHOdBqBKRAeLz6K5TLG16QNedpyJuZwS9jy4DSnpywujHtOP 34h69zywCsbbmU2GPQiksOqUQyTa5oej8mvKuVUAV3C14FshumQ2aip3bFpa3gBWFKKA qbkVqOBMmA8BEDDLlHCpNLo9P1mOgmu4OX5KJ2HGUgGCjz8q0otrIh7FOtvYpjP+7qFD Aurg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782907116; x=1783511916; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=FYgOMk5gfSwcM6S9B3hRpmvSjppXFnUuJF8I+jCMLj8=; b=Z4S9ty6iVxdS8S4mp/JpuFrLalSLnwsb1KIOMLkljTEBhC1HISa+8QrOffMslvIQiB vKHQUJysgHafOE6joqUOrkR2+GJCRFIzNEsD/yAQRBZtwUFJ5nP1dSq2w+V8hRokGQVy KNaaXd6MBeB0fc1/4E7gzEILmxVg2n9B8R+c0nG72j04n/we0TC3qp6bm20FRENbh5dd R37iZ0ru+cyZaHFmmkOq9DMEGtMd5hfdFn2iz7ADm8PtYn+wkyjoJuZF9pzT6+zKVssT EgsIjeDmrAeWo7Zd1+/+rXWgORdQTtkbZypa7DbjLvZq8SRLPF6HbiCP0Y6tpdXDPDO1 PJ3g== X-Gm-Message-State: AOJu0YzRUEaooUonqYKrF77m/hJ9ORV5RA18h6B9f7xX6O3caHjWSdPy 0GK3AlLtdycbHHrhcrYrlFY1m6TLk3gljYDCe6naevNRV4pyfxZevdOuDexxPw== X-Gm-Gg: AfdE7cmzTlm664tGo7Nyk0VuP2sKIyMOXL/tbNzL1c76Z8MXw4tELHCwrl55hBOU6z6 yxzy9fBM4Zui0+pnL46chSuzGsRQlQ347wstz8sovMEVFN3CD9dgIOpO2ZmCTQa4xwFBJFZHDda HGgoFRoIcx4Po9KLS0+bPSKBRJC9TGX94yCFc9jyuHu2rMXMN4/OB5IvcQ/AZHOSGXDR5zX+ZEH dXUsSBDknsR/unDvePzxr7QnACFS536i7DCuDm8GGNdVJ1Lzef0iWngYyiN6ByO/3m3JfAiizkw /fpGd5lFQl7dvtGt96+ILjf5r8Je5fwvl+aIlRQHUGOg4AEeN34y9UmjzIC1qjasy4XQsoIdrVs 4/TKifzG+AguARaJQiip7hDS7maQuf3jElIj+XNmAjDpN1PaUTZG88PNF4qk/p1BuSpSKxOCqrI agaaNGLWTnOO6t9bOyg/Nh6kMRUmRzp6sgHkWi6WAWFf2YR6G3K88BI9MMaH4PWdk= X-Received: by 2002:a05:600d:6454:20b0:493:a87f:52e5 with SMTP id 5b1f17b1804b1-493bc248efcmr62302525e9.10.1782907115886; Wed, 01 Jul 2026 04:58:35 -0700 (PDT) Received: from [192.168.5.15] (cust18-dsl93-89-130.idnet.net. [93.89.130.18]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4756636cf98sm12680161f8f.22.2026.07.01.04.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jul 2026 04:58:35 -0700 (PDT) From: Alex Kiernan Date: Wed, 01 Jul 2026 12:58:13 +0100 Subject: [PATCH 3/3] qemuarmv8a32: add QEMU machine for AArch32 ARMv8-A MIME-Version: 1.0 Message-Id: <20260701-tune-a32-v1-3-a43f28b1d7a4@gmail.com> References: <20260701-tune-a32-v1-0-a43f28b1d7a4@gmail.com> In-Reply-To: <20260701-tune-a32-v1-0-a43f28b1d7a4@gmail.com> To: openembedded-core@lists.openembedded.org Cc: Alex Kiernan , Alex Kiernan X-Mailer: b4 0.15.2 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 01 Jul 2026 11:58:40 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/239980 Add a QEMU machine for exercising an AArch32-only ARMv8-A target (Cortex-A32) under emulation, defaulting to the cortexa32-crypto tune. QEMU has no Cortex-A32 model, so it runs on the 'virt' machine with qemu-system-arm and -cpu max, which provides the ARMv8-A AArch32 feature set including the crypto extensions needed by the crypto tune. The kernel is built as a zImage and u-boot uses qemu_arm_defconfig, matching the other 32-bit ARM QEMU machines. Map KMACHINE to qemuarma15 so the existing linux-yocto BSP is reused, and add qemuarmv8a32 to linux-yocto's COMPATIBLE_MACHINE so a kernel can be built for it. AI-Generated: Claude Code (Claude Opus 4.8) Signed-off-by: Alex Kiernan Signed-off-by: Alex Kiernan --- meta/conf/machine/qemuarmv8a32.conf | 36 +++++++++++++++++++++++++++ meta/recipes-kernel/linux/linux-yocto_6.18.bb | 2 +- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/meta/conf/machine/qemuarmv8a32.conf b/meta/conf/machine/qemuarmv8a32.conf new file mode 100644 index 000000000000..8e49a56ae720 --- /dev/null +++ b/meta/conf/machine/qemuarmv8a32.conf @@ -0,0 +1,36 @@ +#@TYPE: Machine +#@NAME: QEMU ARMv8 AArch32 machine on Cortex-A32 +#@DESCRIPTION: Machine configuration for running an AArch32 system on QEMU + +DEFAULTTUNE = "cortexa32-crypto" + +require conf/machine/include/arm/armv8a/tune-cortexa32.inc +require conf/machine/include/qemu.inc + +KERNEL_IMAGETYPE = "zImage" + +PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot" +UBOOT_MACHINE ?= "qemu_arm_defconfig" + +SERIAL_CONSOLES ?= "115200;ttyAMA0 115200;hvc0" + +# For runqemu +QB_SYSTEM_NAME = "qemu-system-arm" +QB_MACHINE = "-machine virt" +# QEMU doesn't know about Cortex-A32 +QB_CPU = "-cpu max" +QB_SMP ?= "-smp 4" +QB_CPU_KVM = "-cpu host -machine gic-version=3" +# For graphics to work we need to define the VGA device as well as the necessary USB devices +QB_GRAPHICS = "-device virtio-gpu-pci" +QB_OPT_APPEND = "-device qemu-xhci -device usb-tablet -device usb-kbd" +# Virtio Networking support +QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no" +QB_NETWORK_DEVICE = "-device virtio-net-pci,netdev=net0,mac=@MAC@" +# Virtio block device +QB_ROOTFS_OPT = "-drive id=disk0,file=@ROOTFS@,if=none,format=raw -device virtio-blk-pci,drive=disk0" +# Virtio serial console +QB_SERIAL_OPT = "-device virtio-serial-pci -chardev null,id=virtcon -device virtconsole,chardev=virtcon" +QB_TCPSERIAL_OPT = "-device virtio-serial-pci -chardev socket,id=virtcon,port=@PORT@,host=127.0.0.1,nodelay=on -device virtconsole,chardev=virtcon" + +KMACHINE:qemuarmv8a32 = "qemuarma15" diff --git a/meta/recipes-kernel/linux/linux-yocto_6.18.bb b/meta/recipes-kernel/linux/linux-yocto_6.18.bb index 2b1298dedf9c..a818506bb6f3 100644 --- a/meta/recipes-kernel/linux/linux-yocto_6.18.bb +++ b/meta/recipes-kernel/linux/linux-yocto_6.18.bb @@ -52,7 +52,7 @@ KCONF_BSP_AUDIT_LEVEL = "1" KERNEL_DEVICETREE:qemuarmv5 = "arm/versatile-pb.dtb" -COMPATIBLE_MACHINE = "^(qemuarm|qemuarmv5|qemuarm64|qemux86|qemuppc|qemuppc64|qemumips|qemumips64|qemux86-64|qemuriscv64|qemuriscv32|qemuloongarch64)$" +COMPATIBLE_MACHINE = "^(qemuarm|qemuarmv5|qemuarmv8a32|qemuarm64|qemux86|qemuppc|qemuppc64|qemumips|qemumips64|qemux86-64|qemuriscv64|qemuriscv32|qemuloongarch64)$" # Functionality flags KERNEL_EXTRA_FEATURES ?= "features/netfilter/netfilter.scc"