From patchwork Mon Mar 30 10:43:11 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Safwat X-Patchwork-Id: 84825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4251FB3D1A for ; Mon, 30 Mar 2026 10:54:50 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.msgproc01-g2.48393.1774868086222113365 for ; Mon, 30 Mar 2026 03:54:46 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="dkim: body hash did not verify" header.i=@arm.com header.s=foss header.b=XQvo6LSz; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: michael.safwat@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B42FE2BCB; Mon, 30 Mar 2026 03:54:39 -0700 (PDT) Received: from e142473.cambridge.arm.com (e142473.arm.com [10.1.198.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 156643F915; Mon, 30 Mar 2026 03:54:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1774868085; bh=E+I34iTXD3RW86CzXx8NbNOwTrP7je02FaBCbtNVp5g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XQvo6LSzYYI3W9RK+N0okWnLYNQdmbXH1KujyaHyhMC61Cqtiv36ESKuChk31U0aI h0QVSPdoSGN+vx1ivzqitl0Q51a+aN+FYc+CLskNbnDc4bVOdMaOUFYv/hTzc3zVrB ZiNxdHIZ2+9CmYFt8lbAdNBZFmP4jmxJM8W6Hyeo= From: Michael Safwat To: meta-arm@lists.yoctoproject.org Cc: Frazer Carsley Subject: [PATCH 1/7] arm-bsp/u-boot:cs1k: Rework CONFIG_OF_UPSTREAM patch Date: Mon, 30 Mar 2026 11:43:11 +0100 Message-ID: <20260330105428.2580463-2-michael.safwat@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330105428.2580463-1-michael.safwat@arm.com> References: <20260330105428.2580463-1-michael.safwat@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 30 Mar 2026 10:54:50 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6981 From: Frazer Carsley Rework the patch that enables the OF_UPSTREAM config option to split off the extra device tree nodes into their own dtsi files, making it easier to combine them in different ways. The rest of the patches have changed only so that they can be applied cleanly. Signed-off-by: Frazer Carsley --- ...able-OF_UPSTREAM-device-tree-support.patch | 101 ++++++++++++------ ...-use-32-bit-cells-for-reserved-memor.patch | 8 +- ...e1000-Add-Cortex-A320-support-on-FVP.patch | 42 +++----- 3 files changed, 88 insertions(+), 63 deletions(-) diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0037-corstone1000-enable-OF_UPSTREAM-device-tree-support.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0037-corstone1000-enable-OF_UPSTREAM-device-tree-support.patch index 3776c986..a86b791a 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0037-corstone1000-enable-OF_UPSTREAM-device-tree-support.patch +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0037-corstone1000-enable-OF_UPSTREAM-device-tree-support.patch @@ -1,4 +1,4 @@ -From d7500d2733efc8f872bd4be60b31176eec27b5d0 Mon Sep 17 00:00:00 2001 +From e070ae0f02b10bfd482146a748095ca782f73039 Mon Sep 17 00:00:00 2001 From: Frazer Carsley Date: Mon, 19 Jan 2026 15:16:52 +0000 Subject: [PATCH] corstone1000: enable OF_UPSTREAM device tree support @@ -6,27 +6,32 @@ Subject: [PATCH] corstone1000: enable OF_UPSTREAM device tree support Enable OF_UPSTREAM option set for corstone1000 platform. Remove legacy u-boot corstone1000 device trees. Add device tree files for FVP and MPS3 platforms to add device -tree nodes that are missing from the upstream. +tree nodes that are missing from the upstream. These are done in a +modular way. Signed-off-by: Clement Faure Signed-off-by: Frazer Carsley Upstream-Status: Pending [Not submitted to upstream yet] --- - arch/arm/dts/Makefile | 3 - - arch/arm/dts/corstone1000-fvp-u-boot.dtsi | 15 ++ - arch/arm/dts/corstone1000-fvp.dts | 82 --------- - arch/arm/dts/corstone1000-mps3-u-boot.dtsi | 8 + - arch/arm/dts/corstone1000-mps3.dts | 32 ---- - arch/arm/dts/corstone1000-u-boot.dtsi | 39 +++++ - arch/arm/dts/corstone1000.dtsi | 194 --------------------- - board/armltd/corstone1000/corstone1000.c | 4 +- - configs/corstone1000_defconfig | 5 +- - 9 files changed, 68 insertions(+), 314 deletions(-) + arch/arm/dts/Makefile | 3 - + arch/arm/dts/corstone1000-extsys-u-boot.dtsi | 14 ++ + arch/arm/dts/corstone1000-fvp-u-boot.dtsi | 9 + + arch/arm/dts/corstone1000-fvp.dts | 82 -------- + arch/arm/dts/corstone1000-mps3-u-boot.dtsi | 9 + + arch/arm/dts/corstone1000-mps3.dts | 32 --- + arch/arm/dts/corstone1000-u-boot.dtsi | 30 +++ + arch/arm/dts/corstone1000-virtio-u-boot.dtsi | 13 ++ + arch/arm/dts/corstone1000.dtsi | 194 ------------------- + board/armltd/corstone1000/corstone1000.c | 4 +- + configs/corstone1000_defconfig | 5 +- + 11 files changed, 81 insertions(+), 314 deletions(-) + create mode 100644 arch/arm/dts/corstone1000-extsys-u-boot.dtsi create mode 100644 arch/arm/dts/corstone1000-fvp-u-boot.dtsi delete mode 100644 arch/arm/dts/corstone1000-fvp.dts create mode 100644 arch/arm/dts/corstone1000-mps3-u-boot.dtsi delete mode 100644 arch/arm/dts/corstone1000-mps3.dts create mode 100644 arch/arm/dts/corstone1000-u-boot.dtsi + create mode 100644 arch/arm/dts/corstone1000-virtio-u-boot.dtsi delete mode 100644 arch/arm/dts/corstone1000.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile @@ -43,27 +48,41 @@ index 7c8cf3a5a1d..89b3728379b 100644 dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb include $(srctree)/scripts/Makefile.dts +diff --git a/arch/arm/dts/corstone1000-extsys-u-boot.dtsi b/arch/arm/dts/corstone1000-extsys-u-boot.dtsi +new file mode 100644 +index 00000000000..074f45f0e69 +--- /dev/null ++++ b/arch/arm/dts/corstone1000-extsys-u-boot.dtsi +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: GPL-2.0 or MIT ++/* ++ * Copyright 2026 Arm Limited and/or its affiliates ++ * ++ */ ++ ++&{/soc} { ++ extsys0: remoteproc@1a010310 { ++ compatible = "arm,corstone1000-extsys"; ++ reg = <0x1a010310 0x4>, <0x1a010314 0x4>; ++ reg-names = "reset-control", "reset-status"; ++ firmware-name = "es_flashfw.elf"; ++ }; ++}; diff --git a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi new file mode 100644 -index 00000000000..20425fa0624 +index 00000000000..5cb7762fc1c --- /dev/null +++ b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi -@@ -0,0 +1,15 @@ +@@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* -+ * Copyright 2025 Arm Limited and/or its affiliates ++ * Copyright 2026 Arm Limited and/or its affiliates + * + */ + +#include "corstone1000-u-boot.dtsi" -+ -+/ { -+ virtio: virtio-net@40400000 { -+ compatible = "virtio,mmio"; -+ reg = <0x40400000 0x10000>; -+ interrupts = <145>; -+ }; -+}; ++#include "corstone1000-extsys-u-boot.dtsi" ++#include "corstone1000-virtio-u-boot.dtsi" diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts deleted file mode 100644 index cd8a132271e..00000000000 @@ -154,17 +173,18 @@ index cd8a132271e..00000000000 - diff --git a/arch/arm/dts/corstone1000-mps3-u-boot.dtsi b/arch/arm/dts/corstone1000-mps3-u-boot.dtsi new file mode 100644 -index 00000000000..9ab744d8d20 +index 00000000000..0d9d6c5e6e1 --- /dev/null +++ b/arch/arm/dts/corstone1000-mps3-u-boot.dtsi -@@ -0,0 +1,8 @@ +@@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* -+ * Copyright 2025 Arm Limited and/or its affiliates ++ * Copyright 2026 Arm Limited and/or its affiliates + * + */ + +#include "corstone1000-u-boot.dtsi" ++#include "corstone1000-extsys-u-boot.dtsi" + diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts deleted file mode 100644 @@ -206,13 +226,13 @@ index e3146747c2d..00000000000 -}; diff --git a/arch/arm/dts/corstone1000-u-boot.dtsi b/arch/arm/dts/corstone1000-u-boot.dtsi new file mode 100644 -index 00000000000..95dd277d4cc +index 00000000000..a75bc7016aa --- /dev/null +++ b/arch/arm/dts/corstone1000-u-boot.dtsi -@@ -0,0 +1,39 @@ +@@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* -+ * Copyright 2025 Arm Limited and/or its affiliates ++ * Copyright 2025-2026 Arm Limited and/or its affiliates + * + */ + @@ -240,13 +260,23 @@ index 00000000000..95dd277d4cc + }; + }; +}; +diff --git a/arch/arm/dts/corstone1000-virtio-u-boot.dtsi b/arch/arm/dts/corstone1000-virtio-u-boot.dtsi +new file mode 100644 +index 00000000000..89ff06a51f8 +--- /dev/null ++++ b/arch/arm/dts/corstone1000-virtio-u-boot.dtsi +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: GPL-2.0 or MIT ++/* ++ * Copyright 2026 Arm Limited and/or its affiliates ++ * ++ */ + -+&{/soc} { -+ extsys0: remoteproc@1a010310 { -+ compatible = "arm,corstone1000-extsys"; -+ reg = <0x1a010310 0x4>, <0x1a010314 0x4>; -+ reg-names = "reset-control", "reset-status"; -+ firmware-name = "es_flashfw.elf"; ++/ { ++ virtio: virtio-net@40400000 { ++ compatible = "virtio,mmio"; ++ reg = <0x40400000 0x10000>; ++ interrupts = <145>; + }; +}; diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi @@ -494,3 +524,4 @@ index 450d69762ab..350607892fa 100644 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0038-corstone1000-dts-use-32-bit-cells-for-reserved-memor.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0038-corstone1000-dts-use-32-bit-cells-for-reserved-memor.patch index c74c0311..743b2547 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0038-corstone1000-dts-use-32-bit-cells-for-reserved-memor.patch +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0038-corstone1000-dts-use-32-bit-cells-for-reserved-memor.patch @@ -1,7 +1,8 @@ -From b457d1a3665dbac8499ccf8d0726a30e4d0554da Mon Sep 17 00:00:00 2001 +From df01111a866a37fcf875b3c2e2394414d27c89da Mon Sep 17 00:00:00 2001 From: Harsimran Singh Tungal Date: Wed, 24 Sep 2025 13:42:25 +0000 -Subject: [PATCH] corstone1000: dts: use 32-bit cells for /reserved-memory node +Subject: [PATCH] corstone1000: dts: use 32-bit cells for + /reserved-memory node Switch the *reserved-memory* node from two-cell (64-bit) encoding to one-cell (32-bit) encoding and adjust the `reg` property accordingly @@ -14,7 +15,7 @@ Signed-off-by: Harsimran Singh Tungal 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/corstone1000-u-boot.dtsi b/arch/arm/dts/corstone1000-u-boot.dtsi -index 95dd277d4cc..b29ac74217e 100644 +index a75bc7016aa..4ea6f1d9724 100644 --- a/arch/arm/dts/corstone1000-u-boot.dtsi +++ b/arch/arm/dts/corstone1000-u-boot.dtsi @@ -18,12 +18,12 @@ @@ -33,3 +34,4 @@ index 95dd277d4cc..b29ac74217e 100644 no-map; }; }; + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch index af4215a4..be0367b3 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch @@ -1,6 +1,6 @@ -From 46fd90a19c9a2c04fb958badb19e148b08f559c8 Mon Sep 17 00:00:00 2001 +From ef9306fde5247ccd8fecec5f886f52426c01af61 Mon Sep 17 00:00:00 2001 From: Frazer Carsley -Date: Fri, 15 Aug 2025 09:22:26 +0100 +Date: Wed, 25 Feb 2026 14:08:07 +0000 Subject: [PATCH] corstone1000: Add Cortex-A320 support on FVP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -49,20 +49,20 @@ Upstream-Status: Submitted (https://lore.kernel.org/all/20251127154752.589691-1- Signed-off-by: Frazer Carsley Signed-off-by: Harsimran Singh Tungal --- - arch/arm/dts/corstone1000-fvp-u-boot.dtsi | 39 ++++++++++++ - arch/arm/dts/corstone1000-u-boot.dtsi | 76 +++++++++++++++++++++++ + arch/arm/dts/corstone1000-fvp-u-boot.dtsi | 38 +++++++++++ + arch/arm/dts/corstone1000-u-boot.dtsi | 79 +++++++++++++++++++++++ arch/arm/include/asm/armv8/cpu.h | 1 + board/armltd/corstone1000/Kconfig | 8 +++ - 4 files changed, 124 insertions(+) + 4 files changed, 126 insertions(+) diff --git a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi -index 20425fa0624..0539e6c092a 100644 +index 5cb7762fc1c..7ad4ca9e070 100644 --- a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi +++ b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi -@@ -13,3 +13,42 @@ - interrupts = <145>; - }; - }; +@@ -7,3 +7,41 @@ + #include "corstone1000-u-boot.dtsi" + #include "corstone1000-extsys-u-boot.dtsi" + #include "corstone1000-virtio-u-boot.dtsi" + +&{/cpus} { + cpu1: cpu@1 { @@ -101,15 +101,15 @@ index 20425fa0624..0539e6c092a 100644 + next-level-cache = <&L2_0>; + }; +}; -+ diff --git a/arch/arm/dts/corstone1000-u-boot.dtsi b/arch/arm/dts/corstone1000-u-boot.dtsi -index b29ac74217e..7f75eae48cc 100644 +index 4ea6f1d9724..fef56d1ec66 100644 --- a/arch/arm/dts/corstone1000-u-boot.dtsi +++ b/arch/arm/dts/corstone1000-u-boot.dtsi -@@ -29,6 +29,15 @@ +@@ -28,3 +28,82 @@ + }; }; }; - ++ +&{/cpus} { + cpu: cpu@0 { + device_type = "cpu"; @@ -118,14 +118,6 @@ index b29ac74217e..7f75eae48cc 100644 + next-level-cache = <&L2_0>; + }; +}; -+ - &{/soc} { - extsys0: remoteproc@1a010310 { - compatible = "arm,corstone1000-extsys"; -@@ -37,3 +46,72 @@ - firmware-name = "es_flashfw.elf"; - }; - }; + +#ifdef CONFIG_ETHOS_U85 +&{/reserved-memory} { @@ -138,6 +130,7 @@ index b29ac74217e..7f75eae48cc 100644 + compatible = "shared-dma-pool"; + reg = <0xA0000000 0x02000000>; + no-map; ++ + }; +}; + @@ -196,7 +189,7 @@ index b29ac74217e..7f75eae48cc 100644 + }; +#endif diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h -index e906fdf1bf1..a361c1100b3 100644 +index e906fdf1bf1..4ef2ff07f7a 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -11,6 +11,7 @@ @@ -208,7 +201,7 @@ index e906fdf1bf1..a361c1100b3 100644 #define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig -index 709674d4cf7..3af29b2bae7 100644 +index 709674d4cf7..eea5c9b8972 100644 --- a/board/armltd/corstone1000/Kconfig +++ b/board/armltd/corstone1000/Kconfig @@ -9,4 +9,12 @@ config SYS_VENDOR @@ -224,4 +217,3 @@ index 709674d4cf7..3af29b2bae7 100644 + default n + endif - From patchwork Mon Mar 30 10:43:12 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Safwat X-Patchwork-Id: 84826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9D71FC97E2 for ; Mon, 30 Mar 2026 10:54:51 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.msgproc01-g2.48394.1774868086892437192 for ; Mon, 30 Mar 2026 03:54:47 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="dkim: body hash did not verify" header.i=@arm.com header.s=foss header.b=Ou0D6+kT; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: michael.safwat@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7D05F1E8D; Mon, 30 Mar 2026 03:54:40 -0700 (PDT) Received: from e142473.cambridge.arm.com (e142473.arm.com [10.1.198.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D4F7C3F915; Mon, 30 Mar 2026 03:54:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1774868086; bh=dZ43gO/FUm9b6HGZyqPteo1xuzjGmQAGxEis1YDm1To=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ou0D6+kTYlBAyGVrrfboJ2RgwT7nmUgNkims4kHgsmpeNuq9MoEOsLTjRnsuqeu6B B3+2rRaXDyyLMfjHR9PQizfXdmAQaUeGF9wTphbOsma6WtOPsUp2t8BjLdX0WG9pZN pxd6LRkvHg7Y0ez1KdPQBgcAAjCIDo5Do5/GmI1k= From: Michael Safwat To: meta-arm@lists.yoctoproject.org Cc: Frazer Carsley Subject: [PATCH 2/7] arm-bsp/u-boot:cs1k: Split Cortex-a320 device tree Date: Mon, 30 Mar 2026 11:43:12 +0100 Message-ID: <20260330105428.2580463-3-michael.safwat@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330105428.2580463-1-michael.safwat@arm.com> References: <20260330105428.2580463-1-michael.safwat@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 30 Mar 2026 10:54:51 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6983 From: Frazer Carsley The U-Boot maintainers rejected the previous patch [1] for two primary reasons: 1. The Cortex-A320 changes should be considered a separate platform 2. The NPU node bindings do not match those in the Linux kernel The former is handled by this commit. The latter point has not been resolved, hence marking the newly added patch as Inappropriate. This is simply the first step in resolving the comments. [1] https://lore.kernel.org/all/20251127154752.589691-1-frazer.carsley@arm.com Signed-off-by: Frazer Carsley --- .../u-boot/u-boot-corstone1000.inc | 12 +- ...e1000-Add-Cortex-A320-support-on-FVP.patch | 219 ------- ...-a320-Add-Corstone1000-board-variant.patch | 594 ++++++++++++++++++ .../u-boot/corstone1000/corstone1000-a320.cfg | 2 - 4 files changed, 599 insertions(+), 228 deletions(-) delete mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-a320-Add-Corstone1000-board-variant.patch delete mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/corstone1000-a320.cfg diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot-corstone1000.inc b/meta-arm-bsp/recipes-bsp/u-boot/u-boot-corstone1000.inc index 4edd8f18..9660fbc6 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot-corstone1000.inc @@ -3,10 +3,13 @@ DEPENDS:append = " openssl-native efitools-native" CORSTONE1000_DEVICE_TREE:corstone1000-mps3 = "arm/corstone1000-mps3" CORSTONE1000_DEVICE_TREE:corstone1000-fvp = "arm/corstone1000-fvp" +CORSTONE1000_DEVICE_TREE:cortexa320 = "corstone1000-a320-fvp" EXTRA_OEMAKE:append = ' DEVICE_TREE=${CORSTONE1000_DEVICE_TREE}' +CORSTONE1000_DEFCONFIG = "corstone1000_defconfig" +CORSTONE1000_DEFCONFIG:cortexa320 = "corstone1000-a320_defconfig" UBOOT_CONFIG ??= "EFI" -UBOOT_CONFIG[EFI] = "corstone1000_defconfig" +UBOOT_CONFIG[EFI] = "${CORSTONE1000_DEFCONFIG}" UBOOT_ENTRYPOINT = "0x80000000" UBOOT_LOADADDRESS = "0x80000000" UBOOT_BOOTARGS = "${LINUX_KERNEL_ARGS} loglevel=9" @@ -75,12 +78,7 @@ SRC_URI:append = " \ # Add Cortex-a320 support SRC_URI:append = " \ - file://0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch \ -" - -# Add Cortex-a320 specific configurations -SRC_URI:append:cortexa320 = " \ - file://corstone1000-a320.cfg \ + file://0039-corstone1000-a320-Add-Corstone1000-board-variant.patch \ " uboot_configure_config:append() { diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch deleted file mode 100644 index be0367b3..00000000 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch +++ /dev/null @@ -1,219 +0,0 @@ -From ef9306fde5247ccd8fecec5f886f52426c01af61 Mon Sep 17 00:00:00 2001 -From: Frazer Carsley -Date: Wed, 25 Feb 2026 14:08:07 +0000 -Subject: [PATCH] corstone1000: Add Cortex-A320 support on FVP -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enable Cortex-A320 support on the Corstone-1000 platform -(including FVP) and update the device tree to support the integrated -Ethos-U85 NPU and GIC-700 interrupt controller. These updates make -the platform fully compatible with Cortex-A320 while retaining -backward compatibility with Cortex-A35 and GIC-400. - -**Cortex-A320 enablement** - -* Extend Corstone-1000 compatibility list to include `cortex-a320`. -* Ensure build and device-tree logic support both Cortex-A35 and - Cortex-A320 configurations. - -**Ethos-U85 integration** - -* Add `/ethosu@1a050000` node describing the NPU register block at - `0x1A050000`. -* Introduce associated reserved memory regions: - * `ethosu_sram@02400000`: 2 MiB on-chip SRAM (`no-map`). - * `ethosu_reserved@A0000000`: 32 MiB DDR carve-out - (`shared-dma-pool`). -* Connect memory regions through `memory-region` and `sram` phandles. -* Add `dma-ranges`, interrupt spec, `region-cfgs`, `cs-region`, and - `ethosu-mem-config` for full driver support. -* Enable the NPU node conditionally via `CONFIG_ETHOS_U85`. - -**GIC-700 support** - -* Introduce `CONFIG_GIC_700` to toggle between GIC-400 and - GIC-700. -* Add full GICv3 node guarded by `#ifdef CONFIG_GIC_700`. -* Adjust `cpu@1..3` `reg` values to `0x100/0x200/0x300` under - GIC-700 (keep `0x1/0x2/0x3` for GIC-400). -* Update Ethos-U85 interrupt assignment to **SPI 16** to align with - the new interrupt map. - -These updates align the Corstone-1000 platform with Arm’s latest -Cortex-A320 and Ethos-U85 configurations and ensure proper interrupt -and memory mapping for both secure and non-secure domains. - -Upstream-Status: Submitted (https://lore.kernel.org/all/20251127154752.589691-1-frazer.carsley@arm.com/) -Signed-off-by: Frazer Carsley -Signed-off-by: Harsimran Singh Tungal ---- - arch/arm/dts/corstone1000-fvp-u-boot.dtsi | 38 +++++++++++ - arch/arm/dts/corstone1000-u-boot.dtsi | 79 +++++++++++++++++++++++ - arch/arm/include/asm/armv8/cpu.h | 1 + - board/armltd/corstone1000/Kconfig | 8 +++ - 4 files changed, 126 insertions(+) - -diff --git a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi -index 5cb7762fc1c..7ad4ca9e070 100644 ---- a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi -+++ b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi -@@ -7,3 +7,41 @@ - #include "corstone1000-u-boot.dtsi" - #include "corstone1000-extsys-u-boot.dtsi" - #include "corstone1000-virtio-u-boot.dtsi" -+ -+&{/cpus} { -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a35","arm,cortex-a320"; -+#ifdef CONFIG_GIC_700 -+ reg = <0x100>; -+#else -+ reg = <0x1>; -+#endif -+ enable-method = "psci"; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a35","arm,cortex-a320"; -+#ifdef CONFIG_GIC_700 -+ reg = <0x200>; -+#else -+ reg = <0x2>; -+#endif -+ enable-method = "psci"; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a35","arm,cortex-a320"; -+#ifdef CONFIG_GIC_700 -+ reg = <0x300>; -+#else -+ reg = <0x3>; -+#endif -+ enable-method = "psci"; -+ next-level-cache = <&L2_0>; -+ }; -+}; -diff --git a/arch/arm/dts/corstone1000-u-boot.dtsi b/arch/arm/dts/corstone1000-u-boot.dtsi -index 4ea6f1d9724..fef56d1ec66 100644 ---- a/arch/arm/dts/corstone1000-u-boot.dtsi -+++ b/arch/arm/dts/corstone1000-u-boot.dtsi -@@ -28,3 +28,82 @@ - }; - }; - }; -+ -+&{/cpus} { -+ cpu: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a35","arm,cortex-a320"; -+ reg = <0>; -+ next-level-cache = <&L2_0>; -+ }; -+}; -+ -+#ifdef CONFIG_ETHOS_U85 -+&{/reserved-memory} { -+ ethosu_sram: ethosu_sram@02400000 { -+ reg = <0x02400000 0x200000>; -+ no-map; -+ }; -+ -+ ethosu_reserved: ethosu_reserved@A0000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0xA0000000 0x02000000>; -+ no-map; -+ -+ }; -+}; -+ -+/ { -+ ethosu: ethosu@1A050000 { -+ compatible = "arm,ethosu-direct"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ // Base address and size of NPU registers -+ reg = <0x1A050000 0x4000>; -+ -+ memory-region = <ðosu_reserved>; -+ sram = <ðosu_sram>; -+ -+ // Address mappings to translate between bus addresses (NPU) and physical host CPU addresses -+ dma-ranges = <0x02400000 0x02400000 0x200000>, -+ <0xA0000000 0xA0000000 0x02000000>; -+ -+ interrupts = <0 16 4>; -+ interrupt-names = "irq"; -+ -+ // Memory region configuration -+ region-cfgs = <3 3 0 3 3 3 3 3>; -+ -+ // Memory regions used for the command stream -+ cs-region = <2>; -+ -+ // Memory interface configuration for Ethos-U85 -+ ethosu_mem_config { -+ compatible = "arm,ethosu-mem-config"; -+ // -+ sram = <0 64 32>; -+ ext = <1 64 32>; -+ // -+ configs = <0 0 0>, -+ <0 0 0>, -+ <0 0 1>, -+ <0 0 1>; -+ }; -+ }; -+}; -+#endif -+ -+#ifdef CONFIG_GIC_700 -+gic: &{/interrupt-controller@1c000000} { -+ compatible = "arm,gic-v3"; -+ #interrupt-cells = <3>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ interrupt-controller; -+ reg = <0x1c000000 0x00010000>, -+ <0x1c040000 0x00100000>; -+ interrupts = ; -+ }; -+#endif -diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h -index e906fdf1bf1..4ef2ff07f7a 100644 ---- a/arch/arm/include/asm/armv8/cpu.h -+++ b/arch/arm/include/asm/armv8/cpu.h -@@ -11,6 +11,7 @@ - #define MIDR_PARTNUM_CORTEX_A73 0xD09 - #define MIDR_PARTNUM_CORTEX_A75 0xD0A - #define MIDR_PARTNUM_CORTEX_A76 0xD0B -+#define MIDR_PARTNUM_CORTEX_A320 0xD8F - #define MIDR_PARTNUM_SHIFT 0x4 - #define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) - -diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig -index 709674d4cf7..eea5c9b8972 100644 ---- a/board/armltd/corstone1000/Kconfig -+++ b/board/armltd/corstone1000/Kconfig -@@ -9,4 +9,12 @@ config SYS_VENDOR - config SYS_CONFIG_NAME - default "corstone1000" - -+config ETHOS_U85 -+ bool "Enable Arm Ethos-U85 NPU support" -+ default n -+ -+config GIC_700 -+ bool "Enable GIC-700 support" -+ default n -+ - endif diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-a320-Add-Corstone1000-board-variant.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-a320-Add-Corstone1000-board-variant.patch new file mode 100644 index 00000000..d370021b --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-a320-Add-Corstone1000-board-variant.patch @@ -0,0 +1,594 @@ +From 9f95097d9b2d9b1360b5c105161509ea9a5b198d Mon Sep 17 00:00:00 2001 +From: Frazer Carsley +Date: Wed, 25 Feb 2026 14:28:08 +0000 +Subject: [PATCH] corstone1000-a320: Add Corstone1000 board variant +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enable Cortex-A320 support on the Corstone-1000 platform +(including FVP) and support for the integrated Ethos-U85 NPU and GIC-700 +interrupt controller by way of a new device-tree. These updates make the +platform fully compatible with Cortex-A320 while retaining backward +compatibility with Cortex-A35 and GIC-400. + +**Cortex-A320 enablement** + +* Extend Corstone-1000 compatibility list to include `cortex-a320`. +* Add new device-tree to support Cortex-A320 configurations, retaining + existing board support code. + +**Ethos-U85 integration** + +* Add `/ethosu@1a050000` node describing the NPU register block at + `0x1A050000`. +* Introduce associated reserved memory regions: + * `ethosu_sram@02400000`: 2 MiB on-chip SRAM (`no-map`). + * `ethosu_reserved@A0000000`: 32 MiB DDR carve-out + (`shared-dma-pool`). +* Connect memory regions through `memory-region` and `sram` phandles. +* Add `dma-ranges`, interrupt spec, `region-cfgs`, `cs-region`, and + `ethosu-mem-config` for full driver support. +**GIC-700 support** + +* Add full GICv3 node. +* Map `cpu@1..3` `reg` values to `0x100/0x200/0x300` under + GIC-700 +* Update Ethos-U85 interrupt assignment to **SPI 16** to align with + the new interrupt map. + +These updates align the Corstone-1000 platform with Arm’s latest +Cortex-A320 and Ethos-U85 configurations and ensure proper interrupt +and memory mapping for both secure and non-secure domains. + +Upstream-Status: Inappropriate [Unsupported ethosu device-tree nodes, denied by maintainers (https://lore.kernel.org/all/20251127154752.589691-1-frazer.carsley@arm.com/)] +Signed-off-by: Frazer Carsley +Signed-off-by: Harsimran Singh Tungal +--- + arch/arm/Kconfig | 1 + + arch/arm/dts/corstone1000-a320-fvp.dts | 51 ++++ + arch/arm/dts/corstone1000-a320.dtsi | 237 ++++++++++++++++++ + arch/arm/include/asm/armv8/cpu.h | 3 + + board/armltd/corstone1000-a320/Kconfig | 12 + + board/armltd/corstone1000-a320/MAINTAINERS | 7 + + board/armltd/corstone1000/corstone1000.c | 6 +- + configs/corstone1000-a320_defconfig | 89 +++++++ + .../arm/arm,corstone1000-a320.yml | 31 +++ + 9 files changed, 434 insertions(+), 3 deletions(-) + create mode 100644 arch/arm/dts/corstone1000-a320-fvp.dts + create mode 100644 arch/arm/dts/corstone1000-a320.dtsi + create mode 100644 board/armltd/corstone1000-a320/Kconfig + create mode 100644 board/armltd/corstone1000-a320/MAINTAINERS + create mode 100644 configs/corstone1000-a320_defconfig + create mode 100644 doc/device-tree-bindings/arm/arm,corstone1000-a320.yml + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 625d2e995d2..aacc39fa60c 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -2405,6 +2405,7 @@ source "arch/arm/mach-npcm/Kconfig" + + source "board/armltd/total_compute/Kconfig" + source "board/armltd/corstone1000/Kconfig" ++source "board/armltd/corstone1000-a320/Kconfig" + source "board/bosch/shc/Kconfig" + source "board/bosch/guardian/Kconfig" + source "board/Marvell/octeontx/Kconfig" +diff --git a/arch/arm/dts/corstone1000-a320-fvp.dts b/arch/arm/dts/corstone1000-a320-fvp.dts +new file mode 100644 +index 00000000000..c01c629e0ca +--- /dev/null ++++ b/arch/arm/dts/corstone1000-a320-fvp.dts +@@ -0,0 +1,51 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (c) 2026, Arm Limited. All rights reserved. ++ * ++ */ ++ ++/dts-v1/; ++ ++#include "corstone1000-a320.dtsi" ++#include "corstone1000-virtio-u-boot.dtsi" ++ ++/ { ++ model = "ARM Corstone1000-A320 FVP (Fixed Virtual Platform)"; ++ compatible = "arm,corstone1000-a320-fvp"; ++ ++ smsc: ethernet@4010000 { ++ compatible = "smsc,lan91c111"; ++ reg = <0x40100000 0x10000>; ++ phy-mode = "mii"; ++ interrupts = ; ++ reg-io-width = <2>; ++ }; ++ ++ vmmc_v3_3d: regulator-vmmc { ++ compatible = "regulator-fixed"; ++ regulator-name = "vmmc_supply"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ sdmmc0: mmc@40300000 { ++ compatible = "arm,pl18x", "arm,primecell"; ++ reg = <0x40300000 0x1000>; ++ interrupts = ; ++ max-frequency = <12000000>; ++ vmmc-supply = <&vmmc_v3_3d>; ++ clocks = <&smbclk>, <&refclk100mhz>; ++ clock-names = "smclk", "apb_pclk"; ++ }; ++ ++ sdmmc1: mmc@50000000 { ++ compatible = "arm,pl18x", "arm,primecell"; ++ reg = <0x50000000 0x10000>; ++ interrupts = ; ++ max-frequency = <12000000>; ++ vmmc-supply = <&vmmc_v3_3d>; ++ clocks = <&smbclk>, <&refclk100mhz>; ++ clock-names = "smclk", "apb_pclk"; ++ }; ++}; +diff --git a/arch/arm/dts/corstone1000-a320.dtsi b/arch/arm/dts/corstone1000-a320.dtsi +new file mode 100644 +index 00000000000..28424db77bb +--- /dev/null ++++ b/arch/arm/dts/corstone1000-a320.dtsi +@@ -0,0 +1,237 @@ ++// SPDX-License-Identifier: GPL-2.0 or MIT ++/* ++ * Copyright 2026, Arm Limited and/or its affiliates ++ * ++ */ ++ ++#include ++ ++#include "corstone1000-u-boot.dtsi" ++ ++/ { ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ L2: l2-cache { ++ compatible = "cache"; ++ cache-unified; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-line-size = <64>; ++ cache-sets = <1024>; ++ }; ++ ++ cpu: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a320"; ++ reg = <0>; ++ enable-method = "psci"; ++ next-level-cache = <&L2>; ++ }; ++ ++ cpu1: cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a320"; ++ reg = <0x100>; ++ enable-method = "psci"; ++ next-level-cache = <&L2>; ++ }; ++ ++ cpu2: cpu@200 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a320"; ++ reg = <0x200>; ++ enable-method = "psci"; ++ next-level-cache = <&L2>; ++ }; ++ ++ cpu3: cpu@300 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a320"; ++ reg = <0x300>; ++ enable-method = "psci"; ++ next-level-cache = <&L2>; ++ }; ++ }; ++ ++ gic: interrupt-controller@1c000000 { ++ compatible = "arm,gic-v3"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ interrupt-controller; ++ reg = <0x1c000000 0x00010000>, ++ <0x1c040000 0x00100000>; ++ interrupts = ; ++ }; ++ ++ memory@88200000 { ++ device_type = "memory"; ++ reg = <0x88200000 0x77e00000>; ++ }; ++ ++ refclk100mhz: clock-100000000 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <100000000>; ++ clock-output-names = "apb_pclk"; ++ }; ++ ++ smbclk: clock-48000000 { ++ /* Reference 24MHz clock x 2 */ ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <48000000>; ++ clock-output-names = "smclk"; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ uartclk: clock-50000000 { ++ /* UART clock - 50MHz */ ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <50000000>; ++ clock-output-names = "uartclk"; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0", "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ ethosu: ethosu@1A050000 { ++ compatible = "arm,ethosu-direct"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ // Base address and size of NPU registers ++ reg = <0x1A050000 0x4000>; ++ ++ memory-region = <ðosu_reserved>; ++ sram = <ðosu_sram>; ++ ++ // Address mappings to translate between bus addresses (NPU) and physical host CPU addresses ++ dma-ranges = <0x02400000 0x02400000 0x200000>, ++ <0xA0000000 0xA0000000 0x02000000>; ++ ++ interrupts = <0 16 4>; ++ interrupt-names = "irq"; ++ ++ // Memory region configuration ++ region-cfgs = <3 3 0 3 3 3 3 3>; ++ ++ // Memory regions used for the command stream ++ cs-region = <2>; ++ ++ // Memory interface configuration for Ethos-U85 ++ ethosu_mem_config { ++ compatible = "arm,ethosu-mem-config"; ++ // ++ sram = <0 64 32>; ++ ext = <1 64 32>; ++ // ++ configs = <0 0 0>, ++ <0 0 0>, ++ <0 0 1>, ++ <0 0 1>; ++ }; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-parent = <&gic>; ++ ranges; ++ ++ timer@1a220000 { ++ compatible = "arm,armv7-timer-mem"; ++ reg = <0x1a220000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ frame@1a230000 { ++ frame-number = <0>; ++ interrupts = ; ++ reg = <0x1a230000 0x1000>; ++ }; ++ }; ++ ++ uart0: serial@1a510000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x1a510000 0x1000>; ++ interrupts = ; ++ clocks = <&uartclk>, <&refclk100mhz>; ++ clock-names = "uartclk", "apb_pclk"; ++ }; ++ ++ uart1: serial@1a520000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x1a520000 0x1000>; ++ interrupts = ; ++ clocks = <&uartclk>, <&refclk100mhz>; ++ clock-names = "uartclk", "apb_pclk"; ++ }; ++ ++ mhu_hse1: mailbox@1b820000 { ++ compatible = "arm,mhuv2-tx", "arm,primecell"; ++ reg = <0x1b820000 0x1000>; ++ clocks = <&refclk100mhz>; ++ clock-names = "apb_pclk"; ++ interrupts = ; ++ #mbox-cells = <2>; ++ arm,mhuv2-protocols = <0 0>; ++ secure-status = "okay"; /* secure-world-only */ ++ status = "disabled"; ++ }; ++ ++ mhu_seh1: mailbox@1b830000 { ++ compatible = "arm,mhuv2-rx", "arm,primecell"; ++ reg = <0x1b830000 0x1000>; ++ clocks = <&refclk100mhz>; ++ clock-names = "apb_pclk"; ++ interrupts = ; ++ #mbox-cells = <2>; ++ arm,mhuv2-protocols = <0 0>; ++ secure-status = "okay"; /* secure-world-only */ ++ status = "disabled"; ++ }; ++ }; ++}; ++ ++&{/reserved-memory} { ++ ethosu_sram: ethosu_sram@02400000 { ++ reg = <0x02400000 0x200000>; ++ no-map; ++ }; ++ ++ ethosu_reserved: ethosu_reserved@A0000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0xA0000000 0x02000000>; ++ no-map; ++ }; ++}; ++ +diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h +index e906fdf1bf1..1ae679f7119 100644 +--- a/arch/arm/include/asm/armv8/cpu.h ++++ b/arch/arm/include/asm/armv8/cpu.h +@@ -1,6 +1,7 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ + /* + * Copyright 2018 NXP ++ * (C) Copyright 2026 Arm Limited + */ + + #define MIDR_PARTNUM_CORTEX_A35 0xD04 +@@ -11,6 +12,7 @@ + #define MIDR_PARTNUM_CORTEX_A73 0xD09 + #define MIDR_PARTNUM_CORTEX_A75 0xD0A + #define MIDR_PARTNUM_CORTEX_A76 0xD0B ++#define MIDR_PARTNUM_CORTEX_A320 0xD8F + #define MIDR_PARTNUM_SHIFT 0x4 + #define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) + +@@ -40,3 +42,4 @@ is_cortex_a(72) + is_cortex_a(73) + is_cortex_a(75) + is_cortex_a(76) ++is_cortex_a(320) +diff --git a/board/armltd/corstone1000-a320/Kconfig b/board/armltd/corstone1000-a320/Kconfig +new file mode 100644 +index 00000000000..607e5f6689b +--- /dev/null ++++ b/board/armltd/corstone1000-a320/Kconfig +@@ -0,0 +1,12 @@ ++if TARGET_CORSTONE1000-A320 ++ ++config SYS_BOARD ++ default "corstone1000-a320" ++ ++config SYS_VENDOR ++ default "armltd" ++ ++config SYS_CONFIG_NAME ++ default "corstone1000-a320" ++ ++endif +diff --git a/board/armltd/corstone1000-a320/MAINTAINERS b/board/armltd/corstone1000-a320/MAINTAINERS +new file mode 100644 +index 00000000000..e62978b487e +--- /dev/null ++++ b/board/armltd/corstone1000-a320/MAINTAINERS +@@ -0,0 +1,7 @@ ++CORSTONE1000-A320 BOARD ++M: Harsimran Singh Tungal ++M: Frazer Carsley ++M: Hugues Kamba Mpiana ++S: Maintained ++F: board/armltd/corstone1000-a320/ ++F: configs/corstone1000-a320_defconfig +diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c +index db8919298e1..0557865f59b 100644 +--- a/board/armltd/corstone1000/corstone1000.c ++++ b/board/armltd/corstone1000/corstone1000.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* +- * (C) Copyright 2022, 2025 Arm Limited ++ * (C) Copyright 2022, 2025-2026 Arm Limited + * (C) Copyright 2022 Linaro + * Rui Miguel Silva + */ +@@ -264,7 +264,7 @@ struct mm_region *mem_map = corstone1000_mem_map; + int board_init(void) + { + #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +- if (!strcmp(DEVICE_TREE, "arm/corstone1000-fvp")) ++ if (!strstr(DEVICE_TREE, "fvp")) + update_info.images = fw_fvp_images; + else + update_info.images = fw_mps3_images; +@@ -396,7 +396,7 @@ int board_late_init(void) + const char *cmp_dtb = DEVICE_TREE; + int ret; + +- if (!strcmp(cmp_dtb, "arm/corstone1000-fvp")) { ++ if (!strstr(cmp_dtb, "fvp")) { + ret = uclass_first_device_err(UCLASS_VIRTIO, &virtio_bus); + if (!virtio_bus) { + log_err("Cannot find virtio device, err (%d)\n", ret); +diff --git a/configs/corstone1000-a320_defconfig b/configs/corstone1000-a320_defconfig +new file mode 100644 +index 00000000000..d0ae1e745db +--- /dev/null ++++ b/configs/corstone1000-a320_defconfig +@@ -0,0 +1,89 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_TARGET_CORSTONE1000=y ++CONFIG_TEXT_BASE=0x80000000 ++CONFIG_SYS_MALLOC_LEN=0x2000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="corstone1000-a320-fvp" ++CONFIG_SYS_BOOTM_LEN=0x800000 ++CONFIG_SYS_LOAD_ADDR=0x82100000 ++CONFIG_IDENT_STRING=" corstone1000-a320 aarch64 " ++CONFIG_FWU_NUM_IMAGES_PER_BANK=4 ++CONFIG_EFI_SECURE_BOOT=y ++CONFIG_EFI_SET_TIME=y ++CONFIG_EFI_MM_COMM_TEE=y ++CONFIG_FFA_SHARED_MM_BUF_SIZE=4096 ++CONFIG_FFA_SHARED_MM_BUF_OFFSET=0 ++CONFIG_FFA_SHARED_MM_BUF_ADDR=0x81FFF000 ++CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y ++CONFIG_EFI_CAPSULE_ON_DISK=y ++CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y ++CONFIG_EFI_CAPSULE_AUTHENTICATE=y ++CONFIG_EFI_CAPSULE_CRT_FILE="CRT.crt" ++CONFIG_FIT=y ++CONFIG_FIT_SIGNATURE=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DISTRO_DEFAULTS=y ++CONFIG_BOOTDELAY=3 ++CONFIG_USE_BOOTARGS=y ++CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk" ++CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r $filesize; usb start; usb reset; run prepare_ondisk_fwu ; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" ++CONFIG_CONSOLE_RECORD=y ++CONFIG_SYS_CBSIZE=512 ++CONFIG_LOGLEVEL=7 ++# CONFIG_DISPLAY_CPUINFO is not set ++# CONFIG_DISPLAY_BOARDINFO is not set ++CONFIG_BOARD_INIT=y ++CONFIG_SYS_PROMPT="corstone1000# " ++# CONFIG_CMD_CONSOLE is not set ++CONFIG_CMD_FWU_METADATA=y ++CONFIG_CMD_BOOTZ=y ++# CONFIG_CMD_XIMG is not set ++CONFIG_CMD_NVEDIT_EFI=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_LOADM=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_EFIDEBUG=y ++CONFIG_CMD_RTC=y ++CONFIG_CMD_TIME=y ++CONFIG_CMD_GETTIME=y ++CONFIG_OF_CONTROL=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_CLK=y ++CONFIG_ARM_FFA_TRANSPORT=y ++CONFIG_MISC=y ++CONFIG_ARM_PL180_MMCI=y ++CONFIG_MTD=y ++CONFIG_NVMXIP_QSPI=y ++CONFIG_PHYLIB=y ++CONFIG_PHY_SMSC=y ++CONFIG_SMC911X=y ++CONFIG_PHY=y ++CONFIG_RAM=y ++CONFIG_DM_RTC=y ++CONFIG_RTC_EMULATION=y ++CONFIG_DM_SERIAL=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_PSCI=y ++CONFIG_TEE=y ++CONFIG_OPTEE=y ++CONFIG_USB=y ++CONFIG_USB_ISP1760=y ++CONFIG_VIRTIO_MMIO=y ++CONFIG_VIRTIO_NET=y ++# CONFIG_RANDOM_UUID is not set ++CONFIG_ERRNO_STR=y ++# CONFIG_HEXDUMP is not set ++CONFIG_FWU_MULTI_BANK_UPDATE=y ++CONFIG_FWU_MDATA_V2=y ++CONFIG_FWU_ARM_PSA=y ++# CONFIG_TOOLS_MKEFICAPSULE is not set +diff --git a/doc/device-tree-bindings/arm/arm,corstone1000-a320.yml b/doc/device-tree-bindings/arm/arm,corstone1000-a320.yml +new file mode 100644 +index 00000000000..9c8671d1775 +--- /dev/null ++++ b/doc/device-tree-bindings/arm/arm,corstone1000-a320.yml +@@ -0,0 +1,31 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/arm/arm,corstone1000-a320.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: ARM Corstone1000-A320 ++ ++maintainers: ++ - Frazer Carsley ++ - Harsimran Singh Tungal ++ - Hugues Kamba Mpiana ++ ++description: |+ ++ ARM's Corstone1000-A320 platform is a Corstone1000 variant that supports ++ Cortex-A320 processors, enables the use of an integrated Ethos-U85 NPU and ++ an upgraded GIC-700 interrupt controller. ++ ++properties: ++ $nodename: ++ const: '/' ++ compatible: ++ oneOf: ++ - description: Corstone1000-A320 FVP is the Fixed Virtual Platform ++ implementation of this system. See ARM ecosystems FVP's. ++ items: ++ - const: arm,corstone1000-a320-fvp ++ ++additionalProperties: true ++ ++... diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/corstone1000-a320.cfg b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/corstone1000-a320.cfg deleted file mode 100644 index 46760950..00000000 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/corstone1000-a320.cfg +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ETHOS_U85=y -CONFIG_GIC_700=y From patchwork Mon Mar 30 10:43:13 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Safwat X-Patchwork-Id: 84823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3043FB3D1F for ; Mon, 30 Mar 2026 10:54:51 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.msgproc01-g2.48395.1774868087514869522 for ; Mon, 30 Mar 2026 03:54:47 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="dkim: body hash did not verify" header.i=@arm.com header.s=foss header.b=KKIY08KG; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: michael.safwat@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2D08D1C2B; Mon, 30 Mar 2026 03:54:41 -0700 (PDT) Received: from e142473.cambridge.arm.com (e142473.arm.com [10.1.198.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A03BF3F915; Mon, 30 Mar 2026 03:54:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1774868087; bh=ycEXxNOR+ilZgmIZwyfyW7L5zO9Y0XLKD+TbceId5Ho=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KKIY08KGyO0vZK1VvbU/BAqg2eXhhfUcdpurwbfIpc7YKuTgWuLmnQF1OCyY0SXhA VZJ6SNJoUFvL7FdYA/7wtnW3SOpoezehTf5jKR5LpJ0Ru8gvUaceUfRVY5FFbSVu/4 9ceab/dqLMPo3XIxyvzpOG9gGraAF8yRqErgs+Eo= From: Michael Safwat To: meta-arm@lists.yoctoproject.org Cc: Michael Safwat Subject: [PATCH 3/7] arm-bsp/corstone1000: Add linux-yocto 6.19 kernel recipe Date: Mon, 30 Mar 2026 11:43:13 +0100 Message-ID: <20260330105428.2580463-4-michael.safwat@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330105428.2580463-1-michael.safwat@arm.com> References: <20260330105428.2580463-1-michael.safwat@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 30 Mar 2026 10:54:51 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6984 linux-yocto does not currently ship a 6.19 recipe, so add a meta-arm-bsp linux-yocto_6.19.bb that tracks linux-yocto-dev v6.19/base. Pin SRCREV_machine to fixed revision to keep builds reproducible. Update Corstone-1000 to prefer linux-yocto 6.19 and align the user guide pointers accordingly. Signed-off-by: Michael Safwat --- .../conf/machine/include/corstone1000.inc | 2 +- .../documentation/corstone1000/user-guide.rst | 2 +- .../recipes-kernel/linux/linux-yocto_6.19.bb | 37 +++++++++++++++++++ 3 files changed, 39 insertions(+), 2 deletions(-) create mode 100644 meta-arm-bsp/recipes-kernel/linux/linux-yocto_6.19.bb diff --git a/meta-arm-bsp/conf/machine/include/corstone1000.inc b/meta-arm-bsp/conf/machine/include/corstone1000.inc index 6f82c597..309fae61 100644 --- a/meta-arm-bsp/conf/machine/include/corstone1000.inc +++ b/meta-arm-bsp/conf/machine/include/corstone1000.inc @@ -37,7 +37,7 @@ IMAGE_CMD:wic[vardeps] += "GRUB_LINUX_APPEND" # Linux kernel PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto" -PREFERRED_VERSION_linux-yocto ?= "6.18.%" +PREFERRED_VERSION_linux-yocto ?= "6.19%" KERNEL_IMAGETYPE = "Image" KERNEL_IMAGETYPE:firmware = "Image.gz" # add FF-A support in the kernel diff --git a/meta-arm-bsp/documentation/corstone1000/user-guide.rst b/meta-arm-bsp/documentation/corstone1000/user-guide.rst index 18086d25..2a35f432 100644 --- a/meta-arm-bsp/documentation/corstone1000/user-guide.rst +++ b/meta-arm-bsp/documentation/corstone1000/user-guide.rst @@ -157,7 +157,7 @@ The provided distribution is based on `BusyBox `__ and +-----------+------------------------------------------------------------------------------------------------+ | bbappend | ``${WORKSPACE}/meta-arm/meta-arm-bsp/recipes-kernel/linux/linux-yocto_%.bbappend`` | +-----------+------------------------------------------------------------------------------------------------+ -| Recipe | ``${WORKSPACE}/core/meta/recipes-kernel/linux/linux-yocto_6.18.bb`` | +| Recipe | ``${WORKSPACE}/meta-arm/meta-arm-bsp/recipes-kernel/linux/linux-yocto_6.19.bb`` | +-----------+------------------------------------------------------------------------------------------------+ | defconfig | ``${WORKSPACE}/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig`` | +-----------+------------------------------------------------------------------------------------------------+ diff --git a/meta-arm-bsp/recipes-kernel/linux/linux-yocto_6.19.bb b/meta-arm-bsp/recipes-kernel/linux/linux-yocto_6.19.bb new file mode 100644 index 00000000..9c6d421b --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/linux-yocto_6.19.bb @@ -0,0 +1,37 @@ +require recipes-kernel/linux/linux-yocto.inc + +# provide this .inc to set specific revisions +include recipes-kernel/linux/linux-yocto-dev-revisions.inc + +KBRANCH = "v6.19/standard/base" +KMETA = "kernel-meta" + +DEFAULT_PREFERENCE = "-1" + +# CVE exclusions +include recipes-kernel/linux/cve-exclusion.inc +include recipes-kernel/linux/cve-exclusion_6.19.inc + +# linux-yocto-dev pinned to 6.19 +KBRANCH = "v6.19/standard/base" +SRCREV_machine = "c042e9e14dd7efb27e9556c42db39425a2860572" +SRCREV_meta = "6df48aa0b0d32d05614d7eda898f8d930a7600b7" + +SRC_URI = "git://git.yoctoproject.org/linux-yocto-dev.git;name=machine;branch=${KBRANCH};protocol=https \ + git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=master;destsuffix=${KMETA};protocol=https" + +LIC_FILES_CHKSUM = "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46" + +KCONF_BSP_AUDIT_LEVEL = "1" + +# Functionality flags +KERNEL_EXTRA_FEATURES ?= "features/netfilter/netfilter.scc" +KERNEL_FEATURES:append = " ${KERNEL_EXTRA_FEATURES}" +KERNEL_FEATURES:append = " ${@bb.utils.contains("TUNE_FEATURES", "mx32", " cfg/x32.scc", "", d)}" +KERNEL_FEATURES:append = " ${@bb.utils.contains("DISTRO_FEATURES", "ptest", " features/scsi/scsi-debug.scc features/nf_tables/nft_test.scc", "", d)}" +KERNEL_FEATURES:append = " ${@bb.utils.contains("DISTRO_FEATURES", "ptest", " features/gpio/mockup.scc features/gpio/sim.scc", "", d)}" +KERNEL_FEATURES:append = " ${@bb.utils.contains("KERNEL_DEBUG", "True", " features/reproducibility/reproducibility.scc features/debug/debug-btf.scc", "", d)}" +# libteam ptests from meta-oe needs it +KERNEL_FEATURES:append = " ${@bb.utils.contains("DISTRO_FEATURES", "ptest", " features/net/team/team.scc", "", d)}" +# openl2tp tests from meta-networking needs it +KERNEL_FEATURES:append = " ${@bb.utils.contains("DISTRO_FEATURES", "ptest", " cgl/cfg/net/l2tp.scc", "", d)}" From patchwork Mon Mar 30 10:43:14 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Safwat X-Patchwork-Id: 84824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6B28FD0052 for ; Mon, 30 Mar 2026 10:54:51 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.msgproc02-g2.48191.1774868088664430708 for ; Mon, 30 Mar 2026 03:54:48 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="dkim: body hash did not verify" header.i=@arm.com header.s=foss header.b=nAMrfnWF; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: michael.safwat@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EBE002BCB; Mon, 30 Mar 2026 03:54:41 -0700 (PDT) Received: from e142473.cambridge.arm.com (e142473.arm.com [10.1.198.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 50EB03F915; Mon, 30 Mar 2026 03:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1774868087; bh=T7/rWtQzrntMBPXF2EoGNEHolSt4OlMJPJmyF0GiL6E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nAMrfnWFFHYFV3aFZB5qSyPQGegNJ/YRC3q0mVXtLOOfTOrZDaolmilPaWGB8/E4J N9mciDxNyz3Plv9+FtKEQyxnklYDFdIx6XJAcEp05vTWh+5OqGZW/kaP4vWptPbQw+ kvp5Ow3EsBwLLcdpzAXjwWptB9/v7tBOs2CcZoKw= From: Michael Safwat To: meta-arm@lists.yoctoproject.org Cc: Michael Safwat , Frazer Carsley Subject: [PATCH 4/7] arm-bsp/u-boot: cs1k: Align Ethos-U85 DT with in-tree driver Date: Mon, 30 Mar 2026 11:43:14 +0100 Message-ID: <20260330105428.2580463-5-michael.safwat@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330105428.2580463-1-michael.safwat@arm.com> References: <20260330105428.2580463-1-michael.safwat@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 30 Mar 2026 10:54:51 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6985 Align the Corstone1000 Ethos-U85 device tree to match the upstream bindings used by the in-tree Ethos-U DRM accel driver. - Rework the Corstone1000 U-Boot patch to replace the legacy arm,ethosu-direct node with an upstream-style Ethos-U85 node (arm,ethos-u85), add the required clocks/clock-names, and switch the SRAM description to mmio-sram. - Drop meta-ethos specific properties (reserved-memory/dma-ranges, /region-cfgs/mem-config) from the U-Boot DT. - Enable required kernel options for the in-tree driver and SRAM provider: - CONFIG_SRAM - CONFIG_DRM - CONFIG_DRM_ACCEL - CONFIG_DRM_ACCEL_ARM_ETHOSU Signed-off-by: Michael Safwat Signed-off-by: Frazer Carsley --- ...-a320-Add-Corstone1000-board-variant.patch | 81 ++++++------------- .../linux/files/corstone1000/ethosu.cfg | 4 + .../linux/linux-arm-platforms.inc | 1 + 3 files changed, 30 insertions(+), 56 deletions(-) create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/ethosu.cfg diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-a320-Add-Corstone1000-board-variant.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-a320-Add-Corstone1000-board-variant.patch index d370021b..59bf7aa2 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-a320-Add-Corstone1000-board-variant.patch +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-a320-Add-Corstone1000-board-variant.patch @@ -1,4 +1,4 @@ -From 9f95097d9b2d9b1360b5c105161509ea9a5b198d Mon Sep 17 00:00:00 2001 +From da23886f3b38812c60a4597db129ab96df74bb99 Mon Sep 17 00:00:00 2001 From: Frazer Carsley Date: Wed, 25 Feb 2026 14:28:08 +0000 Subject: [PATCH] corstone1000-a320: Add Corstone1000 board variant @@ -22,13 +22,9 @@ compatibility with Cortex-A35 and GIC-400. * Add `/ethosu@1a050000` node describing the NPU register block at `0x1A050000`. -* Introduce associated reserved memory regions: - * `ethosu_sram@02400000`: 2 MiB on-chip SRAM (`no-map`). - * `ethosu_reserved@A0000000`: 32 MiB DDR carve-out - (`shared-dma-pool`). -* Connect memory regions through `memory-region` and `sram` phandles. -* Add `dma-ranges`, interrupt spec, `region-cfgs`, `cs-region`, and - `ethosu-mem-config` for full driver support. +* `ethosu_sram@02400000`: 2 MiB on-chip SRAM. +* Fully compliant with upstream bindings. + **GIC-700 support** * Add full GICv3 node. @@ -41,20 +37,22 @@ These updates align the Corstone-1000 platform with Arm’s latest Cortex-A320 and Ethos-U85 configurations and ensure proper interrupt and memory mapping for both secure and non-secure domains. -Upstream-Status: Inappropriate [Unsupported ethosu device-tree nodes, denied by maintainers (https://lore.kernel.org/all/20251127154752.589691-1-frazer.carsley@arm.com/)] +Upstream-Status: Pending [Strong dependency on previous patches that +should be upstreamed first] Signed-off-by: Frazer Carsley Signed-off-by: Harsimran Singh Tungal +Signed-off-by: Michael Safwat --- arch/arm/Kconfig | 1 + - arch/arm/dts/corstone1000-a320-fvp.dts | 51 ++++ - arch/arm/dts/corstone1000-a320.dtsi | 237 ++++++++++++++++++ + arch/arm/dts/corstone1000-a320-fvp.dts | 51 +++++ + arch/arm/dts/corstone1000-a320.dtsi | 208 ++++++++++++++++++ arch/arm/include/asm/armv8/cpu.h | 3 + board/armltd/corstone1000-a320/Kconfig | 12 + board/armltd/corstone1000-a320/MAINTAINERS | 7 + board/armltd/corstone1000/corstone1000.c | 6 +- - configs/corstone1000-a320_defconfig | 89 +++++++ + configs/corstone1000-a320_defconfig | 89 ++++++++ .../arm/arm,corstone1000-a320.yml | 31 +++ - 9 files changed, 434 insertions(+), 3 deletions(-) + 9 files changed, 405 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/corstone1000-a320-fvp.dts create mode 100644 arch/arm/dts/corstone1000-a320.dtsi create mode 100644 board/armltd/corstone1000-a320/Kconfig @@ -133,10 +131,10 @@ index 00000000000..c01c629e0ca +}; diff --git a/arch/arm/dts/corstone1000-a320.dtsi b/arch/arm/dts/corstone1000-a320.dtsi new file mode 100644 -index 00000000000..28424db77bb +index 00000000000..6715e15ec37 --- /dev/null +++ b/arch/arm/dts/corstone1000-a320.dtsi -@@ -0,0 +1,237 @@ +@@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright 2026, Arm Limited and/or its affiliates @@ -260,42 +258,26 @@ index 00000000000..28424db77bb + method = "smc"; + }; + -+ ethosu: ethosu@1A050000 { -+ compatible = "arm,ethosu-direct"; ++ ethosu_sram: ethosu_sram@02400000 { ++ compatible = "mmio-sram"; ++ reg = <0x02400000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; ++ ranges; ++ }; ++ ++ ethosu@1A050000 { ++ compatible = "arm,corstone1000-ethos-u85", "arm,ethos-u85"; + + // Base address and size of NPU registers + reg = <0x1A050000 0x4000>; + -+ memory-region = <ðosu_reserved>; + sram = <ðosu_sram>; + -+ // Address mappings to translate between bus addresses (NPU) and physical host CPU addresses -+ dma-ranges = <0x02400000 0x02400000 0x200000>, -+ <0xA0000000 0xA0000000 0x02000000>; -+ -+ interrupts = <0 16 4>; -+ interrupt-names = "irq"; -+ -+ // Memory region configuration -+ region-cfgs = <3 3 0 3 3 3 3 3>; -+ -+ // Memory regions used for the command stream -+ cs-region = <2>; -+ -+ // Memory interface configuration for Ethos-U85 -+ ethosu_mem_config { -+ compatible = "arm,ethosu-mem-config"; -+ // -+ sram = <0 64 32>; -+ ext = <1 64 32>; -+ // -+ configs = <0 0 0>, -+ <0 0 0>, -+ <0 0 1>, -+ <0 0 1>; -+ }; ++ interrupts = ; ++ ++ clocks = <&uartclk>, <&refclk100mhz>; ++ clock-names = "core", "apb"; + }; + + soc { @@ -361,19 +343,6 @@ index 00000000000..28424db77bb + }; +}; + -+&{/reserved-memory} { -+ ethosu_sram: ethosu_sram@02400000 { -+ reg = <0x02400000 0x200000>; -+ no-map; -+ }; -+ -+ ethosu_reserved: ethosu_reserved@A0000000 { -+ compatible = "shared-dma-pool"; -+ reg = <0xA0000000 0x02000000>; -+ no-map; -+ }; -+}; -+ diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index e906fdf1bf1..1ae679f7119 100644 --- a/arch/arm/include/asm/armv8/cpu.h diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/ethosu.cfg b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/ethosu.cfg new file mode 100644 index 00000000..aee5312c --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/ethosu.cfg @@ -0,0 +1,4 @@ +CONFIG_SRAM=y +CONFIG_DRM=y +CONFIG_DRM_ACCEL=y +CONFIG_DRM_ACCEL_ARM_ETHOSU=y diff --git a/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc b/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc index a0c4128f..4bd28ebe 100644 --- a/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc +++ b/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc @@ -65,6 +65,7 @@ KMACHINE:corstone1000:cortexa320 = "corstone1000-a320" LINUX_KERNEL_TYPE:corstone1000:cortexa320 = "standard" SRC_URI:append:corstone1000:cortexa320 = " \ file://defconfig \ + file://ethosu.cfg \ " # Default kernel features not needed for Corstone-1000 with From patchwork Mon Mar 30 10:43:15 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Safwat X-Patchwork-Id: 84821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99383FB3D1B for ; Mon, 30 Mar 2026 10:54:50 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.msgproc02-g2.48192.1774868088881610982 for ; Mon, 30 Mar 2026 03:54:49 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="dkim: body hash did not verify" header.i=@arm.com header.s=foss header.b=jH4sxwsj; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: michael.safwat@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9FEAA1C2B; Mon, 30 Mar 2026 03:54:42 -0700 (PDT) Received: from e142473.cambridge.arm.com (e142473.arm.com [10.1.198.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1AF243F915; Mon, 30 Mar 2026 03:54:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1774868088; bh=eJeZDqzGr1vAO5Gp18hldnSimq4asrF91gWrwRB+7Fc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jH4sxwsjrHEzvCcS4G3CsCh51kPxtFLscKmjRo3LtvURs9jiQzvJqAYDCou1c1kol JR3TXz5tT8XPjq9CYrx5zbOUs99CINKY11BQ/BkSHAYSPjnFwRlnwOyzNP2dpzhuiK 4krvcJarlSB38rMhHZR7c8jMTbvSRzrAOqi9Nefc= From: Michael Safwat To: meta-arm@lists.yoctoproject.org Cc: Michael Safwat Subject: [PATCH 5/7] arm-bsp/corstone1000-a320: Drop meta-ethos dependency Date: Mon, 30 Mar 2026 11:43:15 +0100 Message-ID: <20260330105428.2580463-6-michael.safwat@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330105428.2580463-1-michael.safwat@arm.com> References: <20260330105428.2580463-1-michael.safwat@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 30 Mar 2026 10:54:50 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6986 Corstone1000 with Cortex A320 now uses the in-tree ethosu driver, so the external meta-ethos layer (and its meta-sca dependency) is no longer needed. Remove meta-ethos and meta-sca from the Corstone-1000 A320 kas config, drop the layer dependency on meta-ethos, and stop installing arm-npu-ethosu. Update the Corstone-1000 change log to reflect the removed layers. Signed-off-by: Michael Safwat --- kas/corstone1000-a320.yml | 8 -------- meta-arm-bsp/conf/layer.conf | 1 - meta-arm-bsp/conf/machine/include/corstone1000-a320.inc | 2 -- meta-arm-bsp/documentation/corstone1000/change-log.rst | 4 ---- 4 files changed, 15 deletions(-) diff --git a/kas/corstone1000-a320.yml b/kas/corstone1000-a320.yml index 8a7739af..b11af510 100644 --- a/kas/corstone1000-a320.yml +++ b/kas/corstone1000-a320.yml @@ -7,11 +7,3 @@ local_conf_header: a320: | MACHINE_FEATURES += "cortexa320" OVERRIDES .= ":cortexa320" - -repos: - meta-ethos: - url: https://gitlab.arm.com/iot/meta-ethos.git - branch: whinlatter - meta-sca: - url: https://github.com/priv-kweihmann/meta-sca.git - branch: master diff --git a/meta-arm-bsp/conf/layer.conf b/meta-arm-bsp/conf/layer.conf index 0e54e3f4..eb795f23 100644 --- a/meta-arm-bsp/conf/layer.conf +++ b/meta-arm-bsp/conf/layer.conf @@ -14,7 +14,6 @@ LAYERSERIES_COMPAT_meta-arm-bsp = "wrynose" LAYERDEPENDS_meta-arm-bsp = "core meta-arm" # This won't be used by layerindex-fetch, but works everywhere else LAYERDEPENDS_meta-arm-bsp:append:corstone1000 = " meta-python openembedded-layer efi-secure-boot" -LAYERDEPENDS_meta-arm-bsp:append:corstone1000:cortexa320 = " meta-ethos" LAYERDEPENDS_meta-arm-bsp:append:musca-b1 = " meta-python" LAYERDEPENDS_meta-arm-bsp:append:musca-s1 = " meta-python" diff --git a/meta-arm-bsp/conf/machine/include/corstone1000-a320.inc b/meta-arm-bsp/conf/machine/include/corstone1000-a320.inc index c7ff2df7..69813000 100644 --- a/meta-arm-bsp/conf/machine/include/corstone1000-a320.inc +++ b/meta-arm-bsp/conf/machine/include/corstone1000-a320.inc @@ -1,5 +1,3 @@ ETHOSU_NUM_MACS ?= "256" FVP_CONFIG[host.ethosu.num_macs] = "${ETHOSU_NUM_MACS}" - -IMAGE_INSTALL:append = " arm-npu-ethosu" diff --git a/meta-arm-bsp/documentation/corstone1000/change-log.rst b/meta-arm-bsp/documentation/corstone1000/change-log.rst index e42c5a41..7bab9e21 100644 --- a/meta-arm-bsp/documentation/corstone1000/change-log.rst +++ b/meta-arm-bsp/documentation/corstone1000/change-log.rst @@ -66,10 +66,6 @@ Yocto distribution components versions +-------------------------------------------+----------------+ | meta-secure-core | 63209fb150 | +-------------------------------------------+----------------+ -| meta-ethos | aa2504a32f | -+-------------------------------------------+----------------+ -| meta-sca | e68f1a9d17 | -+-------------------------------------------+----------------+ | busybox | 1.37.0 | +-------------------------------------------+----------------+ | musl | 1.2.5 | From patchwork Mon Mar 30 10:43:16 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Safwat X-Patchwork-Id: 84822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B846FB3D19 for ; Mon, 30 Mar 2026 10:54:50 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.msgproc02-g2.48193.1774868089603890297 for ; Mon, 30 Mar 2026 03:54:49 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="dkim: body hash did not verify" header.i=@arm.com header.s=foss header.b=mZxs+Rfh; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: michael.safwat@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D1641E8D; Mon, 30 Mar 2026 03:54:43 -0700 (PDT) Received: from e142473.cambridge.arm.com (e142473.arm.com [10.1.198.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BFF7E3F915; Mon, 30 Mar 2026 03:54:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1774868089; bh=E7f1c2DmRKtKQMXlAN35IYKAP1S1J/SXIxVql4IaKyo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mZxs+RfhHjZsojHH/l6/JtYWzfL9CTNrhb20Pv9HSvX5963s/x9cZaYunFSzgCqI2 BEU8T4doqecDeLlhh7ruUYssOPIHlyglcINhVP+c7fZzEt2HP/w7v3vMrYXD+23kDt ES61U2X6Z3EoWvO2Z90T5j00LZwqChTxGCtvSvPY= From: Michael Safwat To: meta-arm@lists.yoctoproject.org Cc: Michael Safwat Subject: [PATCH 6/7] arm-bsp/docs: corstone1000: document Cortex-A320 SMP support Date: Mon, 30 Mar 2026 11:43:16 +0100 Message-ID: <20260330105428.2580463-7-michael.safwat@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330105428.2580463-1-michael.safwat@arm.com> References: <20260330105428.2580463-1-michael.safwat@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 30 Mar 2026 10:54:50 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6987 Corstone-1000 with Cortex-A320 FVP now supports SMP, so update the documentation to reflect the current status. Update the user guide to state that SMP is supported on Corstone-1000 with Cortex-A35 FVP and on Corstone-1000 with Cortex-A320 FVP. Add the Cortex-A320 multicore build and run commands. Signed-off-by: Michael Safwat --- .../documentation/corstone1000/user-guide.rst | 25 ++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/meta-arm-bsp/documentation/corstone1000/user-guide.rst b/meta-arm-bsp/documentation/corstone1000/user-guide.rst index 2a35f432..f40f5092 100644 --- a/meta-arm-bsp/documentation/corstone1000/user-guide.rst +++ b/meta-arm-bsp/documentation/corstone1000/user-guide.rst @@ -2182,22 +2182,41 @@ Symmetric Multiprocessing .. warning:: - Symmetric multiprocessing (SMP) mode is only supported on Corstone-1000 with Cortex-A35 FVP but is disabled by default. + Symmetric multiprocessing (SMP) mode is supported on Corstone-1000 + with Cortex-A35 FVP and Corstone-1000 with Cortex-A320 FVP, but is disabled by default. -#. Build the software stack with SMP mode enabled: +#. Build the software stack with SMP mode enabled. + + For Corstone-1000 with Cortex-A35 FVP: .. code-block:: console kas build meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-multicore.yml -#. Run the Corstone-1000 FVP: + For Corstone-1000 with Cortex-A320 FVP: + + .. code-block:: console + + kas build meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-a320.yml:\ + meta-arm/kas/corstone1000-multicore.yml + +#. Run the Corstone-1000 FVP. + + For Corstone-1000 with Cortex-A35 FVP: .. code-block:: console kas shell meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-multicore.yml \ -c "../meta-arm/scripts/runfvp" + For Corstone-1000 with Cortex-A320 FVP: + + .. code-block:: console + + kas shell meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-a320.yml:\ + meta-arm/kas/corstone1000-multicore.yml \ + -c "../meta-arm/scripts/runfvp" #. Verify that the FVP is running the Host Processor with more than one CPU core: From patchwork Mon Mar 30 10:43:17 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Safwat X-Patchwork-Id: 84827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2556D10D14A0 for ; Mon, 30 Mar 2026 10:54:52 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.msgproc02-g2.48195.1774868090229241411 for ; Mon, 30 Mar 2026 03:54:50 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="dkim: body hash did not verify" header.i=@arm.com header.s=foss header.b=akCofDXB; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: michael.safwat@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 018271C2B; Mon, 30 Mar 2026 03:54:44 -0700 (PDT) Received: from e142473.cambridge.arm.com (e142473.arm.com [10.1.198.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 70CCF3F915; Mon, 30 Mar 2026 03:54:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1774868089; bh=YEkmUakRw9/WmJhDJ58iM2QMPAeulsgf+GDlddUxnOQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=akCofDXBYwaC8+V2ClbowrDtRMSOkYY3b8goovgGVHKazEbDwPJTOLUVzHEpfN19A vyVVL0FPKUCmPD9ZN7l1QMEDakcKWaV+71jwM5OFzEx5oHmxiaNv0ZHj7FWDhI0I+D KcN7QVm3fXvTjyIQRLVv3bAbR6/aeEqfDNJmK71Y= From: Michael Safwat To: meta-arm@lists.yoctoproject.org Cc: Michael Safwat Subject: [PATCH 7/7] arm-bsp/docs: corstone1000: switch Ethos-U85 test flow to test_teflon Date: Mon, 30 Mar 2026 11:43:17 +0100 Message-ID: <20260330105428.2580463-8-michael.safwat@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330105428.2580463-1-michael.safwat@arm.com> References: <20260330105428.2580463-1-michael.safwat@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 30 Mar 2026 10:54:52 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6988 Update the Corstone-1000 user guide to reflect the current Ethos-U85 test and workaround flow. As the Corstone-1000 software stack moves to the in-tree ethosu driver, switch the Ethos-U85 test instructions from delegate_runner to Mesa's test_teflon application. Also update the guide to use the renamed ethos-u85-test kas fragment and to apply the Mesa patch needed to package test_teflon into the image. Also replace the disable_module_autoloading kas fragment in the A320 workaround instructions with the disable-ethosu patch, to align with the workaround flow used in systemready-patch. Signed-off-by: Michael Safwat --- .../documentation/corstone1000/user-guide.rst | 55 +++++++++++++------ 1 file changed, 37 insertions(+), 18 deletions(-) diff --git a/meta-arm-bsp/documentation/corstone1000/user-guide.rst b/meta-arm-bsp/documentation/corstone1000/user-guide.rst index f40f5092..cf336ca0 100644 --- a/meta-arm-bsp/documentation/corstone1000/user-guide.rst +++ b/meta-arm-bsp/documentation/corstone1000/user-guide.rst @@ -882,13 +882,26 @@ Capsule Update git clone https://git.gitlab.arm.com/arm-reference-solutions/systemready-patch.git \ -b CORSTONE1000-2025.12 + #. Copy the disable ethosu driver Git patch file to your copy of `meta-arm`. + + .. code-block:: console + + cp -f systemready-patch/embedded-a/corstone1000/disable_module_autoloading/0001-arm-bsp-linux-corstone1000-a320-disable-ethosu-confi.patch \ + ${WORKSPACE}/meta-arm/ + + #. Apply the Git patch to `meta-arm`. + + .. code-block:: console + + cd ${WORKSPACE}/meta-arm/ + git apply 0001-arm-bsp-linux-corstone1000-a320-disable-ethosu-confi.patch + cd ${WORKSPACE} #. Re-Build the **Corstone-1000 with Cortex-A320 FVP** software stack as follows: .. code-block:: console - kas build meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-a320.yml:\ - systemready-patch/embedded-a/corstone1000/disable_module_autoloading/disable_module_autoloading.yml + kas build meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-a320.yml .. important:: @@ -2245,22 +2258,37 @@ Ethos-U85 NPU .. code-block:: console - cp ${WORKSPACE}/systemready-patch/embedded-a/corstone1000/ethos-u85_test/ethos-u85_test.yml \ + cp ${WORKSPACE}/systemready-patch/embedded-a/corstone1000/ethos-u85_test/ethos-u85-test.yml \ ${WORKSPACE}/meta-arm/kas/ +#. Copy the mesa package Git patch file to your copy of meta-arm. + + .. code-block:: console + + cp -f ${WORKSPACE}/systemready-patch/embedded-a/corstone1000/ethos-u85_test/0001-arm-bsp-mesa-Package-Teflon-test-runner-and-models.patch \ + ${WORKSPACE}/meta-arm/ + +#. Apply the Git patch to meta-arm. + + .. code-block:: console + + cd ${WORKSPACE}/meta-arm/ + git apply 0001-arm-bsp-mesa-Package-Teflon-test-runner-and-models.patch + cd ${WORKSPACE} + #. Re-Build the Corstone-1000 with Cortex-A320 FVP software stack as follows: .. code-block:: console kas build meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-a320.yml:\ - meta-arm/kas/ethos-u85_test.yml + meta-arm/kas/ethos-u85-test.yml #. Run the Corstone-1000 with Cortex-320 FVP: .. code-block:: console kas shell meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-a320.yml:\ - systemready-patch/embedded-a/corstone1000/ethos-u85_test/ethos-u85_test.yml \ + systemready-patch/embedded-a/corstone1000/ethos-u85_test/ethos-u85-test.yml \ -c "../meta-arm/scripts/runfvp" #. To verify you are running the Corstone-1000 with Cortex-A320, build and run the FVP and inspect the CPU model @@ -2272,25 +2300,16 @@ Ethos-U85 NPU grep -E 'CPU part|model name' /proc/cpuinfo # Expect: CPU part : 0xd8f (which corresponds to Cortex-A320) -#. Run the `delegate_runner` test application inside the FVP shell as follows: +#. Run the `test_teflon` test application inside the FVP shell as follows: .. code-block:: console - delegate_runner -l /usr/lib/libethosu_op_delegate.so \ - -n /usr/share/ethosu/mobilenet_v2_1.0_224_INT8_vela.tflite \ - -i /usr/share/ethosu/input_data0.bin \ - -o /usr/share/ethosu/actual_output_data0.bin + export TEFLON_TEST_DELEGATE=/usr/lib/libteflon.so + export TEFLON_TEST_DATA=/usr/share/teflon/tests + test_teflon --gtest_filter='Models.*' The test completes in approximately one minute. -#. Run the following command to compare the generated output binary with the expected output binary: - - .. code-block:: console - - cmp -s /usr/share/ethosu/expected_output_data0.bin /usr/share/ethosu/actual_output_data0.bin - - The two binary files should be identical. - Secure Debug ------------