From patchwork Tue Mar 17 13:42:55 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Chapman X-Patchwork-Id: 83634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62E03FD8775 for ; Tue, 17 Mar 2026 13:43:20 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.msgproc02-g2.76259.1773754995253073649 for ; Tue, 17 Mar 2026 06:43:15 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: alex.chapman@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AE66516F2; Tue, 17 Mar 2026 06:43:08 -0700 (PDT) Received: from e142473.cambridge.arm.com (e142473.arm.com [10.1.198.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6450A3F778; Tue, 17 Mar 2026 06:43:14 -0700 (PDT) From: Alex Chapman To: meta-arm@lists.yoctoproject.org Cc: Alex Chapman Subject: [PATCH 1/3] arm-bsp: corstone1000: Make multicore configuration platform-agnostic Date: Tue, 17 Mar 2026 13:42:55 +0000 Message-ID: <20260317134259.493017-2-alex.chapman@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260317134259.493017-1-alex.chapman@arm.com> References: <20260317134259.493017-1-alex.chapman@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 17 Mar 2026 13:43:20 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6957 To improve portability, testing coverage, and future platform enablement. - Gate multicore on `MACHINE_FEATURES += "corstone1000_smp"`. - Change recipe overrides from `:corstone1000-fvp` to `:corstone1000`. - Update the Corstone-1000 multicore kas/doc references. Signed-off-by: Alex Chapman --- ...stone1000-fvp-multicore.yml => corstone1000-multicore.yml} | 4 ++-- meta-arm-bsp/documentation/corstone1000/user-guide.rst | 4 ++-- .../trusted-firmware-a/trusted-firmware-a-corstone1000.inc | 2 +- .../trusted-firmware-m/trusted-firmware-m-corstone1000.inc | 2 +- .../recipes-security/optee/optee-os-corstone1000-common.inc | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) rename kas/{corstone1000-fvp-multicore.yml => corstone1000-multicore.yml} (69%) diff --git a/kas/corstone1000-fvp-multicore.yml b/kas/corstone1000-multicore.yml similarity index 69% rename from kas/corstone1000-fvp-multicore.yml rename to kas/corstone1000-multicore.yml index d806bb11..402ce956 100644 --- a/kas/corstone1000-fvp-multicore.yml +++ b/kas/corstone1000-multicore.yml @@ -4,5 +4,5 @@ header: version: 14 local_conf_header: - fvp-multicore: | - MACHINE_FEATURES += "corstone1000_fvp_smp" + multicore: | + MACHINE_FEATURES += "corstone1000_smp" diff --git a/meta-arm-bsp/documentation/corstone1000/user-guide.rst b/meta-arm-bsp/documentation/corstone1000/user-guide.rst index 95dd60b7..18086d25 100644 --- a/meta-arm-bsp/documentation/corstone1000/user-guide.rst +++ b/meta-arm-bsp/documentation/corstone1000/user-guide.rst @@ -2189,13 +2189,13 @@ Symmetric Multiprocessing .. code-block:: console - kas build meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-fvp-multicore.yml + kas build meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-multicore.yml #. Run the Corstone-1000 FVP: .. code-block:: console - kas shell meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-fvp-multicore.yml \ + kas shell meta-arm/kas/corstone1000-fvp.yml:meta-arm/ci/debug.yml:meta-arm/kas/corstone1000-multicore.yml \ -c "../meta-arm/scripts/runfvp" diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc index d7c436dc..a6621145 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc @@ -58,7 +58,7 @@ EXTRA_OEMAKE:append = " \ BL32=${RECIPE_SYSROOT}/${nonarch_base_libdir}/firmware/tee-pager_v2.bin \ FVP_USE_GIC_DRIVER=${FVP_GIC_DRIVER} \ " -EXTRA_OEMAKE:append:corstone1000-fvp = "${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_fvp_smp', ' ENABLE_MULTICORE=1', '', d)}" +EXTRA_OEMAKE:append = "${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_smp', ' ENABLE_MULTICORE=1', '', d)}" # Add Cortex-A320 specific configurations EXTRA_OEMAKE:append:cortexa320 = " \ diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc index fe2c05a0..72144df0 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc @@ -26,7 +26,7 @@ EXTRA_OECMAKE:append:cortexa320 = " \ EXTRA_OECMAKE += "-DPLATFORM_IS_FVP=${TFM_PLATFORM_IS_FVP}" EXTRA_OECMAKE += "-DCC312_LEGACY_DRIVER_API_ENABLED=OFF" -EXTRA_OECMAKE:append:corstone1000-fvp = " -DENABLE_MULTICORE=${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_fvp_smp', 'TRUE', 'FALSE', d)}" +EXTRA_OECMAKE:append = " -DENABLE_MULTICORE=${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_smp', 'TRUE', 'FALSE', d)}" EXTRA_OECMAKE:append:corstone1000-mps3 = " -DPLATFORM_PSA_ADAC_SECURE_DEBUG=${@bb.utils.contains('MACHINE_FEATURES', 'secure-debug', 'ON', 'OFF', d)}" EXTRA_OECMAKE:append:corstone1000-mps3 = " -DPLATFORM_PSA_ADAC_SOURCE_PATH=${S}/external/tfm-psa-adac -DPLATFORM_PSA_ADAC_BUILD_PATH=${B}/tfm-psa-adac-build" diff --git a/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc b/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc index 304dd0a9..4a90ca3e 100644 --- a/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc +++ b/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc @@ -19,7 +19,7 @@ EXTRA_OEMAKE += " CFG_CORE_SEL1_SPMC=y CFG_CORE_FFA=y" EXTRA_OEMAKE += " CFG_WITH_SP=y" -EXTRA_OEMAKE:append:corstone1000-fvp = "${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_fvp_smp', ' CFG_TEE_CORE_NB_CORE=4', '', d)}" +EXTRA_OEMAKE:append = "${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_smp', ' CFG_TEE_CORE_NB_CORE=4', '', d)}" # Override OP-TEE OS ARM64 core architecture based on MACHINE_FEATURES CPUARCH = "cortex-a35" From patchwork Tue Mar 17 13:42:56 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Chapman X-Patchwork-Id: 83633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CFF4FD8777 for ; Tue, 17 Mar 2026 13:43:20 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.msgproc01-g2.76212.1773754995878875384 for ; Tue, 17 Mar 2026 06:43:16 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: alex.chapman@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 56D7C19F6; Tue, 17 Mar 2026 06:43:09 -0700 (PDT) Received: from e142473.cambridge.arm.com (e142473.arm.com [10.1.198.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0C4893F778; Tue, 17 Mar 2026 06:43:14 -0700 (PDT) From: Alex Chapman To: meta-arm@lists.yoctoproject.org Cc: Alex Chapman Subject: [PATCH 2/3] arm-bsp/trusted-firmware-a: corstone1000: Remove FVP requirement for TF-A multicore Date: Tue, 17 Mar 2026 13:42:56 +0000 Message-ID: <20260317134259.493017-3-alex.chapman@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260317134259.493017-1-alex.chapman@arm.com> References: <20260317134259.493017-1-alex.chapman@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 17 Mar 2026 13:43:20 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6958 To improve portability, testing coverage, and future platform enablement. - Replace FVP-only multicore guards with platform-generic guards. - Add the corresponding TF-A patch to the Corstone-1000 recipe. Signed-off-by: Alex Chapman --- ...000-make-mutlicore-support-platform-.patch | 113 ++++++++++++++++++ .../trusted-firmware-a-corstone1000.inc | 1 + 2 files changed, 114 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-feat-corestone-1000-make-mutlicore-support-platform-.patch diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-feat-corestone-1000-make-mutlicore-support-platform-.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-feat-corestone-1000-make-mutlicore-support-platform-.patch new file mode 100644 index 00000000..c338fba0 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-feat-corestone-1000-make-mutlicore-support-platform-.patch @@ -0,0 +1,113 @@ +From a9801643d9d4d3f24960c5f24d5f5c3fd4889cc1 Mon Sep 17 00:00:00 2001 +From: Alex Chapman +Date: Tue, 3 Mar 2026 17:00:58 +0000 +Subject: [PATCH] feat(corestone-1000): make mutlicore support platform generic + +To improve portability, testing coverage, and future platform enablement. + +- Replace FVP-only multicore checks with platform-generic checks. +- Add the corresponding TF-M patch to the Corstone-1000 recipe. + +Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/49092] +Signed-off-by: Alex Chapman +--- + plat/arm/board/corstone1000/common/corstone1000_helpers.S | 4 ++-- + plat/arm/board/corstone1000/common/corstone1000_pm.c | 6 +++--- + plat/arm/board/corstone1000/common/include/platform_def.h | 4 ++-- + plat/arm/board/corstone1000/platform.mk | 6 ++---- + 4 files changed, 9 insertions(+), 11 deletions(-) + +diff --git a/plat/arm/board/corstone1000/common/corstone1000_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S +index 665dbc61a..d41df4ebe 100644 +--- a/plat/arm/board/corstone1000/common/corstone1000_helpers.S ++++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2021-2025 Arm Limited and Contributors. All rights reserved. ++ * Copyright (c) 2021-2026 Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -54,7 +54,7 @@ endfunc plat_arm_calc_core_pos + * -------------------------------------------------------------------- + */ + func plat_secondary_cold_boot_setup +-#if defined(CORSTONE1000_FVP_MULTICORE) ++#if defined(CORSTONE1000_MULTICORE) + + /* Calculate the address of our hold entry */ + bl plat_my_core_pos +diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c +index a87697e97..2c7a2c67b 100644 +--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c ++++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved. ++ * Copyright (c) 2021-2026, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -41,7 +41,7 @@ static void corstone1000_system_reset(void) + *watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE; + } + +-#if defined(CORSTONE1000_FVP_MULTICORE) ++#if defined(CORSTONE1000_MULTICORE) + int corstone1000_validate_ns_entrypoint(uintptr_t entrypoint) + { + /* +@@ -77,7 +77,7 @@ void corstone1000_pwr_domain_on_finish(const psci_power_state_t *target_state) + #endif + + plat_psci_ops_t plat_arm_psci_pm_ops = { +-#if defined(CORSTONE1000_FVP_MULTICORE) ++#if defined(CORSTONE1000_MULTICORE) + .pwr_domain_on = corstone1000_pwr_domain_on, + .pwr_domain_on_finish = corstone1000_pwr_domain_on_finish, + .validate_ns_entrypoint = corstone1000_validate_ns_entrypoint, +diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h +index ffb1e2dec..4682b8b5d 100644 +--- a/plat/arm/board/corstone1000/common/include/platform_def.h ++++ b/plat/arm/board/corstone1000/common/include/platform_def.h +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved. ++ * Copyright (c) 2021-2026, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -266,7 +266,7 @@ + + #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE + +-#if defined(CORSTONE1000_FVP_MULTICORE) ++#if defined(CORSTONE1000_MULTICORE) + /* The secondary core entrypoint address points to bl31_warm_entrypoint + * and the address size is 8 bytes */ + #define CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE UL(0x8) +diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk +index fe3e94865..dee40f3b3 100644 +--- a/plat/arm/board/corstone1000/platform.mk ++++ b/plat/arm/board/corstone1000/platform.mk +@@ -1,5 +1,5 @@ + # +-# Copyright (c) 2021-2025 Arm Limited and Contributors. All rights reserved. ++# Copyright (c) 2021-2026 Arm Limited and Contributors. All rights reserved. + # + # SPDX-License-Identifier: BSD-3-Clause + # +@@ -44,10 +44,8 @@ $(eval $(call add_define,CORSTONE1000_WITH_BL32)) + endif + + ENABLE_MULTICORE := 0 +-ifneq ($(filter ${TARGET_PLATFORM}, fvp),) + ifeq (${ENABLE_MULTICORE},1) +-$(eval $(call add_define,CORSTONE1000_FVP_MULTICORE)) +-endif ++$(eval $(call add_define,CORSTONE1000_MULTICORE)) + endif + + ifdef CORSTONE1000_CORTEX_A320 +-- +2.43.0 diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc index a6621145..c77ec29d 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc @@ -6,6 +6,7 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:" SRC_URI:append = " \ file://0001-Fix-FF-A-version-in-SPMC-manifest.patch \ file://0002-plat-corstone1000-add-Cortex-A320-support.patch \ + file://0003-feat-corestone-1000-make-mutlicore-support-platform-.patch \ " TFA_DEBUG = "1" From patchwork Tue Mar 17 13:42:57 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alex Chapman X-Patchwork-Id: 83632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEBA5FD8770 for ; Tue, 17 Mar 2026 13:43:19 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.msgproc02-g2.76261.1773754996497828751 for ; Tue, 17 Mar 2026 06:43:16 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: alex.chapman@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F21811477; Tue, 17 Mar 2026 06:43:09 -0700 (PDT) Received: from e142473.cambridge.arm.com (e142473.arm.com [10.1.198.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A7E9B3F778; Tue, 17 Mar 2026 06:43:15 -0700 (PDT) From: Alex Chapman To: meta-arm@lists.yoctoproject.org Cc: Alex Chapman Subject: [PATCH 3/3] arm-bsp/trusted-firmware-m: corstone1000: Remove FVP requirement for TF-M multicore Date: Tue, 17 Mar 2026 13:42:57 +0000 Message-ID: <20260317134259.493017-4-alex.chapman@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260317134259.493017-1-alex.chapman@arm.com> References: <20260317134259.493017-1-alex.chapman@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 17 Mar 2026 13:43:19 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6959 To improve portability, testing coverage, and future platform enablement. - Replace FVP-only multicore checks with platform-generic checks. - Add the corresponding TF-M patch to the Corstone-1000 recipe. Signed-off-by: Alex Chapman --- ...ke-mutlicore-support-platform-generi.patch | 90 +++++++++++++++++++ .../trusted-firmware-m-corstone1000.inc | 1 + 2 files changed, 91 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0015-Platform-CS1K-make-mutlicore-support-platform-generi.patch diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0015-Platform-CS1K-make-mutlicore-support-platform-generi.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0015-Platform-CS1K-make-mutlicore-support-platform-generi.patch new file mode 100644 index 00000000..36a919e1 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0015-Platform-CS1K-make-mutlicore-support-platform-generi.patch @@ -0,0 +1,90 @@ +From 9f86d644aa23589e5187f0a22394438cd525d574 Mon Sep 17 00:00:00 2001 +From: Alex Chapman +Date: Wed, 4 Mar 2026 13:41:59 +0000 +Subject: [PATCH] Platform: CS1K: make mutlicore support platform generic + +To improve portability, testing coverage, and future platform enablement. + +- Replace FVP-only multicore checks with platform-generic checks. + +Upstream-Status: Backport [71619253e03cc10cdd4527ab7e896e3ec10afabe] +Signed-off-by: Alex Chapman +--- + platform/ext/target/arm/corstone1000/CMakeLists.txt | 4 +--- + .../target/arm/corstone1000/Device/Config/device_cfg.h | 2 +- + platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c | 8 ++++---- + 3 files changed, 6 insertions(+), 8 deletions(-) + +diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt +index 993c51591..a13f16fd7 100644 +--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt ++++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt +@@ -407,12 +407,10 @@ target_sources(tfm_psa_rot_partition_ns_agent_mailbox + tfm_hal_multi_core.c + ) + +-if (PLATFORM_IS_FVP) + target_compile_definitions(tfm_psa_rot_partition_ns_agent_mailbox + PUBLIC +- $<$:CORSTONE1000_FVP_MULTICORE> ++ $<$:CORSTONE1000_MULTICORE> + ) +-endif() + #========================= tfm_spm ============================================# + + target_sources(tfm_spm +diff --git a/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h b/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h +index 544475a86..0c3a9088e 100644 +--- a/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h ++++ b/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h +@@ -46,7 +46,7 @@ + #define CFI_S + + /* Total number of host cores */ +-#if CORSTONE1000_FVP_MULTICORE ++#if CORSTONE1000_MULTICORE + #define PLATFORM_HOST_MAX_CORE_COUNT 4 + #else + #define PLATFORM_HOST_MAX_CORE_COUNT 1 +diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c +index 10c66ac41..9a785bfa0 100644 +--- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c ++++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c +@@ -62,7 +62,7 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr) + volatile uint32_t *PE0_CONFIG = + (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE + + HOST_CPU_PE0_CONFIG_OFFSET); +-#if CORSTONE1000_FVP_MULTICORE ++#if CORSTONE1000_MULTICORE + volatile uint32_t *PE1_CONFIG = + (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE + + HOST_CPU_PE1_CONFIG_OFFSET); +@@ -80,7 +80,7 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr) + #endif + /* Select host CPU architecture as AArch64 */ + *PE0_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */ +-#if CORSTONE1000_FVP_MULTICORE ++#if CORSTONE1000_MULTICORE + *PE1_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */ + *PE2_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */ + *PE3_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */ +@@ -92,7 +92,7 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr) + /* Clear HOST_SYS_RST_CTRL register to bring host out of RESET */ + *reset_ctl_reg = 0; + +-#if CORSTONE1000_FVP_MULTICORE ++#if CORSTONE1000_MULTICORE + /* Wake up secondary cores. + * This should be done after bringing the primary core out of reset.*/ + for (int core_index=1; core_index < PLATFORM_HOST_MAX_CORE_COUNT; core_index++) { +@@ -111,7 +111,7 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr) + PPU_SetOperatingPolicy(CORE0_PPU, PPU_OP_MODE_ONE_SLICE_SF_ONLY_ON, false); + PPU_SetPowerPolicy(CORE0_PPU, PPU_PWR_MODE_ON, false); + +-#if CORSTONE1000_FVP_MULTICORE ++#if CORSTONE1000_MULTICORE + /* Power on all Cortex-A320 cores in DSU-120T Cluster */ + PPU_SetOperatingPolicy(CORE1_PPU, PPU_OP_MODE_ONE_SLICE_SF_ONLY_ON, false); + PPU_SetPowerPolicy(CORE1_PPU, PPU_PWR_MODE_ON, false); +-- +2.43.0 diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc index 72144df0..17b1794b 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc @@ -46,6 +46,7 @@ SRC_URI:append:corstone1000 = " \ file://0012-bl2-corstone-1000-secure-debug-waiting-in-CM-LCS.patch \ file://0013-Build-adjust-CS1000-platform-for-GCC-v14.2.patch \ file://0014-Workaround-compile-errors-in-AES.patch \ + file://0015-Platform-CS1K-make-mutlicore-support-platform-generi.patch \ " SRCREV_tfm-psa-adac:corstone1000 = "f2809ae231be33a1afcd7714f40756c67d846c88"