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https://lists.openembedded.org/g/openembedded-core/message/222057 Signed-off-by: Khem Raj --- ...-Add-SPV_INTEL_function_variants-532.patch | 642 ++++++++++++++++++ .../spir/spirv-headers_1.4.321.0.bb | 4 +- 2 files changed, 645 insertions(+), 1 deletion(-) create mode 100644 meta/recipes-graphics/spir/spirv-headers/0001-Add-SPV_INTEL_function_variants-532.patch diff --git a/meta/recipes-graphics/spir/spirv-headers/0001-Add-SPV_INTEL_function_variants-532.patch b/meta/recipes-graphics/spir/spirv-headers/0001-Add-SPV_INTEL_function_variants-532.patch new file mode 100644 index 00000000000..9a3ab153508 --- /dev/null +++ b/meta/recipes-graphics/spir/spirv-headers/0001-Add-SPV_INTEL_function_variants-532.patch @@ -0,0 +1,642 @@ +From 9e3836d7d6023843a72ecd3fbf3f09b1b6747a9e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jakub=20=C5=BD=C3=A1dn=C3=ADk?= +Date: Tue, 24 Jun 2025 15:35:27 +0300 +Subject: [PATCH] Add SPV_INTEL_function_variants (#532) + +* Add tokens for SPV_INTEL_function_variants + +Add FunctionVariantXXX decorations + +Add SpecConditionalINTEL capability + +Change class of conditional copy to Composite + +Add new instructions; Update tokens + +Fix wrong op name + +Change spec const arch operand to integer + +Reassign tokens; Fix operand + +Remove old decorations + +* Generate headers + +* Add provisional entries and missing capability + +Co-authored-by: Victor Lomuller + +--------- + +Upstream-Status: Backport [https://github.com/KhronosGroup/SPIRV-Headers/commit/9e3836d7d6023843a72ecd3fbf3f09b1b6747a9e] +Signed-off-by: Khem Raj +Co-authored-by: Victor Lomuller +--- + include/spirv/unified1/spirv.bf | 10 ++ + .../spirv/unified1/spirv.core.grammar.json | 120 ++++++++++++++++++ + include/spirv/unified1/spirv.cs | 10 ++ + include/spirv/unified1/spirv.h | 27 ++++ + include/spirv/unified1/spirv.hpp | 27 ++++ + include/spirv/unified1/spirv.hpp11 | 27 ++++ + include/spirv/unified1/spirv.json | 10 ++ + include/spirv/unified1/spirv.lua | 10 ++ + include/spirv/unified1/spirv.py | 10 ++ + include/spirv/unified1/spv.d | 10 ++ + 10 files changed, 261 insertions(+) + +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index 1d5945a..630f2f4 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -655,6 +655,7 @@ namespace Spv + HostAccessINTEL = 6188, + InitModeINTEL = 6190, + ImplementInRegisterMapINTEL = 6191, ++ ConditionalINTEL = 6247, + CacheControlLoadINTEL = 6442, + CacheControlStoreINTEL = 6443, + Max = 0x7fffffff, +@@ -1312,6 +1313,8 @@ namespace Spv + Subgroup2DBlockTransposeINTEL = 6230, + SubgroupMatrixMultiplyAccumulateINTEL = 6236, + TernaryBitwiseFunctionINTEL = 6241, ++ SpecConditionalINTEL = 6245, ++ FunctionVariantsINTEL = 6246, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -2472,6 +2475,13 @@ namespace Spv + OpSubgroup2DBlockStoreINTEL = 6235, + OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, + OpBitwiseFunctionINTEL = 6242, ++ OpConditionalExtensionINTEL = 6248, ++ OpConditionalEntryPointINTEL = 6249, ++ OpConditionalCapabilityINTEL = 6250, ++ OpSpecConstantTargetINTEL = 6251, ++ OpSpecConstantArchitectureINTEL = 6252, ++ OpSpecConstantCapabilitiesINTEL = 6253, ++ OpConditionalCopyObjectINTEL = 6254, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index b197d9e..2470bfa 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -10777,6 +10777,101 @@ + "capabilities" : [ "TernaryBitwiseFunctionINTEL" ], + "version" : "None" + }, ++ { ++ "opname" : "OpConditionalExtensionINTEL", ++ "class" : "Extension", ++ "opcode" : 6248, ++ "operands" : [ ++ { "kind" : "IdRef", "name" : "Condition" }, ++ { "kind" : "LiteralString", "name" : "Name" } ++ ], ++ "capabilities" : [ "SpecConditionalINTEL" ], ++ "provisional" : true, ++ "version" : "None" ++ }, ++ { ++ "opname" : "OpConditionalEntryPointINTEL", ++ "class" : "Mode-Setting", ++ "opcode" : 6249, ++ "operands" : [ ++ { "kind" : "IdRef", "name" : "Condition" }, ++ { "kind" : "ExecutionModel" }, ++ { "kind" : "IdRef", "name" : "Entry Point" }, ++ { "kind" : "LiteralString", "name" : "Name" }, ++ { "kind" : "IdRef", "quantifier" : "*", "name" : "Interface" } ++ ], ++ "capabilities" : [ "SpecConditionalINTEL" ], ++ "provisional" : true, ++ "version" : "None" ++ }, ++ { ++ "opname" : "OpConditionalCapabilityINTEL", ++ "class" : "Mode-Setting", ++ "opcode" : 6250, ++ "operands" : [ ++ { "kind" : "IdRef", "name" : "Condition" }, ++ { "kind" : "Capability", "name" : "Capability" } ++ ], ++ "capabilities" : [ "SpecConditionalINTEL" ], ++ "provisional" : true, ++ "version" : "None" ++ }, ++ { ++ "opname" : "OpSpecConstantTargetINTEL", ++ "class" : "Constant-Creation", ++ "opcode" : 6251, ++ "operands" : [ ++ { "kind" : "IdResultType" }, ++ { "kind" : "IdResult" }, ++ { "kind" : "LiteralInteger", "name" : "Target" }, ++ { "kind" : "LiteralInteger", "quantifier" : "*", "name" : "Features" } ++ ], ++ "capabilities" : [ "FunctionVariantsINTEL" ], ++ "provisional" : true, ++ "version": "None" ++ }, ++ { ++ "opname" : "OpSpecConstantArchitectureINTEL", ++ "class" : "Constant-Creation", ++ "opcode" : 6252, ++ "operands" : [ ++ { "kind" : "IdResultType" }, ++ { "kind" : "IdResult" }, ++ { "kind" : "LiteralInteger", "name" : "Category" }, ++ { "kind" : "LiteralInteger", "name" : "Family" }, ++ { "kind" : "LiteralInteger", "name" : "Opcode" }, ++ { "kind" : "LiteralInteger", "name" : "Architecture" } ++ ], ++ "capabilities" : [ "FunctionVariantsINTEL" ], ++ "provisional" : true, ++ "version": "None" ++ }, ++ { ++ "opname" : "OpSpecConstantCapabilitiesINTEL", ++ "class" : "Constant-Creation", ++ "opcode" : 6253, ++ "operands" : [ ++ { "kind" : "IdResultType" }, ++ { "kind" : "IdResult" }, ++ { "kind" : "Capability", "quantifier" : "*", "name" : "Capabilities" } ++ ], ++ "capabilities" : [ "FunctionVariantsINTEL" ], ++ "provisional" : true, ++ "version": "None" ++ }, ++ { ++ "opname" : "OpConditionalCopyObjectINTEL", ++ "class" : "Composite", ++ "opcode" : 6254, ++ "operands" : [ ++ { "kind" : "IdResultType" }, ++ { "kind" : "IdResult" }, ++ { "kind" : "IdRef", "quantifier" : "*", "name" : "Condition 0, Operand 0, +\nCondition 1, Operand 1, +\n..." } ++ ], ++ "capabilities" : [ "SpecConditionalINTEL" ], ++ "provisional" : true, ++ "version" : "None" ++ }, + { + "opname" : "OpGroupIMulKHR", + "class" : "Group", +@@ -14900,6 +14995,16 @@ + "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ], + "version" : "None" + }, ++ { ++ "enumerant" : "ConditionalINTEL", ++ "value" : 6247, ++ "parameters": [ ++ { "kind" : "IdRef", "name" : "Condition" } ++ ], ++ "capabilities" : [ "SpecConditionalINTEL" ], ++ "provisional" : true, ++ "version" : "None" ++ }, + { + "enumerant" : "CacheControlLoadINTEL", + "value" : 6442, +@@ -17563,6 +17668,21 @@ + "extensions" : [ "SPV_INTEL_ternary_bitwise_function"], + "version" : "None" + }, ++ { ++ "enumerant" : "SpecConditionalINTEL", ++ "value" : 6245, ++ "extensions" : [ "SPV_INTEL_function_variants" ], ++ "provisional" : true, ++ "version": "None" ++ }, ++ { ++ "enumerant" : "FunctionVariantsINTEL", ++ "value" : 6246, ++ "capabilities" : [ "SpecConditionalINTEL" ], ++ "extensions" : [ "SPV_INTEL_function_variants" ], ++ "provisional" : true, ++ "version": "None" ++ }, + { + "enumerant" : "GroupUniformArithmeticKHR", + "value" : 6400, +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index b11a8b2..57e7216 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -654,6 +654,7 @@ namespace Spv + HostAccessINTEL = 6188, + InitModeINTEL = 6190, + ImplementInRegisterMapINTEL = 6191, ++ ConditionalINTEL = 6247, + CacheControlLoadINTEL = 6442, + CacheControlStoreINTEL = 6443, + Max = 0x7fffffff, +@@ -1311,6 +1312,8 @@ namespace Spv + Subgroup2DBlockTransposeINTEL = 6230, + SubgroupMatrixMultiplyAccumulateINTEL = 6236, + TernaryBitwiseFunctionINTEL = 6241, ++ SpecConditionalINTEL = 6245, ++ FunctionVariantsINTEL = 6246, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -2471,6 +2474,13 @@ namespace Spv + OpSubgroup2DBlockStoreINTEL = 6235, + OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, + OpBitwiseFunctionINTEL = 6242, ++ OpConditionalExtensionINTEL = 6248, ++ OpConditionalEntryPointINTEL = 6249, ++ OpConditionalCapabilityINTEL = 6250, ++ OpSpecConstantTargetINTEL = 6251, ++ OpSpecConstantArchitectureINTEL = 6252, ++ OpSpecConstantCapabilitiesINTEL = 6253, ++ OpConditionalCopyObjectINTEL = 6254, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index 005d451..84972da 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -642,6 +642,7 @@ typedef enum SpvDecoration_ { + SpvDecorationHostAccessINTEL = 6188, + SpvDecorationInitModeINTEL = 6190, + SpvDecorationImplementInRegisterMapINTEL = 6191, ++ SpvDecorationConditionalINTEL = 6247, + SpvDecorationCacheControlLoadINTEL = 6442, + SpvDecorationCacheControlStoreINTEL = 6443, + SpvDecorationMax = 0x7fffffff, +@@ -1282,6 +1283,8 @@ typedef enum SpvCapability_ { + SpvCapabilitySubgroup2DBlockTransposeINTEL = 6230, + SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236, + SpvCapabilityTernaryBitwiseFunctionINTEL = 6241, ++ SpvCapabilitySpecConditionalINTEL = 6245, ++ SpvCapabilityFunctionVariantsINTEL = 6246, + SpvCapabilityGroupUniformArithmeticKHR = 6400, + SpvCapabilityTensorFloat32RoundingINTEL = 6425, + SpvCapabilityMaskedGatherScatterINTEL = 6427, +@@ -2406,6 +2409,13 @@ typedef enum SpvOp_ { + SpvOpSubgroup2DBlockStoreINTEL = 6235, + SpvOpSubgroupMatrixMultiplyAccumulateINTEL = 6237, + SpvOpBitwiseFunctionINTEL = 6242, ++ SpvOpConditionalExtensionINTEL = 6248, ++ SpvOpConditionalEntryPointINTEL = 6249, ++ SpvOpConditionalCapabilityINTEL = 6250, ++ SpvOpSpecConstantTargetINTEL = 6251, ++ SpvOpSpecConstantArchitectureINTEL = 6252, ++ SpvOpSpecConstantCapabilitiesINTEL = 6253, ++ SpvOpConditionalCopyObjectINTEL = 6254, + SpvOpGroupIMulKHR = 6401, + SpvOpGroupFMulKHR = 6402, + SpvOpGroupBitwiseAndKHR = 6403, +@@ -3225,6 +3235,13 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy + case SpvOpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break; ++ case SpvOpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break; ++ case SpvOpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break; ++ case SpvOpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break; ++ case SpvOpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break; ++ case SpvOpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; ++ case SpvOpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; ++ case SpvOpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; + case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; + case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; +@@ -3765,6 +3782,7 @@ inline const char* SpvDecorationToString(SpvDecoration value) { + case SpvDecorationHostAccessINTEL: return "HostAccessINTEL"; + case SpvDecorationInitModeINTEL: return "InitModeINTEL"; + case SpvDecorationImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL"; ++ case SpvDecorationConditionalINTEL: return "ConditionalINTEL"; + case SpvDecorationCacheControlLoadINTEL: return "CacheControlLoadINTEL"; + case SpvDecorationCacheControlStoreINTEL: return "CacheControlStoreINTEL"; + default: return "Unknown"; +@@ -4204,6 +4222,8 @@ inline const char* SpvCapabilityToString(SpvCapability value) { + case SpvCapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL"; + case SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL"; + case SpvCapabilityTernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL"; ++ case SpvCapabilitySpecConditionalINTEL: return "SpecConditionalINTEL"; ++ case SpvCapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL"; + case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; + case SpvCapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; + case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; +@@ -5198,6 +5218,13 @@ inline const char* SpvOpToString(SpvOp value) { + case SpvOpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL"; + case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL"; + case SpvOpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL"; ++ case SpvOpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL"; ++ case SpvOpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL"; ++ case SpvOpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL"; ++ case SpvOpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL"; ++ case SpvOpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; ++ case SpvOpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; ++ case SpvOpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; + case SpvOpGroupIMulKHR: return "OpGroupIMulKHR"; + case SpvOpGroupFMulKHR: return "OpGroupFMulKHR"; + case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index f7a7bf8..a3d760a 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -638,6 +638,7 @@ enum Decoration { + DecorationHostAccessINTEL = 6188, + DecorationInitModeINTEL = 6190, + DecorationImplementInRegisterMapINTEL = 6191, ++ DecorationConditionalINTEL = 6247, + DecorationCacheControlLoadINTEL = 6442, + DecorationCacheControlStoreINTEL = 6443, + DecorationMax = 0x7fffffff, +@@ -1278,6 +1279,8 @@ enum Capability { + CapabilitySubgroup2DBlockTransposeINTEL = 6230, + CapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236, + CapabilityTernaryBitwiseFunctionINTEL = 6241, ++ CapabilitySpecConditionalINTEL = 6245, ++ CapabilityFunctionVariantsINTEL = 6246, + CapabilityGroupUniformArithmeticKHR = 6400, + CapabilityTensorFloat32RoundingINTEL = 6425, + CapabilityMaskedGatherScatterINTEL = 6427, +@@ -2402,6 +2405,13 @@ enum Op { + OpSubgroup2DBlockStoreINTEL = 6235, + OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, + OpBitwiseFunctionINTEL = 6242, ++ OpConditionalExtensionINTEL = 6248, ++ OpConditionalEntryPointINTEL = 6249, ++ OpConditionalCapabilityINTEL = 6250, ++ OpSpecConstantTargetINTEL = 6251, ++ OpSpecConstantArchitectureINTEL = 6252, ++ OpSpecConstantCapabilitiesINTEL = 6253, ++ OpConditionalCopyObjectINTEL = 6254, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +@@ -3221,6 +3231,13 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { + case OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break; + case OpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break; + case OpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break; ++ case OpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break; ++ case OpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break; ++ case OpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break; ++ case OpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break; ++ case OpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; ++ case OpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; ++ case OpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; + case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; + case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; + case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; +@@ -3761,6 +3778,7 @@ inline const char* DecorationToString(Decoration value) { + case DecorationHostAccessINTEL: return "HostAccessINTEL"; + case DecorationInitModeINTEL: return "InitModeINTEL"; + case DecorationImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL"; ++ case DecorationConditionalINTEL: return "ConditionalINTEL"; + case DecorationCacheControlLoadINTEL: return "CacheControlLoadINTEL"; + case DecorationCacheControlStoreINTEL: return "CacheControlStoreINTEL"; + default: return "Unknown"; +@@ -4200,6 +4218,8 @@ inline const char* CapabilityToString(Capability value) { + case CapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL"; + case CapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL"; + case CapabilityTernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL"; ++ case CapabilitySpecConditionalINTEL: return "SpecConditionalINTEL"; ++ case CapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL"; + case CapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; + case CapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; + case CapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; +@@ -5194,6 +5214,13 @@ inline const char* OpToString(Op value) { + case OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL"; + case OpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL"; + case OpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL"; ++ case OpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL"; ++ case OpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL"; ++ case OpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL"; ++ case OpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL"; ++ case OpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; ++ case OpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; ++ case OpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; + case OpGroupIMulKHR: return "OpGroupIMulKHR"; + case OpGroupFMulKHR: return "OpGroupFMulKHR"; + case OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index b83ca46..e8479cb 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -638,6 +638,7 @@ enum class Decoration : unsigned { + HostAccessINTEL = 6188, + InitModeINTEL = 6190, + ImplementInRegisterMapINTEL = 6191, ++ ConditionalINTEL = 6247, + CacheControlLoadINTEL = 6442, + CacheControlStoreINTEL = 6443, + Max = 0x7fffffff, +@@ -1278,6 +1279,8 @@ enum class Capability : unsigned { + Subgroup2DBlockTransposeINTEL = 6230, + SubgroupMatrixMultiplyAccumulateINTEL = 6236, + TernaryBitwiseFunctionINTEL = 6241, ++ SpecConditionalINTEL = 6245, ++ FunctionVariantsINTEL = 6246, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -2402,6 +2405,13 @@ enum class Op : unsigned { + OpSubgroup2DBlockStoreINTEL = 6235, + OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, + OpBitwiseFunctionINTEL = 6242, ++ OpConditionalExtensionINTEL = 6248, ++ OpConditionalEntryPointINTEL = 6249, ++ OpConditionalCapabilityINTEL = 6250, ++ OpSpecConstantTargetINTEL = 6251, ++ OpSpecConstantArchitectureINTEL = 6252, ++ OpSpecConstantCapabilitiesINTEL = 6253, ++ OpConditionalCopyObjectINTEL = 6254, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +@@ -3221,6 +3231,13 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { + case Op::OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break; ++ case Op::OpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break; ++ case Op::OpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break; ++ case Op::OpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break; ++ case Op::OpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break; ++ case Op::OpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; ++ case Op::OpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; ++ case Op::OpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; + case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; + case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; +@@ -3761,6 +3778,7 @@ inline const char* DecorationToString(Decoration value) { + case Decoration::HostAccessINTEL: return "HostAccessINTEL"; + case Decoration::InitModeINTEL: return "InitModeINTEL"; + case Decoration::ImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL"; ++ case Decoration::ConditionalINTEL: return "ConditionalINTEL"; + case Decoration::CacheControlLoadINTEL: return "CacheControlLoadINTEL"; + case Decoration::CacheControlStoreINTEL: return "CacheControlStoreINTEL"; + default: return "Unknown"; +@@ -4200,6 +4218,8 @@ inline const char* CapabilityToString(Capability value) { + case Capability::Subgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL"; + case Capability::SubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL"; + case Capability::TernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL"; ++ case Capability::SpecConditionalINTEL: return "SpecConditionalINTEL"; ++ case Capability::FunctionVariantsINTEL: return "FunctionVariantsINTEL"; + case Capability::GroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; + case Capability::TensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; + case Capability::MaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; +@@ -5194,6 +5214,13 @@ inline const char* OpToString(Op value) { + case Op::OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL"; + case Op::OpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL"; + case Op::OpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL"; ++ case Op::OpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL"; ++ case Op::OpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL"; ++ case Op::OpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL"; ++ case Op::OpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL"; ++ case Op::OpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; ++ case Op::OpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; ++ case Op::OpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; + case Op::OpGroupIMulKHR: return "OpGroupIMulKHR"; + case Op::OpGroupFMulKHR: return "OpGroupFMulKHR"; + case Op::OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index 0668c98..e0c0230 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -661,6 +661,7 @@ + "HostAccessINTEL": 6188, + "InitModeINTEL": 6190, + "ImplementInRegisterMapINTEL": 6191, ++ "ConditionalINTEL": 6247, + "CacheControlLoadINTEL": 6442, + "CacheControlStoreINTEL": 6443 + } +@@ -1254,6 +1255,8 @@ + "Subgroup2DBlockTransposeINTEL": 6230, + "SubgroupMatrixMultiplyAccumulateINTEL": 6236, + "TernaryBitwiseFunctionINTEL": 6241, ++ "SpecConditionalINTEL": 6245, ++ "FunctionVariantsINTEL": 6246, + "GroupUniformArithmeticKHR": 6400, + "TensorFloat32RoundingINTEL": 6425, + "MaskedGatherScatterINTEL": 6427, +@@ -2383,6 +2386,13 @@ + "OpSubgroup2DBlockStoreINTEL": 6235, + "OpSubgroupMatrixMultiplyAccumulateINTEL": 6237, + "OpBitwiseFunctionINTEL": 6242, ++ "OpConditionalExtensionINTEL": 6248, ++ "OpConditionalEntryPointINTEL": 6249, ++ "OpConditionalCapabilityINTEL": 6250, ++ "OpSpecConstantTargetINTEL": 6251, ++ "OpSpecConstantArchitectureINTEL": 6252, ++ "OpSpecConstantCapabilitiesINTEL": 6253, ++ "OpConditionalCopyObjectINTEL": 6254, + "OpGroupIMulKHR": 6401, + "OpGroupFMulKHR": 6402, + "OpGroupBitwiseAndKHR": 6403, +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index a612e5c..410060b 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -629,6 +629,7 @@ spv = { + HostAccessINTEL = 6188, + InitModeINTEL = 6190, + ImplementInRegisterMapINTEL = 6191, ++ ConditionalINTEL = 6247, + CacheControlLoadINTEL = 6442, + CacheControlStoreINTEL = 6443, + Max = 0x7fffffff, +@@ -1269,6 +1270,8 @@ spv = { + Subgroup2DBlockTransposeINTEL = 6230, + SubgroupMatrixMultiplyAccumulateINTEL = 6236, + TernaryBitwiseFunctionINTEL = 6241, ++ SpecConditionalINTEL = 6245, ++ FunctionVariantsINTEL = 6246, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -2393,6 +2396,13 @@ spv = { + OpSubgroup2DBlockStoreINTEL = 6235, + OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, + OpBitwiseFunctionINTEL = 6242, ++ OpConditionalExtensionINTEL = 6248, ++ OpConditionalEntryPointINTEL = 6249, ++ OpConditionalCapabilityINTEL = 6250, ++ OpSpecConstantTargetINTEL = 6251, ++ OpSpecConstantArchitectureINTEL = 6252, ++ OpSpecConstantCapabilitiesINTEL = 6253, ++ OpConditionalCopyObjectINTEL = 6254, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index 5adfded..0b77b4f 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -611,6 +611,7 @@ spv = { + 'HostAccessINTEL' : 6188, + 'InitModeINTEL' : 6190, + 'ImplementInRegisterMapINTEL' : 6191, ++ 'ConditionalINTEL' : 6247, + 'CacheControlLoadINTEL' : 6442, + 'CacheControlStoreINTEL' : 6443, + }, +@@ -1240,6 +1241,8 @@ spv = { + 'Subgroup2DBlockTransposeINTEL' : 6230, + 'SubgroupMatrixMultiplyAccumulateINTEL' : 6236, + 'TernaryBitwiseFunctionINTEL' : 6241, ++ 'SpecConditionalINTEL' : 6245, ++ 'FunctionVariantsINTEL' : 6246, + 'GroupUniformArithmeticKHR' : 6400, + 'TensorFloat32RoundingINTEL' : 6425, + 'MaskedGatherScatterINTEL' : 6427, +@@ -2336,6 +2339,13 @@ spv = { + 'OpSubgroup2DBlockStoreINTEL' : 6235, + 'OpSubgroupMatrixMultiplyAccumulateINTEL' : 6237, + 'OpBitwiseFunctionINTEL' : 6242, ++ 'OpConditionalExtensionINTEL' : 6248, ++ 'OpConditionalEntryPointINTEL' : 6249, ++ 'OpConditionalCapabilityINTEL' : 6250, ++ 'OpSpecConstantTargetINTEL' : 6251, ++ 'OpSpecConstantArchitectureINTEL' : 6252, ++ 'OpSpecConstantCapabilitiesINTEL' : 6253, ++ 'OpConditionalCopyObjectINTEL' : 6254, + 'OpGroupIMulKHR' : 6401, + 'OpGroupFMulKHR' : 6402, + 'OpGroupBitwiseAndKHR' : 6403, +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index 3c5130a..a5763e6 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -657,6 +657,7 @@ enum Decoration : uint + HostAccessINTEL = 6188, + InitModeINTEL = 6190, + ImplementInRegisterMapINTEL = 6191, ++ ConditionalINTEL = 6247, + CacheControlLoadINTEL = 6442, + CacheControlStoreINTEL = 6443, + Max = 0x7fffffff, +@@ -1314,6 +1315,8 @@ enum Capability : uint + Subgroup2DBlockTransposeINTEL = 6230, + SubgroupMatrixMultiplyAccumulateINTEL = 6236, + TernaryBitwiseFunctionINTEL = 6241, ++ SpecConditionalINTEL = 6245, ++ FunctionVariantsINTEL = 6246, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -2474,6 +2477,13 @@ enum Op : uint + OpSubgroup2DBlockStoreINTEL = 6235, + OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, + OpBitwiseFunctionINTEL = 6242, ++ OpConditionalExtensionINTEL = 6248, ++ OpConditionalEntryPointINTEL = 6249, ++ OpConditionalCapabilityINTEL = 6250, ++ OpSpecConstantTargetINTEL = 6251, ++ OpSpecConstantArchitectureINTEL = 6252, ++ OpSpecConstantCapabilitiesINTEL = 6253, ++ OpConditionalCopyObjectINTEL = 6254, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, diff --git a/meta/recipes-graphics/spir/spirv-headers_1.4.321.0.bb b/meta/recipes-graphics/spir/spirv-headers_1.4.321.0.bb index 5365d64a999..807e34abcc2 100644 --- a/meta/recipes-graphics/spir/spirv-headers_1.4.321.0.bb +++ b/meta/recipes-graphics/spir/spirv-headers_1.4.321.0.bb @@ -5,7 +5,9 @@ LICENSE = "MIT & CC-BY-4.0" LIC_FILES_CHKSUM = "file://LICENSE;md5=a0dcaa512cc2dee95fe0fd791ee83a18" SRCREV = "2a611a970fdbc41ac2e3e328802aed9985352dca" -SRC_URI = "git://github.com/KhronosGroup/SPIRV-Headers;protocol=https;branch=main" +SRC_URI = "git://github.com/KhronosGroup/SPIRV-Headers;protocol=https;branch=main \ + file://0001-Add-SPV_INTEL_function_variants-532.patch \ + " PE = "1" # These recipes need to be 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<20250819010128.3519760-1-raj.khem@gmail.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 19 Aug 2025 01:01:39 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/222058 Needed for compiling clang-21 Signed-off-by: Khem Raj --- ...on_variants-basic-asm-dis-support-61.patch | 289 ++++++++++++++++++ .../spir/spirv-tools_1.4.321.0.bb | 1 + 2 files changed, 290 insertions(+) create mode 100644 meta/recipes-graphics/spir/spirv-tools/0001-SPV_INTEL_function_variants-basic-asm-dis-support-61.patch diff --git a/meta/recipes-graphics/spir/spirv-tools/0001-SPV_INTEL_function_variants-basic-asm-dis-support-61.patch b/meta/recipes-graphics/spir/spirv-tools/0001-SPV_INTEL_function_variants-basic-asm-dis-support-61.patch new file mode 100644 index 00000000000..d4ca23c7295 --- /dev/null +++ b/meta/recipes-graphics/spir/spirv-tools/0001-SPV_INTEL_function_variants-basic-asm-dis-support-61.patch @@ -0,0 +1,289 @@ +From 28a883ba4c67f58a9540fb0651c647bb02883622 Mon Sep 17 00:00:00 2001 +From: David Neto +Date: Wed, 25 Jun 2025 11:27:23 -0400 +Subject: [PATCH] SPV_INTEL_function_variants: basic asm, dis support (#6195) + +The challenging part is that there are instructions that +take zero or more Capability operands. So we have to introduce +SPV_TYPE_OPERAND_VARIABLE_CAPABILITY and SPV_TYPE_OPERAND_OPTIONAL_CAPABILITY. + +Remove deprecated enums for the first and last variable or optional +enums. +Upstream-Status: Backport [https://github.com/KhronosGroup/SPIRV-Tools/commit/28a883ba4c67f58a9540fb0651c647bb02883622] +Signed-off-by: Khem Raj +--- + DEPS | 2 +- + include/spirv-tools/libspirv.h | 48 +++++++---------- + source/binary.cpp | 3 ++ + source/disassemble.cpp | 1 + + source/operand.cpp | 7 +++ + test/text_to_binary.extension_test.cpp | 73 ++++++++++++++++++++++++++ + utils/ggt.py | 3 +- + 7 files changed, 107 insertions(+), 30 deletions(-) + +diff --git a/DEPS b/DEPS +index e25ca513..511fd718 100644 +--- a/DEPS ++++ b/DEPS +@@ -14,7 +14,7 @@ vars = { + + 're2_revision': 'c84a140c93352cdabbfb547c531be34515b12228', + +- 'spirv_headers_revision': '2a611a970fdbc41ac2e3e328802aed9985352dca', ++ 'spirv_headers_revision': '9e3836d7d6023843a72ecd3fbf3f09b1b6747a9e', + + 'mimalloc_revision': '09a27098aa6e9286518bd9c74e6ffa7199c3f04e', + } +diff --git a/include/spirv-tools/libspirv.h b/include/spirv-tools/libspirv.h +index a2a032a0..2a604e94 100644 +--- a/include/spirv-tools/libspirv.h ++++ b/include/spirv-tools/libspirv.h +@@ -189,36 +189,24 @@ typedef enum spv_operand_type_t { + SPV_OPERAND_TYPE_MEMORY_ACCESS, // SPIR-V Sec 3.26 + SPV_OPERAND_TYPE_FRAGMENT_SHADING_RATE, // SPIR-V Sec 3.FSR + +-// NOTE: New concrete enum values should be added at the end. +- +-// The "optional" and "variable" operand types are only used internally by +-// the assembler and the binary parser. +-// There are two categories: +-// Optional : expands to 0 or 1 operand, like ? in regular expressions. +-// Variable : expands to 0, 1 or many operands or pairs of operands. +-// This is similar to * in regular expressions. +- +-// NOTE: These FIRST_* and LAST_* enum values are DEPRECATED. +-// The concept of "optional" and "variable" operand types are only intended +-// for use as an implementation detail of parsing SPIR-V, either in text or +-// binary form. Instead of using enum ranges, use characteristic function +-// spvOperandIsConcrete. +-// The use of enum value ranges in a public API makes it difficult to insert +-// new values into a range without also breaking binary compatibility. +-// +-// Macros for defining bounds on optional and variable operand types. +-// Any variable operand type is also optional. +-// TODO(dneto): Remove SPV_OPERAND_TYPE_FIRST_* and SPV_OPERAND_TYPE_LAST_* +-#define FIRST_OPTIONAL(ENUM) ENUM, SPV_OPERAND_TYPE_FIRST_OPTIONAL_TYPE = ENUM +-#define FIRST_VARIABLE(ENUM) ENUM, SPV_OPERAND_TYPE_FIRST_VARIABLE_TYPE = ENUM +-#define LAST_VARIABLE(ENUM) \ +- ENUM, SPV_OPERAND_TYPE_LAST_VARIABLE_TYPE = ENUM, \ +- SPV_OPERAND_TYPE_LAST_OPTIONAL_TYPE = ENUM ++ // NOTE: New concrete enum values should be added at the end. ++ ++ // The "optional" and "variable" operand types are only used internally by ++ // the assembler and the binary parser. ++ // There are two categories: ++ // Optional : expands to 0 or 1 operand, like ? in regular expressions. ++ // Variable : expands to 0, 1 or many operands or pairs of operands. ++ // This is similar to * in regular expressions. ++ ++ // Use characteristic function spvOperandIsConcrete to classify the ++ // operand types; when it returns false, the operand is optional or variable. ++ // ++ // Any variable operand type is also optional. + + // An optional operand represents zero or one logical operands. + // In an instruction definition, this may only appear at the end of the + // operand types. +- FIRST_OPTIONAL(SPV_OPERAND_TYPE_OPTIONAL_ID), ++ SPV_OPERAND_TYPE_OPTIONAL_ID, + // An optional image operand type. + SPV_OPERAND_TYPE_OPTIONAL_IMAGE, + // An optional memory access type. +@@ -243,7 +231,7 @@ typedef enum spv_operand_type_t { + // A variable operand represents zero or more logical operands. + // In an instruction definition, this may only appear at the end of the + // operand types. +- FIRST_VARIABLE(SPV_OPERAND_TYPE_VARIABLE_ID), ++ SPV_OPERAND_TYPE_VARIABLE_ID, + SPV_OPERAND_TYPE_VARIABLE_LITERAL_INTEGER, + // A sequence of zero or more pairs of (typed literal integer, Id). + // Expands to zero or more: +@@ -251,7 +239,7 @@ typedef enum spv_operand_type_t { + // where the literal number must always be an integer of some sort. + SPV_OPERAND_TYPE_VARIABLE_LITERAL_INTEGER_ID, + // A sequence of zero or more pairs of (Id, Literal integer) +- LAST_VARIABLE(SPV_OPERAND_TYPE_VARIABLE_ID_LITERAL_INTEGER), ++ SPV_OPERAND_TYPE_VARIABLE_ID_LITERAL_INTEGER, + + // The following are concrete enum types from the DebugInfo extended + // instruction set. +@@ -343,6 +331,10 @@ typedef enum spv_operand_type_t { + SPV_OPERAND_TYPE_TENSOR_OPERANDS, + SPV_OPERAND_TYPE_OPTIONAL_TENSOR_OPERANDS, + ++ // SPV_INTEL_function_variants ++ SPV_OPERAND_TYPE_OPTIONAL_CAPABILITY, ++ SPV_OPERAND_TYPE_VARIABLE_CAPABILITY, ++ + // This is a sentinel value, and does not represent an operand type. + // It should come last. + SPV_OPERAND_TYPE_NUM_OPERAND_TYPES, +diff --git a/source/binary.cpp b/source/binary.cpp +index 180d0a99..8e4d899f 100644 +--- a/source/binary.cpp ++++ b/source/binary.cpp +@@ -636,6 +636,7 @@ spv_result_t Parser::parseOperand(size_t inst_offset, + } break; + + case SPV_OPERAND_TYPE_CAPABILITY: ++ case SPV_OPERAND_TYPE_OPTIONAL_CAPABILITY: + case SPV_OPERAND_TYPE_EXECUTION_MODEL: + case SPV_OPERAND_TYPE_ADDRESSING_MODEL: + case SPV_OPERAND_TYPE_MEMORY_MODEL: +@@ -689,6 +690,8 @@ spv_result_t Parser::parseOperand(size_t inst_offset, + parsed_operand.type = SPV_OPERAND_TYPE_PACKED_VECTOR_FORMAT; + if (type == SPV_OPERAND_TYPE_OPTIONAL_FPENCODING) + parsed_operand.type = SPV_OPERAND_TYPE_FPENCODING; ++ if (type == SPV_OPERAND_TYPE_OPTIONAL_CAPABILITY) ++ parsed_operand.type = SPV_OPERAND_TYPE_CAPABILITY; + + const spvtools::OperandDesc* entry = nullptr; + if (spvtools::LookupOperand(type, word, &entry)) { +diff --git a/source/disassemble.cpp b/source/disassemble.cpp +index 2d9bb0ff..4267333a 100644 +--- a/source/disassemble.cpp ++++ b/source/disassemble.cpp +@@ -907,6 +907,7 @@ void InstructionDisassembler::EmitOperand(std::ostream& stream, + stream << '"'; + } break; + case SPV_OPERAND_TYPE_CAPABILITY: ++ case SPV_OPERAND_TYPE_OPTIONAL_CAPABILITY: + case SPV_OPERAND_TYPE_SOURCE_LANGUAGE: + case SPV_OPERAND_TYPE_EXECUTION_MODEL: + case SPV_OPERAND_TYPE_ADDRESSING_MODEL: +diff --git a/source/operand.cpp b/source/operand.cpp +index c635c72d..d7fc535c 100644 +--- a/source/operand.cpp ++++ b/source/operand.cpp +@@ -111,6 +111,7 @@ const char* spvOperandTypeStr(spv_operand_type_t type) { + case SPV_OPERAND_TYPE_KERNEL_PROFILING_INFO: + return "kernel profiling info"; + case SPV_OPERAND_TYPE_CAPABILITY: ++ case SPV_OPERAND_TYPE_OPTIONAL_CAPABILITY: + return "capability"; + case SPV_OPERAND_TYPE_RAY_FLAGS: + return "ray flags"; +@@ -394,6 +395,7 @@ bool spvOperandIsOptional(spv_operand_type_t type) { + case SPV_OPERAND_TYPE_OPTIONAL_RAW_ACCESS_CHAIN_OPERANDS: + case SPV_OPERAND_TYPE_OPTIONAL_FPENCODING: + case SPV_OPERAND_TYPE_OPTIONAL_TENSOR_OPERANDS: ++ case SPV_OPERAND_TYPE_OPTIONAL_CAPABILITY: + return true; + default: + break; +@@ -408,6 +410,7 @@ bool spvOperandIsVariable(spv_operand_type_t type) { + case SPV_OPERAND_TYPE_VARIABLE_LITERAL_INTEGER: + case SPV_OPERAND_TYPE_VARIABLE_LITERAL_INTEGER_ID: + case SPV_OPERAND_TYPE_VARIABLE_ID_LITERAL_INTEGER: ++ case SPV_OPERAND_TYPE_VARIABLE_CAPABILITY: + return true; + default: + break; +@@ -439,6 +442,10 @@ bool spvExpandOperandSequenceOnce(spv_operand_type_t type, + pattern->push_back(SPV_OPERAND_TYPE_LITERAL_INTEGER); + pattern->push_back(SPV_OPERAND_TYPE_OPTIONAL_ID); + return true; ++ case SPV_OPERAND_TYPE_VARIABLE_CAPABILITY: ++ pattern->push_back(type); ++ pattern->push_back(SPV_OPERAND_TYPE_OPTIONAL_CAPABILITY); ++ return true; + default: + break; + } +diff --git a/test/text_to_binary.extension_test.cpp b/test/text_to_binary.extension_test.cpp +index 65079d1b..39accfc1 100644 +--- a/test/text_to_binary.extension_test.cpp ++++ b/test/text_to_binary.extension_test.cpp +@@ -1495,5 +1495,78 @@ INSTANTIATE_TEST_SUITE_P( + SaturatedToLargestFloat8NormalConversionEXT)})}, + }))); + ++// SPV_INTEL_function_variants ++// https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_function_variants.asciidoc ++INSTANTIATE_TEST_SUITE_P( ++ SPV_INTEL_function_variants, ExtensionRoundTripTest, ++ Combine( ++ Values(SPV_ENV_UNIVERSAL_1_0, SPV_ENV_UNIVERSAL_1_6), ++ ValuesIn(std::vector{ ++ {"OpExtension \"SPV_INTEL_function_variants\"\n", ++ MakeInstruction(spv::Op::OpExtension, ++ MakeVector("SPV_INTEL_function_variants"))}, ++ {"OpCapability SpecConditionalINTEL\n", ++ MakeInstruction( ++ spv::Op::OpCapability, ++ {(uint32_t)spv::Capability::SpecConditionalINTEL})}, ++ {"OpCapability FunctionVariantsINTEL\n", ++ MakeInstruction( ++ spv::Op::OpCapability, ++ {(uint32_t)spv::Capability::FunctionVariantsINTEL})}, ++ {"OpDecorate %1 ConditionalINTEL %2\n", ++ MakeInstruction(spv::Op::OpDecorate, ++ {1, (uint32_t)spv::Decoration::ConditionalINTEL, ++ 2})}, ++ ++ {"OpConditionalExtensionINTEL %1 \"foo\"\n", ++ MakeInstruction(spv::Op::OpConditionalExtensionINTEL, {1}, ++ MakeVector("foo"))}, ++ ++ {"OpConditionalEntryPointINTEL %1 Kernel %2 \"foo\"\n", ++ MakeInstruction(spv::Op::OpConditionalEntryPointINTEL, ++ {1, (uint32_t)spv::ExecutionModel::Kernel, 2}, ++ MakeVector("foo"))}, ++ ++ {"OpConditionalCapabilityINTEL %1 Kernel\n", ++ MakeInstruction(spv::Op::OpConditionalCapabilityINTEL, ++ {1, (uint32_t)spv::ExecutionModel::Kernel})}, ++ ++ {"%2 = OpSpecConstantTargetINTEL %1 42\n", ++ MakeInstruction(spv::Op::OpSpecConstantTargetINTEL, {1, 2, 42})}, ++ ++ {"%2 = OpSpecConstantTargetINTEL %1 42 99\n", ++ MakeInstruction(spv::Op::OpSpecConstantTargetINTEL, ++ {1, 2, 42, 99})}, ++ ++ {"%2 = OpSpecConstantTargetINTEL %1 42 99 108\n", ++ MakeInstruction(spv::Op::OpSpecConstantTargetINTEL, ++ {1, 2, 42, 99, 108})}, ++ ++ {"%2 = OpSpecConstantArchitectureINTEL %1 42 99 108 72\n", ++ MakeInstruction(spv::Op::OpSpecConstantArchitectureINTEL, ++ {1, 2, 42, 99, 108, 72})}, ++ ++ {"%2 = OpSpecConstantCapabilitiesINTEL %1\n", ++ MakeInstruction(spv::Op::OpSpecConstantCapabilitiesINTEL, {1, 2})}, ++ ++ {"%2 = OpSpecConstantCapabilitiesINTEL %1 Kernel\n", ++ MakeInstruction(spv::Op::OpSpecConstantCapabilitiesINTEL, ++ {1, 2, (uint32_t)spv::Capability::Kernel})}, ++ ++ {"%2 = OpSpecConstantCapabilitiesINTEL %1 Kernel Shader\n", ++ MakeInstruction(spv::Op::OpSpecConstantCapabilitiesINTEL, ++ {1, 2, (uint32_t)spv::Capability::Kernel, ++ (uint32_t)spv::Capability::Shader})}, ++ ++ {"%2 = OpConditionalCopyObjectINTEL %1 %3 %4\n", ++ MakeInstruction(spv::Op::OpConditionalCopyObjectINTEL, ++ {1, 2, 3, 4})}, ++ ++ {"%2 = OpConditionalCopyObjectINTEL %1 %3 %4 %5 %6\n", ++ MakeInstruction(spv::Op::OpConditionalCopyObjectINTEL, ++ {1, 2, 3, 4, 5, 6})}, ++ ++ }))); ++ + } // namespace + } // namespace spvtools +diff --git a/utils/ggt.py b/utils/ggt.py +index 258c1b00..45262ba8 100755 +--- a/utils/ggt.py ++++ b/utils/ggt.py +@@ -242,7 +242,8 @@ class Grammar(): + 'MatrixMultiplyAccumulateOperands', + 'RawAccessChainOperands', + 'FPEncoding', +- 'TensorOperands'] ++ 'TensorOperands', ++ 'Capability'] + + def dump(self) -> None: + self.context.dump() diff --git a/meta/recipes-graphics/spir/spirv-tools_1.4.321.0.bb b/meta/recipes-graphics/spir/spirv-tools_1.4.321.0.bb index 319b25b7f43..30c42e915f9 100644 --- a/meta/recipes-graphics/spir/spirv-tools_1.4.321.0.bb +++ b/meta/recipes-graphics/spir/spirv-tools_1.4.321.0.bb @@ -9,6 +9,7 @@ LIC_FILES_CHKSUM = "file://LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57" SRCREV = "33e02568181e3312f49a3cf33df470bf96ef293a" SRC_URI = "git://github.com/KhronosGroup/SPIRV-Tools.git;branch=main;protocol=https \ + file://0001-SPV_INTEL_function_variants-basic-asm-dis-support-61.patch \ " PE = "1" # These recipes need to be updated in lockstep with each other: From patchwork Tue Aug 19 01:01:28 2025 Content-Type: text/plain; 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Mon, 18 Aug 2025 18:01:34 -0700 (PDT) Received: from apollo.tail3ccdd3.ts.net ([2601:646:8201:fd20::adc2]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76e7d544de1sm777859b3a.94.2025.08.18.18.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:01:33 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Cc: Khem Raj Subject: [PATCH 3/3] m4: Fix ptest on musl Date: Mon, 18 Aug 2025 18:01:28 -0700 Message-ID: <20250819010128.3519760-3-raj.khem@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819010128.3519760-1-raj.khem@gmail.com> References: <20250819010128.3519760-1-raj.khem@gmail.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 19 Aug 2025 01:01:39 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/222059 Fixes ../../sources/m4-1.4.20/tests/test-c32ispunct.c:261: assertion 'is == 0' failed ./test-c32ispunct.sh: line 36: 402 Aborted (core dumped) LC_ALL="$testlocale" ${CHECKER} ./test-c32ispunct${EXEEXT} 3 FAIL: test-c32ispunct.sh Signed-off-by: Khem Raj --- meta/recipes-devtools/m4/m4-1.4.20.inc | 1 + ...unct-Check-for-musl-along-with-glibc.patch | 26 +++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 meta/recipes-devtools/m4/m4/0001-test-c32ispunct-Check-for-musl-along-with-glibc.patch diff --git a/meta/recipes-devtools/m4/m4-1.4.20.inc b/meta/recipes-devtools/m4/m4-1.4.20.inc index aad57b8b649..0a7e018d296 100644 --- a/meta/recipes-devtools/m4/m4-1.4.20.inc +++ b/meta/recipes-devtools/m4/m4-1.4.20.inc @@ -8,6 +8,7 @@ inherit autotools texinfo ptest gettext SRC_URI = "${GNU_MIRROR}/m4/m4-${PV}.tar.gz \ file://0001-gettext-h-Avoid-gcc-Wformat-security-warnings-with-d.patch \ + file://0001-test-c32ispunct-Check-for-musl-along-with-glibc.patch \ " SRC_URI:append:class-target = " file://run-ptest \ file://serial-tests-config.patch \ diff --git a/meta/recipes-devtools/m4/m4/0001-test-c32ispunct-Check-for-musl-along-with-glibc.patch b/meta/recipes-devtools/m4/m4/0001-test-c32ispunct-Check-for-musl-along-with-glibc.patch new file mode 100644 index 00000000000..fb03e94c52d --- /dev/null +++ b/meta/recipes-devtools/m4/m4/0001-test-c32ispunct-Check-for-musl-along-with-glibc.patch @@ -0,0 +1,26 @@ +From 761aa7fab4a82dc01daa28799f4f1d6ae17a4c26 Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Mon, 18 Aug 2025 11:31:32 -0700 +Subject: [PATCH] test-c32ispunct: Check for musl along with glibc + +This check crashes on musl based locales, other libcs +e.g. glibc ignore it too. + +Upstream-Status: Submitted [https://lists.gnu.org/archive/html/m4-patches/2025-08/msg00000.html] + +Signed-off-by: Khem Raj +--- + tests/test-c32ispunct.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/tests/test-c32ispunct.c ++++ b/tests/test-c32ispunct.c +@@ -255,7 +255,7 @@ main (int argc, char *argv[]) + is = for_character ("\360\235\204\200", 4); + ASSERT (is != 0); + #endif +- #if !(defined __GLIBC__ || (defined __APPLE__ && defined __MACH__) || defined __FreeBSD__ || defined __NetBSD__ || defined __OpenBSD__ || defined _AIX || defined __sun || defined __CYGWIN__ || (defined _WIN32 && !defined __CYGWIN__) || defined __ANDROID__) ++ #if !(defined __GLIBC__ || defined MUSL_LIBC || (defined __APPLE__ && defined __MACH__) || defined __FreeBSD__ || defined __NetBSD__ || defined __OpenBSD__ || defined _AIX || defined __sun || defined __CYGWIN__ || (defined _WIN32 && !defined __CYGWIN__) || defined __ANDROID__) + /* U+E003A TAG COLON */ + is = for_character ("\363\240\200\272", 4); + ASSERT (is == 0);