From patchwork Wed Jul 16 10:28:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TWFjcGF1bCBMaW4gKOael+aZuuaWjCk=?= X-Patchwork-Id: 66959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BEFFC83F1B for ; Wed, 16 Jul 2025 10:29:25 +0000 (UTC) Received: from mailgw02.mediatek.com (mailgw02.mediatek.com [210.61.82.184]) by mx.groups.io with SMTP id smtpd.web10.18942.1752661755315659985 for ; Wed, 16 Jul 2025 03:29:15 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@mediatek.com header.s=dk header.b=dGjcCQwn; spf=pass (domain: mediatek.com, ip: 210.61.82.184, mailfrom: macpaul.lin@mediatek.com) X-UUID: b51081ee622f11f0b33aeb1e7f16c2b6-20250716 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=47DSmbpAEvdNnkdmmTBwsL5yTco8H3BTdt/jhcrSUBw=; b=dGjcCQwnTpQZA88uayD+pOiZt3iqocExF2ha0PcMsUzfvpHy/06TaPiTy6m+s1w+CPO3XrVD/94O+gqzW25D67TAz3UCHN4U5TkWNlGjNIN/j55TIBB9GKRPC6wBCuWKBv4H6ZMNePDHHpdB/EA7gs6ir162lunTAjya+Ej/ZTo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.2,REQID:952e2e1d-51c2-4e26-8f3f-ccb5d413a5b6,IP:0,UR L:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:-5 X-CID-META: VersionHash:9eb4ff7,CLOUDID:e51c1373-f565-4a89-86be-304708e7ad47,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0|50,EDM:-3,IP:ni l,URL:99|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0, LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: b51081ee622f11f0b33aeb1e7f16c2b6-20250716 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1060070217; Wed, 16 Jul 2025 18:29:08 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Wed, 16 Jul 2025 18:29:07 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Wed, 16 Jul 2025 18:29:06 +0800 From: Macpaul Lin To: , , , Catalin Marinas , Will Deacon , Matthias Brugger , AngeloGioacchino Del Regno , Sasha Levin , =?utf-8?q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_P?= =?utf-8?q?rado?= , , , CC: Bear Wang , Pablo Sun , Macpaul Lin , Macpaul Lin , MediaTek Chromebook Upstream , Dmitry Baryshkov , Neil Armstrong , Bjorn Andersson Subject: [PATCH 6.12 1/2] arm64: defconfig: enable DRM_DISPLAY_CONNECTOR as a module Date: Wed, 16 Jul 2025 18:28:53 +0800 Message-ID: <20250716102854.4012956-1-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-MTK: N List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 16 Jul 2025 10:29:25 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/220444 From: Dmitry Baryshkov [ Upstream commit 691b5b53dbcc30bb3572cbb255374990723af0d2 ] The display connector family of bridges is used on a plenty of ARM64 platforms (including, but not being limited to several Qualcomm Robotics and Dragonboard platforms). It doesn't make sense for the DRM drivers to select the driver, so select it via the defconfig. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250214-arm64-display-connector-v1-1-306bca76316e@linaro.org Signed-off-by: Bjorn Andersson [ Backport to 6.12.y ] Signed-off-by: Macpaul Lin --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7e475f38f3e1..219ef05ee5a7 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -911,6 +911,7 @@ CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m +CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_FSL_LDB=m CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_LONTIUM_LT9611=m From patchwork Wed Jul 16 10:28:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWFjcGF1bCBMaW4gKOael+aZuuaWjCk=?= X-Patchwork-Id: 66958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AAFCC83F22 for ; Wed, 16 Jul 2025 10:29:25 +0000 (UTC) Received: from mailgw01.mediatek.com (mailgw01.mediatek.com [60.244.123.138]) by mx.groups.io with SMTP id smtpd.web10.18943.1752661756350045456 for ; Wed, 16 Jul 2025 03:29:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@mediatek.com header.s=dk header.b=sOUHRnes; spf=pass (domain: mediatek.com, ip: 60.244.123.138, mailfrom: macpaul.lin@mediatek.com) X-UUID: b79144d0622f11f08b7dc59d57013e23-20250716 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=yK6pP8ct3hWE54sonE1HMGIx5/H1eGrNIjCFJab0FW4=; b=sOUHRnesE38FQeBqCLAxkjghxLR5zZQSqqaUwtrt46bdS4i4U4KIxaZHm9Wa1d+a4Peb+ayoguvFCXHM/vHrL2Fxa86zJFVL7KA9dIRMecXc5Jp5kmVussJlRJ7Il9zcWyQKjcXDevYlX7L2P4R6c3lr80LUg+aP/AfikvP/d3g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.2,REQID:693e8ec6-0534-4520-8212-dbb5637b2f14,IP:0,UR L:0,TC:0,Content:-5,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-35 X-CID-META: VersionHash:9eb4ff7,CLOUDID:b68ad80e-6968-429c-a74d-a1cce2b698bd,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:2, IP:nil,URL:99|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: b79144d0622f11f08b7dc59d57013e23-20250716 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1851545832; Wed, 16 Jul 2025 18:29:13 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Wed, 16 Jul 2025 18:29:11 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Wed, 16 Jul 2025 18:29:10 +0800 From: Macpaul Lin To: , , , Catalin Marinas , Will Deacon , Matthias Brugger , AngeloGioacchino Del Regno , Sasha Levin , =?utf-8?q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_P?= =?utf-8?q?rado?= , , , CC: Bear Wang , Pablo Sun , Macpaul Lin , Macpaul Lin , MediaTek Chromebook Upstream , =?utf-8?q?Andr=C3=A9_D?= =?utf-8?q?raszik?= , Peter Griffin , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann Subject: [PATCH 6.12 2/2] arm64: defconfig: enable Maxim TCPCI driver Date: Wed, 16 Jul 2025 18:28:54 +0800 Message-ID: <20250716102854.4012956-2-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250716102854.4012956-1-macpaul.lin@mediatek.com> References: <20250716102854.4012956-1-macpaul.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 16 Jul 2025 10:29:25 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/220445 From: André Draszik [ Upstream commit d2ca319822e071423ab883bc8493053320b8e52c ] Enable the Maxim max33359 as this is used by the gs101-oriole (Google Pixel 6) board. Reviewed-by: Peter Griffin Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-1-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20241231131742.134329-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann Signed-off-by: Macpaul Lin --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d2fdef159210..960fe7183539 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1123,6 +1123,7 @@ CONFIG_USB_MASS_STORAGE=m CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_TCPCI_MAXIM=m CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_QCOM_PMIC=m CONFIG_TYPEC_UCSI=m