From patchwork Tue Nov 23 15:59:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26496C433F5 for ; Tue, 23 Nov 2021 15:59:41 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.13029.1637683180049319013 for ; Tue, 23 Nov 2021 07:59:40 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6C7C81063; Tue, 23 Nov 2021 07:59:39 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D8AED3F5A1; Tue, 23 Nov 2021 07:59:37 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Satish Kumar , Jon Mason Subject: [PATCH][honister 01/19] arm/trusted-firmware-m: upgrade to 1.4.0 Date: Tue, 23 Nov 2021 15:59:08 +0000 Message-Id: <20211123155926.31743-2-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 15:59:41 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2430 From: Satish Kumar Update TF-M to version 1.4.0, mbed TLS to 3.0.0, TF-M tests to 1.4.0, and MCUBoot to TF-Mv1.4-integ tag. Change-Id: I9172ed9fbf6c6c2ed88303256ef2452dafc665be Signed-off-by: Satish Kumar Signed-off-by: Jon Mason --- .../trusted-firmware-m_1.4.0.bb | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 meta-arm/recipes-bsp/trusted-firmware-m/trusted-firmware-m_1.4.0.bb diff --git a/meta-arm/recipes-bsp/trusted-firmware-m/trusted-firmware-m_1.4.0.bb b/meta-arm/recipes-bsp/trusted-firmware-m/trusted-firmware-m_1.4.0.bb new file mode 100644 index 0000000..c8465fb --- /dev/null +++ b/meta-arm/recipes-bsp/trusted-firmware-m/trusted-firmware-m_1.4.0.bb @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2020 Arm Limited +# +DEFAULT_PREFERENCE = "-1" + +SUMMARY = "Trusted Firmware for Cortex-M" +DESCRIPTION = "Trusted Firmware-M" +HOMEPAGE = "https://git.trustedfirmware.org/trusted-firmware-m.git" +PROVIDES = "virtual/trusted-firmware-m" + +LICENSE = "BSD-3-Clause & Apachev2" + +LIC_FILES_CHKSUM = "file://license.rst;md5=07f368487da347f3c7bd0fc3085f3afa \ + file://../tf-m-tests/license.rst;md5=02d06ffb8d9f099ff4961c0cb0183a18 \ + file://../mbedtls/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \ + file://../mcuboot/LICENSE;md5=b6ee33f1d12a5e6ee3de1e82fb51eeb8" + +SRC_URI = "git://git.trustedfirmware.org/TF-M/trusted-firmware-m.git;protocol=https;branch=master;name=tfm;destsuffix=${S} \ + git://git.trustedfirmware.org/TF-M/tf-m-tests.git;protocol=https;branch=master;name=tfm-tests;destsuffix=${S}/../tf-m-tests \ + git://github.com/ARMmbed/mbedtls.git;protocol=https;branch=master;name=mbedtls;destsuffix=${S}/../mbedtls \ + git://github.com/mcu-tools/mcuboot.git;protocol=https;branch=main;name=mcuboot;destsuffix=${S}/../mcuboot \ + " + +# The required dependencies are documented in tf-m/config/config_default.cmake +# TF-Mv1.4.0 +SRCREV_tfm = "7ef9178adad866d48e3af42d8a3129dfab792ed8" +# mbedtls-3.0.0 +SRCREV_mbedtls = "8df2f8e7b9c7bb9390ac74bb7bace27edca81a2b" +# TF-Mv1.4.0 +SRCREV_tfm-tests = "e1a8c9fb8394b1f6ea66d2611c070915b0d4b573" +# TF-Mv1.4-integ +SRCREV_mcuboot = "4f8091318b4026d14af9e5a7036825bff62fb612" + +UPSTREAM_CHECK_GITTAGREGEX = "^TF-Mv(?P\d+(\.\d+)+)$" + +# Note to future readers of this recipe: until the CMakeLists don't abuse +# installation (see do_install) there is no point in trying to inherit +# cmake here. You can easily short-circuit the toolchain but the install +# is so convoluted there's no gain. + +inherit python3native deploy + +# Baremetal and we bring a compiler below +INHIBIT_DEFAULT_DEPS = "1" + +PACKAGE_ARCH = "${MACHINE_ARCH}" + +DEPENDS += "cmake-native \ + python3-intelhex-native \ + python3-jinja2-native \ + python3-pyyaml-native \ + python3-click-native \ + python3-cryptography-native \ + python3-pyasn1-native \ + python3-cbor-native" + +S = "${WORKDIR}/git/tfm" +B = "${WORKDIR}/build" + +# Build for debug (set TFM_DEBUG to 1 to activate) +TFM_DEBUG ?= "0" + +# Platform must be set, ideally in the machine configuration. +TFM_PLATFORM ?= "" +python() { + if not d.getVar("TFM_PLATFORM"): + raise bb.parse.SkipRecipe("TFM_PLATFORM needs to be set") +} + +PACKAGECONFIG ??= "cc-gnuarm" +# What compiler to use +PACKAGECONFIG[cc-gnuarm] = "-DTFM_TOOLCHAIN_FILE=${S}/toolchain_GNUARM.cmake,,gcc-arm-none-eabi-native" +PACKAGECONFIG[cc-armclang] = "-DTFM_TOOLCHAIN_FILE=${S}/toolchain_ARMCLANG.cmake,,armcompiler-native" +# Whether to integrate the test suite +PACKAGECONFIG[test-secure] = "-DTEST_S=ON,-DTEST_S=OFF" +PACKAGECONFIG[test-nonsecure] = "-DTEST_NS=ON,-DTEST_NS=OFF" + +# Add platform parameters +EXTRA_OECMAKE += "-DTFM_PLATFORM=${TFM_PLATFORM}" + +# Handle TFM_DEBUG parameter +EXTRA_OECMAKE += "${@bb.utils.contains('TFM_DEBUG', '1', '-DCMAKE_BUILD_TYPE=Debug', '', d)}" + +# Verbose builds +EXTRA_OECMAKE += "-DCMAKE_VERBOSE_MAKEFILE:BOOL=ON" + +EXTRA_OECMAKE += "-DMBEDCRYPTO_PATH=${S}/../mbedtls -DTFM_TEST_REPO_PATH=${S}/../tf-m-tests -DMCUBOOT_PATH=${S}/../mcuboot" + +# Let the Makefile handle setting up the CFLAGS and LDFLAGS as it is a standalone application +CFLAGS[unexport] = "1" +LDFLAGS[unexport] = "1" +AS[unexport] = "1" +LD[unexport] = "1" + +# TF-M ships patches that it needs applied to mbedcrypto, so apply them +# as part of do_patch. +apply_local_patches() { + cat ${S}/lib/ext/mbedcrypto/*.patch | patch -p1 -d ${S}/../mbedtls +} +do_patch[postfuncs] += "apply_local_patches" + +do_configure[cleandirs] = "${B}" +do_configure() { + cmake -G"Unix Makefiles" -S ${S} -B ${B} ${EXTRA_OECMAKE} ${PACKAGECONFIG_CONFARGS} +} + +# Invoke install here as there's no point in splitting compile from install: the +# first thing the build does is 'install' inside the build tree thus causing a +# rebuild. It also overrides the install prefix to be in the build tree, so you +# can't use the usual install prefix variables. +do_compile() { + cmake --build ${B} -- install +} + +do_install() { + # TODO install headers and static libraries when we know how they're used + install -d -m 755 ${D}/firmware + install -m 0644 ${B}/bin/* ${D}/firmware/ +} + +FILES:${PN} = "/firmware" +SYSROOT_DIRS += "/firmware" + +addtask deploy after do_install +do_deploy() { + cp -rf ${D}/firmware/* ${DEPLOYDIR}/ +} From patchwork Tue Nov 23 15:59:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EE46C433F5 for ; Tue, 23 Nov 2021 15:59:44 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.13249.1637683183020533708 for ; Tue, 23 Nov 2021 07:59:43 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C3B641FB; Tue, 23 Nov 2021 07:59:41 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E009F3F5A1; Tue, 23 Nov 2021 07:59:39 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Abdellatif El Khlifi , Jon Mason Subject: [PATCH][honister 02/19] arm-bsp/trusted-firmware-a: remove TARGET_FPU build argument Date: Tue, 23 Nov 2021 15:59:09 +0000 Message-Id: <20211123155926.31743-3-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 15:59:44 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2431 From: Abdellatif El Khlifi TARGET_FPU passed to TF-A Makefile but is not used in TF-A source code. Change-Id: I7c275711ed1e9fb9ee4e4df2b9c1606cacc4138c Signed-off-by: Abdellatif El Khlifi Signed-off-by: Jon Mason --- meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc b/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc index ef1b744..1fd99e7 100644 --- a/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc +++ b/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc @@ -143,7 +143,6 @@ EXTRA_OEMAKE += "OPENSSL_DIR=${STAGING_DIR_NATIVE}/${prefix_native}" # Runtime variables EXTRA_OEMAKE += "RUNTIME_SYSROOT=${STAGING_DIR_HOST}" -EXTRA_OEMAKE += "TARGET_FPU=${TARGET_FPU}" BUILD_DIR = "${B}/${TFA_PLATFORM}" BUILD_DIR .= "${@'/${TFA_BOARD}' if d.getVar('TFA_BOARD') else ''}" From patchwork Tue Nov 23 15:59:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F3E3C433EF for ; Tue, 23 Nov 2021 15:59:45 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.13031.1637683184252845718 for ; Tue, 23 Nov 2021 07:59:44 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E7ADD1FB; Tue, 23 Nov 2021 07:59:43 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2F4B43F5A1; Tue, 23 Nov 2021 07:59:41 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Abdellatif El Khlifi , Jon Mason Subject: [PATCH][honister 03/19] arm/fiptool-native: bumping the version to v2.5 Date: Tue, 23 Nov 2021 15:59:10 +0000 Message-Id: <20211123155926.31743-4-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 15:59:45 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2432 From: Abdellatif El Khlifi The commit provides the v2.5 recipe for fiptool-native and removes the older versions. Change-Id: Ie87ca97bc63bfe7ba2337b1bf05d9658921bab83 Signed-off-by: Abdellatif El Khlifi Signed-off-by: Jon Mason --- .../fiptool/fiptool-native_1.5.bb | 31 ------------------- ...ol-native_2.3.bb => fiptool-native_2.5.bb} | 9 +++--- 2 files changed, 4 insertions(+), 36 deletions(-) delete mode 100644 meta-arm/recipes-devtools/fiptool/fiptool-native_1.5.bb rename meta-arm/recipes-devtools/fiptool/{fiptool-native_2.3.bb => fiptool-native_2.5.bb} (73%) diff --git a/meta-arm/recipes-devtools/fiptool/fiptool-native_1.5.bb b/meta-arm/recipes-devtools/fiptool/fiptool-native_1.5.bb deleted file mode 100644 index 925542c..0000000 --- a/meta-arm/recipes-devtools/fiptool/fiptool-native_1.5.bb +++ /dev/null @@ -1,31 +0,0 @@ -# Firmware Image Package (FIP) -# It is a packaging format used by TF-A to package the -# firmware images in a single binary. - -DESCRIPTION = "fiptool - Trusted Firmware tool for packaging" -LICENSE = "BSD-3-Clause" - -SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;protocol=https" -LIC_FILES_CHKSUM = "file://license.rst;md5=e927e02bca647e14efd87e9e914b2443" - -# Use fiptool from TF-A v1.5 -SRCREV = "ed8112606c54d85781fc8429160883d6310ece32" - -DEPENDS += "openssl-native" - -inherit native - -S = "${WORKDIR}/git" - -do_compile () { - # These changes are needed to have the fiptool compiling and executing properly - sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile - sed -i '/^INCLUDE_PATHS/ s,$, \$\{BUILD_CFLAGS},' ${S}/tools/fiptool/Makefile - - oe_runmake fiptool -} - -do_install () { - install -d ${D}${bindir}/ - install -m 0755 tools/fiptool/fiptool ${D}${bindir} -} diff --git a/meta-arm/recipes-devtools/fiptool/fiptool-native_2.3.bb b/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb similarity index 73% rename from meta-arm/recipes-devtools/fiptool/fiptool-native_2.3.bb rename to meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb index 25ca111..2d0f333 100644 --- a/meta-arm/recipes-devtools/fiptool/fiptool-native_2.3.bb +++ b/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb @@ -6,10 +6,10 @@ DESCRIPTION = "fiptool - Trusted Firmware tool for packaging" LICENSE = "BSD-3-Clause" SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;destsuffix=fiptool-${PV};protocol=https;" -LIC_FILES_CHKSUM = "file://docs/license.rst;md5=189505435dbcdcc8caa63c46fe93fa89" +LIC_FILES_CHKSUM = "file://docs/license.rst;md5=713afe122abbe07f067f939ca3c480c5" -# Use fiptool from TF-A v2.3 -SRCREV = "ecd27ad85f1eba29f6bf92c39dc002c85b07dad5" +# Use fiptool from TF-A v2.5 +SRCREV = "c158878249f1bd930906ebd744b90d3f2a8265f1" DEPENDS += "openssl-native" @@ -24,6 +24,5 @@ do_compile () { } do_install () { - install -d ${D}${bindir}/ - install -m 0755 tools/fiptool/fiptool ${D}${bindir} + install -D -p -m 0755 tools/fiptool/fiptool ${D}${bindir}/fiptool } From patchwork Tue Nov 23 15:59:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FC1DC433F5 for ; Tue, 23 Nov 2021 15:59:47 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.13250.1637683186266651829 for ; Tue, 23 Nov 2021 07:59:46 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E52621063; Tue, 23 Nov 2021 07:59:45 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3ACA93F5A1; Tue, 23 Nov 2021 07:59:44 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Ross Burton , Ross Burton , Jon Mason Subject: [PATCH][honister 04/19] arm/fiptool-native: improve OpenSSL build fix Date: Tue, 23 Nov 2021 15:59:11 +0000 Message-Id: <20211123155926.31743-5-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 15:59:47 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2433 From: Ross Burton Take a patch that is heading upstream to pass OPENSSL_DIR to the fiptool build, removing the need to alter the Makefiles at build time. Signed-off-by: Ross Burton Signed-off-by: Jon Mason --- .../recipes-devtools/fiptool/files/ssl.patch | 52 +++++++++++++++++++ .../fiptool/fiptool-native_2.5.bb | 9 ++-- 2 files changed, 56 insertions(+), 5 deletions(-) create mode 100644 meta-arm/recipes-devtools/fiptool/files/ssl.patch diff --git a/meta-arm/recipes-devtools/fiptool/files/ssl.patch b/meta-arm/recipes-devtools/fiptool/files/ssl.patch new file mode 100644 index 0000000..cdabd1b --- /dev/null +++ b/meta-arm/recipes-devtools/fiptool/files/ssl.patch @@ -0,0 +1,52 @@ +fiptool: respect OPENSSL_DIR + +fiptool links to libcrypto, so as with the other tools it should respect +OPENSSL_DIR for include/library paths. + +Upstream-Status: Submitted +Signed-off-by: Ross Burton + +diff --git a/Makefile b/Makefile +index ec6f88585..2d3b9fc26 100644 +--- a/Makefile ++++ b/Makefile +@@ -1388,7 +1388,7 @@ fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME} + + ${FIPTOOL}: FORCE + ifdef UNIX_MK +- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH} ++ ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} --no-print-directory -C ${FIPTOOLPATH} + else + # Clear the MAKEFLAGS as we do not want + # to pass the gnumake flags to nmake. +diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile +index 11d2e7b0b..7c2a08379 100644 +--- a/tools/fiptool/Makefile ++++ b/tools/fiptool/Makefile +@@ -12,6 +12,8 @@ FIPTOOL ?= fiptool${BIN_EXT} + PROJECT := $(notdir ${FIPTOOL}) + OBJECTS := fiptool.o tbbr_config.o + V ?= 0 ++OPENSSL_DIR := /usr ++ + + override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700 + HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99 +@@ -20,7 +22,7 @@ ifeq (${DEBUG},1) + else + HOSTCCFLAGS += -O2 + endif +-LDLIBS := -lcrypto ++LDLIBS := -L${OPENSSL_DIR}/lib -lcrypto + + ifeq (${V},0) + Q := @ +@@ -28,7 +30,7 @@ else + Q := + endif + +-INCLUDE_PATHS := -I../../include/tools_share ++INCLUDE_PATHS := -I../../include/tools_share -I${OPENSSL_DIR}/include + + HOSTCC ?= gcc + diff --git a/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb b/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb index 2d0f333..e733ff1 100644 --- a/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb +++ b/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb @@ -5,7 +5,8 @@ DESCRIPTION = "fiptool - Trusted Firmware tool for packaging" LICENSE = "BSD-3-Clause" -SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;destsuffix=fiptool-${PV};protocol=https;" +SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;destsuffix=fiptool-${PV};protocol=https \ + file://ssl.patch" LIC_FILES_CHKSUM = "file://docs/license.rst;md5=713afe122abbe07f067f939ca3c480c5" # Use fiptool from TF-A v2.5 @@ -15,11 +16,9 @@ DEPENDS += "openssl-native" inherit native -do_compile () { - # These changes are needed to have the fiptool compiling and executing properly - sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile - sed -i '/^INCLUDE_PATHS/ s,$, \$\{BUILD_CFLAGS},' ${S}/tools/fiptool/Makefile +EXTRA_OEMAKE = "V=1 HOSTCC='${BUILD_CC}' OPENSSL_DIR=${STAGING_DIR_NATIVE}/${prefix_native}" +do_compile () { oe_runmake fiptool } From patchwork Tue Nov 23 15:59:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26782C433EF for ; Tue, 23 Nov 2021 15:59:49 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.13099.1637683188631550191 for ; Tue, 23 Nov 2021 07:59:48 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5760A1FB; Tue, 23 Nov 2021 07:59:48 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 470493F5A1; Tue, 23 Nov 2021 07:59:46 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Ross Burton , Ross Burton , Jon Mason Subject: [PATCH][honister 05/19] arm/trusted-firmware-a: improve OpenSSL build fix Date: Tue, 23 Nov 2021 15:59:12 +0000 Message-Id: <20211123155926.31743-6-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 15:59:49 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2434 From: Ross Burton Take a patch that is heading upstream to pass OPENSSL_DIR to the fiptool build, removing the need to alter the Makefiles at build time. Signed-off-by: Ross Burton Signed-off-by: Jon Mason --- .../trusted-firmware-a/files/ssl.patch | 52 +++++++++++++++++++ .../trusted-firmware-a/trusted-firmware-a.inc | 20 ++----- 2 files changed, 57 insertions(+), 15 deletions(-) create mode 100644 meta-arm/recipes-bsp/trusted-firmware-a/files/ssl.patch diff --git a/meta-arm/recipes-bsp/trusted-firmware-a/files/ssl.patch b/meta-arm/recipes-bsp/trusted-firmware-a/files/ssl.patch new file mode 100644 index 0000000..cdabd1b --- /dev/null +++ b/meta-arm/recipes-bsp/trusted-firmware-a/files/ssl.patch @@ -0,0 +1,52 @@ +fiptool: respect OPENSSL_DIR + +fiptool links to libcrypto, so as with the other tools it should respect +OPENSSL_DIR for include/library paths. + +Upstream-Status: Submitted +Signed-off-by: Ross Burton + +diff --git a/Makefile b/Makefile +index ec6f88585..2d3b9fc26 100644 +--- a/Makefile ++++ b/Makefile +@@ -1388,7 +1388,7 @@ fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME} + + ${FIPTOOL}: FORCE + ifdef UNIX_MK +- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH} ++ ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} --no-print-directory -C ${FIPTOOLPATH} + else + # Clear the MAKEFLAGS as we do not want + # to pass the gnumake flags to nmake. +diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile +index 11d2e7b0b..7c2a08379 100644 +--- a/tools/fiptool/Makefile ++++ b/tools/fiptool/Makefile +@@ -12,6 +12,8 @@ FIPTOOL ?= fiptool${BIN_EXT} + PROJECT := $(notdir ${FIPTOOL}) + OBJECTS := fiptool.o tbbr_config.o + V ?= 0 ++OPENSSL_DIR := /usr ++ + + override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700 + HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99 +@@ -20,7 +22,7 @@ ifeq (${DEBUG},1) + else + HOSTCCFLAGS += -O2 + endif +-LDLIBS := -lcrypto ++LDLIBS := -L${OPENSSL_DIR}/lib -lcrypto + + ifeq (${V},0) + Q := @ +@@ -28,7 +30,7 @@ else + Q := + endif + +-INCLUDE_PATHS := -I../../include/tools_share ++INCLUDE_PATHS := -I../../include/tools_share -I${OPENSSL_DIR}/include + + HOSTCC ?= gcc + diff --git a/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc b/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc index 1fd99e7..36bd037 100644 --- a/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc +++ b/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc @@ -7,7 +7,8 @@ PACKAGE_ARCH = "${MACHINE_ARCH}" inherit deploy -SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;protocol=https;name=tfa" +SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;protocol=https;name=tfa \ + file://ssl.patch" UPSTREAM_CHECK_GITTAGREGEX = "^v(?P\d+(\.\d+)+)$" COMPATIBLE_MACHINE ?= "invalid" @@ -140,6 +141,8 @@ EXTRA_OEMAKE += "${@bb.utils.contains('SEL2_SPMC', '1', 'ARM_SPMC_MANIFEST_DTS=$ # Tell the tools where the native OpenSSL is located EXTRA_OEMAKE += "OPENSSL_DIR=${STAGING_DIR_NATIVE}/${prefix_native}" +# Use the correct native compiler +EXTRA_OEMAKE += "HOSTCC='${BUILD_CC}'" # Runtime variables EXTRA_OEMAKE += "RUNTIME_SYSROOT=${STAGING_DIR_HOST}" @@ -148,23 +151,10 @@ BUILD_DIR = "${B}/${TFA_PLATFORM}" BUILD_DIR .= "${@'/${TFA_BOARD}' if d.getVar('TFA_BOARD') else ''}" BUILD_DIR .= "/${@'debug' if d.getVar("TFA_DEBUG") == '1' else 'release'}" -# The following hack is needed to fit properly in yocto build environment -# TFA is forcing the host compiler and its flags in the Makefile using := -# assignment for GCC and CFLAGS. do_compile() { - cd ${S} - - # These changes are needed to have the native tools compiling and executing properly - sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile - sed -i '/^INCLUDE_PATHS/ s,$, \$\{BUILD_CFLAGS},' ${S}/tools/fiptool/Makefile - sed -i '/^LIB/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/cert_create/Makefile - - # This can be removed when only TF-A 2.4 onwards is supported - sed -i 's^OPENSSL_DIR.*=.*$^OPENSSL_DIR = ${STAGING_DIR_NATIVE}/${prefix_native}^' ${S}/tools/*/Makefile - # Currently there are races if you build all the targets at once in parallel for T in ${TFA_BUILD_TARGET}; do - oe_runmake $T + oe_runmake -C ${S} $T done } do_compile[cleandirs] = "${B}" From patchwork Tue Nov 23 15:59:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25414C433F5 for ; Tue, 23 Nov 2021 15:59:52 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.13034.1637683190882819471 for ; Tue, 23 Nov 2021 07:59:51 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B0F21FB; Tue, 23 Nov 2021 07:59:50 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B67D23F5A1; Tue, 23 Nov 2021 07:59:48 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Diego Sueiro , Jon Mason Subject: [PATCH][honister 06/19] arm/trusted-firmware-a,fiptool-native: Fix fiptool execution Date: Tue, 23 Nov 2021 15:59:13 +0000 Message-Id: <20211123155926.31743-7-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 15:59:52 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2435 From: Diego Sueiro After http://git.yoctoproject.org/cgit/cgit.cgi/meta-arm/commit/?id=648571b113b39420735859461fcd69cfc6f66c76 the fiptool create command fails with: tools/fiptool/fiptool: error while loading shared libraries: libcrypto.so.3: cannot open shared object file: No such file or directory Put back the inclusion of BUILD_LDFLAGS to fix this. Issue-Id: SCM-3548 Signed-off-by: Diego Sueiro Change-Id: I8bfddd0528d5c4dbf5dfd87c9ae17db4e0071b1c Signed-off-by: Jon Mason --- .../recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc | 4 ++++ meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc b/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc index 36bd037..3c4cd58 100644 --- a/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc +++ b/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc @@ -152,6 +152,10 @@ BUILD_DIR .= "${@'/${TFA_BOARD}' if d.getVar('TFA_BOARD') else ''}" BUILD_DIR .= "/${@'debug' if d.getVar("TFA_DEBUG") == '1' else 'release'}" do_compile() { + # This is still needed to have the native fiptool executing properly by + # setting the RPATH + sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile + # Currently there are races if you build all the targets at once in parallel for T in ${TFA_BUILD_TARGET}; do oe_runmake -C ${S} $T diff --git a/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb b/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb index e733ff1..9ad1166 100644 --- a/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb +++ b/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb @@ -19,6 +19,10 @@ inherit native EXTRA_OEMAKE = "V=1 HOSTCC='${BUILD_CC}' OPENSSL_DIR=${STAGING_DIR_NATIVE}/${prefix_native}" do_compile () { + # This is still needed to have the native fiptool executing properly by + # setting the RPATH + sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile + oe_runmake fiptool } From patchwork Tue Nov 23 15:59:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B2E0C433EF for ; Tue, 23 Nov 2021 15:59:55 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.13294.1637683194278276316 for ; Tue, 23 Nov 2021 07:59:54 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9DCC11063; Tue, 23 Nov 2021 07:59:53 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DB3C23F5A1; Tue, 23 Nov 2021 07:59:50 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Abdellatif El Khlifi , Satish Kumar , Rui Miguel Silva , Jon Mason Subject: [PATCH][honister 07/19] arm-bsp/linux: introducing corstone1000 FVP machine Date: Tue, 23 Nov 2021 15:59:14 +0000 Message-Id: <20211123155926.31743-8-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 15:59:55 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2436 From: Abdellatif El Khlifi This commit enables Linux kernel v5.10 for corstone1000-fvp machine. Change-Id: I882902bba273355428af06c29796358e17f9b379 Signed-off-by: Arpita S.K Signed-off-by: Satish Kumar Signed-off-by: Vishnu Banavath Signed-off-by: Abdellatif El Khlifi Signed-off-by: Rui Miguel Silva Signed-off-by: Jon Mason --- .../conf/machine/corstone1000-fvp.conf | 9 + .../conf/machine/include/corstone1000.inc | 24 + .../arm-platforms/corstone1000-standard.scc | 5 + .../bsp/arm-platforms/corstone1000/base.cfg | 29 + ...-usb-isp1760-fix-strict-typechecking.patch | 191 ++ ...0-move-to-regmap-for-register-access.patch | 2333 +++++++++++++++++ ...3-usb-isp1760-use-relaxed-primitives.patch | 64 + ...remove-platform-data-struct-and-code.patch | 62 + ...cd-refactor-mempool-config-and-setup.patch | 304 +++ ...0006-usb-isp1760-use-dr_mode-binding.patch | 78 + ...-usb-isp1760-add-support-for-isp1763.patch | 1894 +++++++++++++ ...indings-usb-nxp-isp1760-add-bindings.patch | 99 + ...0009-usb-isp1763-add-peripheral-mode.patch | 303 +++ ...760-udc-Provide-missing-description-.patch | 41 + ...Fix-meaningless-check-in-isp1763_run.patch | 38 + ...sp1760-remove-debug-message-as-error.patch | 32 + ...-do-not-sleep-in-field-register-poll.patch | 58 + ...rk-cache-initialization-error-handli.patch | 55 + ...re-return-value-for-bus-change-patte.patch | 55 + ...-check-maxpacketsize-before-using-it.patch | 40 + ...0029-usb-isp1760-do-not-reset-retval.patch | 36 + ...0-do-not-shift-in-uninitialized-slot.patch | 61 + ...clean-never-read-udc_enabled-warning.patch | 52 + ...p1760-fix-memory-pool-initialization.patch | 36 + ...0033-usb-isp1760-fix-qtd-fill-length.patch | 38 + ...write-to-status-and-address-register.patch | 90 + ...isp1760-use-the-right-irq-status-bit.patch | 72 + ...-isp1760-otg-control-register-access.patch | 134 + .../corstone1000_kernel_debug.cfg | 3 + .../linux/files/corstone1000/defconfig | 88 + .../linux/linux-arm-platforms.inc | 68 + 31 files changed, 6392 insertions(+) create mode 100644 meta-arm-bsp/conf/machine/corstone1000-fvp.conf create mode 100644 meta-arm-bsp/conf/machine/include/corstone1000.inc create mode 100644 meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/corstone1000-standard.scc create mode 100644 meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/corstone1000/base.cfg create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0001-usb-isp1760-fix-strict-typechecking.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0002-usb-isp1760-move-to-regmap-for-register-access.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0003-usb-isp1760-use-relaxed-primitives.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0004-usb-isp1760-remove-platform-data-struct-and-code.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0005-usb-isp1760-hcd-refactor-mempool-config-and-setup.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0006-usb-isp1760-use-dr_mode-binding.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0007-usb-isp1760-add-support-for-isp1763.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0008-dt-bindings-usb-nxp-isp1760-add-bindings.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0009-usb-isp1763-add-peripheral-mode.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0022-usb-isp1760-isp1760-udc-Provide-missing-description-.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0023-usb-isp1760-Fix-meaningless-check-in-isp1763_run.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0024-usb-isp1760-remove-debug-message-as-error.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0025-usb-isp1760-do-not-sleep-in-field-register-poll.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0026-usb-isp1760-rework-cache-initialization-error-handli.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0027-usb-isp1760-ignore-return-value-for-bus-change-patte.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0028-usb-isp1760-check-maxpacketsize-before-using-it.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0029-usb-isp1760-do-not-reset-retval.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0030-usb-isp1760-do-not-shift-in-uninitialized-slot.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0031-usb-isp1760-clean-never-read-udc_enabled-warning.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0032-usb-isp1760-fix-memory-pool-initialization.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0033-usb-isp1760-fix-qtd-fill-length.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0034-usb-isp1760-write-to-status-and-address-register.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0035-usb-isp1760-use-the-right-irq-status-bit.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0036-usb-isp1760-otg-control-register-access.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/corstone1000_kernel_debug.cfg create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig diff --git a/meta-arm-bsp/conf/machine/corstone1000-fvp.conf b/meta-arm-bsp/conf/machine/corstone1000-fvp.conf new file mode 100644 index 0000000..fc69fe8 --- /dev/null +++ b/meta-arm-bsp/conf/machine/corstone1000-fvp.conf @@ -0,0 +1,9 @@ +#@TYPE: Machine +#@NAME: corstone1000-fvp machine +#@DESCRIPTION: Machine configuration for Corstone1000 64-bit FVP + +require conf/machine/include/corstone1000.inc + +TFA_TARGET_PLATFORM = "fvp" + +TFM_PLATFORM_IS_FVP = "TRUE" diff --git a/meta-arm-bsp/conf/machine/include/corstone1000.inc b/meta-arm-bsp/conf/machine/include/corstone1000.inc new file mode 100644 index 0000000..3d06143 --- /dev/null +++ b/meta-arm-bsp/conf/machine/include/corstone1000.inc @@ -0,0 +1,24 @@ +require conf/machine/include/arm/armv8a/tune-cortexa35.inc + +MACHINEOVERRIDES =. "corstone1000:" + +# Linux kernel +PREFERRED_PROVIDER_virtual/kernel:forcevariable = "linux-yocto" +PREFERRED_VERSION_linux-yocto = "5.10%" +KERNEL_IMAGETYPE = "Image" + +INITRAMFS_IMAGE_BUNDLE ?= "1" + +#telling the build system which image is responsible of the generation of the initramfs rootfs +INITRAMFS_IMAGE = "corstone1000-initramfs-image" + +# enable this feature for kernel debugging +# MACHINE_FEATURES += "corstone1000_kernel_debug" + +# login terminal serial port settings +SERIAL_CONSOLES ?= "115200;ttyAMA0" + +# making sure EXTRA_IMAGEDEPENDS will be used while creating the image +WKS_FILE_DEPENDS:append = " ${EXTRA_IMAGEDEPENDS}" + +WKS_FILE ?= "corstone1000-image.corstone1000.wks" diff --git a/meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/corstone1000-standard.scc b/meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/corstone1000-standard.scc new file mode 100644 index 0000000..9278ce1 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/corstone1000-standard.scc @@ -0,0 +1,5 @@ +define KMACHINE corstone1000 +define KTYPE standard +define KARCH arm64 + +kconf hardware corstone1000/base.cfg diff --git a/meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/corstone1000/base.cfg b/meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/corstone1000/base.cfg new file mode 100644 index 0000000..aea1d84 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/corstone1000/base.cfg @@ -0,0 +1,29 @@ +CONFIG_LOCALVERSION="-yocto-standard" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_LOG_BUF_SHIFT=12 +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARM64=y +CONFIG_THUMB2_KERNEL=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_TMPFS=y +# CONFIG_WLAN is not set +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PL031=y +CONFIG_MAILBOX=y +# CONFIG_CRYPTO_HW is not set diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0001-usb-isp1760-fix-strict-typechecking.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0001-usb-isp1760-fix-strict-typechecking.patch new file mode 100644 index 0000000..1b1cb96 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0001-usb-isp1760-fix-strict-typechecking.patch @@ -0,0 +1,191 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From abfabc8ae3bd625f57fa35d25f2435bb6465a3b1 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 13 May 2021 09:47:09 +0100 +Subject: [PATCH 01/23] usb: isp1760: fix strict typechecking + +There are a lot of pre-existing typechecking warnings around the +access and assign of elements of ptd structure of __dw type. + +sparse: warning: invalid assignment: |= +sparse: left side has type restricted __dw +sparse: right side has type unsigned int + +or + +warning: restricted __dw degrades to integer + +or + +sparse: warning: incorrect type in assignment (different base types) +sparse: expected restricted __dw [usertype] dw4 +sparse: got unsigned int [assigned] [usertype] usof + +To handle this, annotate conversions along the {TO,FROM}_DW* macros +and some assignments and function arguments. + +This clean up completely all sparse warnings for this driver. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210513084717.2487366-2-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-hcd.c | 92 ++++++++++++++++--------------- + 1 file changed, 47 insertions(+), 45 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index 33ae656c4b68..0e0a4b01c710 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -66,44 +66,46 @@ struct ptd { + #define ATL_PTD_OFFSET 0x0c00 + #define PAYLOAD_OFFSET 0x1000 + +- +-/* ATL */ +-/* DW0 */ +-#define DW0_VALID_BIT 1 +-#define FROM_DW0_VALID(x) ((x) & 0x01) +-#define TO_DW0_LENGTH(x) (((u32) x) << 3) +-#define TO_DW0_MAXPACKET(x) (((u32) x) << 18) +-#define TO_DW0_MULTI(x) (((u32) x) << 29) +-#define TO_DW0_ENDPOINT(x) (((u32) x) << 31) ++#define TO_DW(x) ((__force __dw)x) ++#define TO_U32(x) ((__force u32)x) ++ ++ /* ATL */ ++ /* DW0 */ ++#define DW0_VALID_BIT TO_DW(1) ++#define FROM_DW0_VALID(x) (TO_U32(x) & 0x01) ++#define TO_DW0_LENGTH(x) TO_DW((((u32)x) << 3)) ++#define TO_DW0_MAXPACKET(x) TO_DW((((u32)x) << 18)) ++#define TO_DW0_MULTI(x) TO_DW((((u32)x) << 29)) ++#define TO_DW0_ENDPOINT(x) TO_DW((((u32)x) << 31)) + /* DW1 */ +-#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3) +-#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10) +-#define DW1_TRANS_BULK ((u32) 2 << 12) +-#define DW1_TRANS_INT ((u32) 3 << 12) +-#define DW1_TRANS_SPLIT ((u32) 1 << 14) +-#define DW1_SE_USB_LOSPEED ((u32) 2 << 16) +-#define TO_DW1_PORT_NUM(x) (((u32) x) << 18) +-#define TO_DW1_HUB_NUM(x) (((u32) x) << 25) ++#define TO_DW1_DEVICE_ADDR(x) TO_DW((((u32)x) << 3)) ++#define TO_DW1_PID_TOKEN(x) TO_DW((((u32)x) << 10)) ++#define DW1_TRANS_BULK TO_DW(((u32)2 << 12)) ++#define DW1_TRANS_INT TO_DW(((u32)3 << 12)) ++#define DW1_TRANS_SPLIT TO_DW(((u32)1 << 14)) ++#define DW1_SE_USB_LOSPEED TO_DW(((u32)2 << 16)) ++#define TO_DW1_PORT_NUM(x) TO_DW((((u32)x) << 18)) ++#define TO_DW1_HUB_NUM(x) TO_DW((((u32)x) << 25)) + /* DW2 */ +-#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8) +-#define TO_DW2_RL(x) ((x) << 25) +-#define FROM_DW2_RL(x) (((x) >> 25) & 0xf) ++#define TO_DW2_DATA_START_ADDR(x) TO_DW((((u32)x) << 8)) ++#define TO_DW2_RL(x) TO_DW(((x) << 25)) ++#define FROM_DW2_RL(x) ((TO_U32(x) >> 25) & 0xf) + /* DW3 */ +-#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff) +-#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff) +-#define TO_DW3_NAKCOUNT(x) ((x) << 19) +-#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf) +-#define TO_DW3_CERR(x) ((x) << 23) +-#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3) +-#define TO_DW3_DATA_TOGGLE(x) ((x) << 25) +-#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1) +-#define TO_DW3_PING(x) ((x) << 26) +-#define FROM_DW3_PING(x) (((x) >> 26) & 0x1) +-#define DW3_ERROR_BIT (1 << 28) +-#define DW3_BABBLE_BIT (1 << 29) +-#define DW3_HALT_BIT (1 << 30) +-#define DW3_ACTIVE_BIT (1 << 31) +-#define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01) ++#define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x7fff) ++#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x07ff) ++#define TO_DW3_NAKCOUNT(x) TO_DW(((x) << 19)) ++#define FROM_DW3_NAKCOUNT(x) ((TO_U32(x) >> 19) & 0xf) ++#define TO_DW3_CERR(x) TO_DW(((x) << 23)) ++#define FROM_DW3_CERR(x) ((TO_U32(x) >> 23) & 0x3) ++#define TO_DW3_DATA_TOGGLE(x) TO_DW(((x) << 25)) ++#define FROM_DW3_DATA_TOGGLE(x) ((TO_U32(x) >> 25) & 0x1) ++#define TO_DW3_PING(x) TO_DW(((x) << 26)) ++#define FROM_DW3_PING(x) ((TO_U32(x) >> 26) & 0x1) ++#define DW3_ERROR_BIT TO_DW((1 << 28)) ++#define DW3_BABBLE_BIT TO_DW((1 << 29)) ++#define DW3_HALT_BIT TO_DW((1 << 30)) ++#define DW3_ACTIVE_BIT TO_DW((1 << 31)) ++#define FROM_DW3_ACTIVE(x) ((TO_U32(x) >> 31) & 0x01) + + #define INT_UNDERRUN (1 << 2) + #define INT_BABBLE (1 << 1) +@@ -292,12 +294,12 @@ static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, + struct ptd *ptd) + { + mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), +- &ptd->dw1, 7*sizeof(ptd->dw1)); ++ (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1)); + /* Make sure dw0 gets written last (after other dw's and after payload) + since it contains the enable bit */ + wmb(); +- mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, +- sizeof(ptd->dw0)); ++ mem_writes8(base, ptd_offset + slot * sizeof(*ptd), ++ (__force u32 *)&ptd->dw0, sizeof(ptd->dw0)); + } + + +@@ -553,7 +555,7 @@ static void create_ptd_atl(struct isp1760_qh *qh, + ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); + + /* DW1 */ +- ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1; ++ ptd->dw1 = TO_DW((usb_pipeendpoint(qtd->urb->pipe) >> 1)); + ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); + ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); + +@@ -575,7 +577,7 @@ static void create_ptd_atl(struct isp1760_qh *qh, + /* SE bit for Split INT transfers */ + if (usb_pipeint(qtd->urb->pipe) && + (qtd->urb->dev->speed == USB_SPEED_LOW)) +- ptd->dw1 |= 2 << 16; ++ ptd->dw1 |= DW1_SE_USB_LOSPEED; + + rl = 0; + nak = 0; +@@ -647,14 +649,14 @@ static void transform_add_int(struct isp1760_qh *qh, + * that number come from? 0xff seems to work fine... + */ + /* ptd->dw5 = 0x1c; */ +- ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */ ++ ptd->dw5 = TO_DW(0xff); /* Execute Complete Split on any uFrame */ + } + + period = period >> 1;/* Ensure equal or shorter period than requested */ + period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ + +- ptd->dw2 |= period; +- ptd->dw4 = usof; ++ ptd->dw2 |= TO_DW(period); ++ ptd->dw4 = TO_DW(usof); + } + + static void create_ptd_int(struct isp1760_qh *qh, +@@ -977,10 +979,10 @@ static void schedule_ptds(struct usb_hcd *hcd) + static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, + struct urb *urb) + { +- __dw dw4; ++ u32 dw4; + int i; + +- dw4 = ptd->dw4; ++ dw4 = TO_U32(ptd->dw4); + dw4 >>= 8; + + /* FIXME: ISP1761 datasheet does not say what to do with these. Do we +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0002-usb-isp1760-move-to-regmap-for-register-access.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0002-usb-isp1760-move-to-regmap-for-register-access.patch new file mode 100644 index 0000000..a386296 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0002-usb-isp1760-move-to-regmap-for-register-access.patch @@ -0,0 +1,2333 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From 1da9e1c06873350c99ba49a052f92de85f2c69f2 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 13 May 2021 09:47:10 +0100 +Subject: [PATCH 02/23] usb: isp1760: move to regmap for register access + +Rework access to registers and memory to use regmap framework. +No change in current feature or way of work is intended with this +change. + +This will allow to reuse this driver with other IP of this family, +for example isp1763, with little changes and effort. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210513084717.2487366-3-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/Kconfig | 1 + + drivers/usb/isp1760/isp1760-core.c | 239 +++++++++++++--- + drivers/usb/isp1760/isp1760-core.h | 38 ++- + drivers/usb/isp1760/isp1760-hcd.c | 445 +++++++++++++++-------------- + drivers/usb/isp1760/isp1760-hcd.h | 18 +- + drivers/usb/isp1760/isp1760-if.c | 4 +- + drivers/usb/isp1760/isp1760-regs.h | 338 ++++++++++------------ + drivers/usb/isp1760/isp1760-udc.c | 227 ++++++++++----- + drivers/usb/isp1760/isp1760-udc.h | 10 +- + 9 files changed, 789 insertions(+), 531 deletions(-) + +diff --git a/drivers/usb/isp1760/Kconfig b/drivers/usb/isp1760/Kconfig +index b1022cc490a2..d23853f601b1 100644 +--- a/drivers/usb/isp1760/Kconfig ++++ b/drivers/usb/isp1760/Kconfig +@@ -3,6 +3,7 @@ + config USB_ISP1760 + tristate "NXP ISP 1760/1761 support" + depends on USB || USB_GADGET ++ select REGMAP_MMIO + help + Say Y or M here if your system as an ISP1760 USB host controller + or an ISP1761 USB dual-role controller. +diff --git a/drivers/usb/isp1760/isp1760-core.c b/drivers/usb/isp1760/isp1760-core.c +index fdeb4cf97cc5..c79ba98df9f9 100644 +--- a/drivers/usb/isp1760/isp1760-core.c ++++ b/drivers/usb/isp1760/isp1760-core.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -25,8 +26,8 @@ + + static void isp1760_init_core(struct isp1760_device *isp) + { +- u32 otgctrl; +- u32 hwmode; ++ struct isp1760_hcd *hcd = &isp->hcd; ++ struct isp1760_udc *udc = &isp->udc; + + /* Low-level chip reset */ + if (isp->rst_gpio) { +@@ -39,24 +40,22 @@ static void isp1760_init_core(struct isp1760_device *isp) + * Reset the host controller, including the CPU interface + * configuration. + */ +- isp1760_write32(isp->regs, HC_RESET_REG, SW_RESET_RESET_ALL); ++ isp1760_field_set(hcd->fields, SW_RESET_RESET_ALL); + msleep(100); + + /* Setup HW Mode Control: This assumes a level active-low interrupt */ +- hwmode = HW_DATA_BUS_32BIT; +- + if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_16) +- hwmode &= ~HW_DATA_BUS_32BIT; ++ isp1760_field_clear(hcd->fields, HW_DATA_BUS_WIDTH); + if (isp->devflags & ISP1760_FLAG_ANALOG_OC) +- hwmode |= HW_ANA_DIGI_OC; ++ isp1760_field_set(hcd->fields, HW_ANA_DIGI_OC); + if (isp->devflags & ISP1760_FLAG_DACK_POL_HIGH) +- hwmode |= HW_DACK_POL_HIGH; ++ isp1760_field_set(hcd->fields, HW_DACK_POL_HIGH); + if (isp->devflags & ISP1760_FLAG_DREQ_POL_HIGH) +- hwmode |= HW_DREQ_POL_HIGH; ++ isp1760_field_set(hcd->fields, HW_DREQ_POL_HIGH); + if (isp->devflags & ISP1760_FLAG_INTR_POL_HIGH) +- hwmode |= HW_INTR_HIGH_ACT; ++ isp1760_field_set(hcd->fields, HW_INTR_HIGH_ACT); + if (isp->devflags & ISP1760_FLAG_INTR_EDGE_TRIG) +- hwmode |= HW_INTR_EDGE_TRIG; ++ isp1760_field_set(hcd->fields, HW_INTR_EDGE_TRIG); + + /* + * The ISP1761 has a dedicated DC IRQ line but supports sharing the HC +@@ -65,18 +64,10 @@ static void isp1760_init_core(struct isp1760_device *isp) + * spurious interrupts during HCD registration. + */ + if (isp->devflags & ISP1760_FLAG_ISP1761) { +- isp1760_write32(isp->regs, DC_MODE, 0); +- hwmode |= HW_COMN_IRQ; ++ isp1760_reg_write(udc->regs, ISP176x_DC_MODE, 0); ++ isp1760_field_set(hcd->fields, HW_COMN_IRQ); + } + +- /* +- * We have to set this first in case we're in 16-bit mode. +- * Write it twice to ensure correct upper bits if switching +- * to 16-bit mode. +- */ +- isp1760_write32(isp->regs, HC_HW_MODE_CTRL, hwmode); +- isp1760_write32(isp->regs, HC_HW_MODE_CTRL, hwmode); +- + /* + * PORT 1 Control register of the ISP1760 is the OTG control register + * on ISP1761. +@@ -85,14 +76,15 @@ static void isp1760_init_core(struct isp1760_device *isp) + * when OTG is requested. + */ + if ((isp->devflags & ISP1760_FLAG_ISP1761) && +- (isp->devflags & ISP1760_FLAG_OTG_EN)) +- otgctrl = ((HW_DM_PULLDOWN | HW_DP_PULLDOWN) << 16) +- | HW_OTG_DISABLE; +- else +- otgctrl = (HW_SW_SEL_HC_DC << 16) +- | (HW_VBUS_DRV | HW_SEL_CP_EXT); +- +- isp1760_write32(isp->regs, HC_PORT1_CTRL, otgctrl); ++ (isp->devflags & ISP1760_FLAG_OTG_EN)) { ++ isp1760_field_set(hcd->fields, HW_DM_PULLDOWN); ++ isp1760_field_set(hcd->fields, HW_DP_PULLDOWN); ++ isp1760_field_set(hcd->fields, HW_OTG_DISABLE); ++ } else { ++ isp1760_field_set(hcd->fields, HW_SW_SEL_HC_DC); ++ isp1760_field_set(hcd->fields, HW_VBUS_DRV); ++ isp1760_field_set(hcd->fields, HW_SEL_CP_EXT); ++ } + + dev_info(isp->dev, "bus width: %u, oc: %s\n", + isp->devflags & ISP1760_FLAG_BUS_WIDTH_16 ? 16 : 32, +@@ -101,16 +93,158 @@ static void isp1760_init_core(struct isp1760_device *isp) + + void isp1760_set_pullup(struct isp1760_device *isp, bool enable) + { +- isp1760_write32(isp->regs, HW_OTG_CTRL_SET, +- enable ? HW_DP_PULLUP : HW_DP_PULLUP << 16); ++ struct isp1760_udc *udc = &isp->udc; ++ ++ if (enable) ++ isp1760_field_set(udc->fields, HW_DP_PULLUP); ++ else ++ isp1760_field_set(udc->fields, HW_DP_PULLUP_CLEAR); + } + ++static const struct regmap_range isp176x_hc_volatile_ranges[] = { ++ regmap_reg_range(ISP176x_HC_USBCMD, ISP176x_HC_ATL_PTD_LASTPTD), ++ regmap_reg_range(ISP176x_HC_BUFFER_STATUS, ISP176x_HC_MEMORY), ++ regmap_reg_range(ISP176x_HC_INTERRUPT, ISP176x_HC_ATL_IRQ_MASK_AND), ++}; ++ ++static const struct regmap_access_table isp176x_hc_volatile_table = { ++ .yes_ranges = isp176x_hc_volatile_ranges, ++ .n_yes_ranges = ARRAY_SIZE(isp176x_hc_volatile_ranges), ++}; ++ ++static struct regmap_config isp1760_hc_regmap_conf = { ++ .name = "isp1760-hc", ++ .reg_bits = 16, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .fast_io = true, ++ .max_register = ISP176x_HC_MEMORY, ++ .volatile_table = &isp176x_hc_volatile_table, ++}; ++ ++static const struct reg_field isp1760_hc_reg_fields[] = { ++ [HCS_PPC] = REG_FIELD(ISP176x_HC_HCSPARAMS, 4, 4), ++ [HCS_N_PORTS] = REG_FIELD(ISP176x_HC_HCSPARAMS, 0, 3), ++ [HCC_ISOC_CACHE] = REG_FIELD(ISP176x_HC_HCCPARAMS, 7, 7), ++ [HCC_ISOC_THRES] = REG_FIELD(ISP176x_HC_HCCPARAMS, 4, 6), ++ [CMD_LRESET] = REG_FIELD(ISP176x_HC_USBCMD, 7, 7), ++ [CMD_RESET] = REG_FIELD(ISP176x_HC_USBCMD, 1, 1), ++ [CMD_RUN] = REG_FIELD(ISP176x_HC_USBCMD, 0, 0), ++ [STS_PCD] = REG_FIELD(ISP176x_HC_USBSTS, 2, 2), ++ [HC_FRINDEX] = REG_FIELD(ISP176x_HC_FRINDEX, 0, 13), ++ [FLAG_CF] = REG_FIELD(ISP176x_HC_CONFIGFLAG, 0, 0), ++ [PORT_OWNER] = REG_FIELD(ISP176x_HC_PORTSC1, 13, 13), ++ [PORT_POWER] = REG_FIELD(ISP176x_HC_PORTSC1, 12, 12), ++ [PORT_LSTATUS] = REG_FIELD(ISP176x_HC_PORTSC1, 10, 11), ++ [PORT_RESET] = REG_FIELD(ISP176x_HC_PORTSC1, 8, 8), ++ [PORT_SUSPEND] = REG_FIELD(ISP176x_HC_PORTSC1, 7, 7), ++ [PORT_RESUME] = REG_FIELD(ISP176x_HC_PORTSC1, 6, 6), ++ [PORT_PE] = REG_FIELD(ISP176x_HC_PORTSC1, 2, 2), ++ [PORT_CSC] = REG_FIELD(ISP176x_HC_PORTSC1, 1, 1), ++ [PORT_CONNECT] = REG_FIELD(ISP176x_HC_PORTSC1, 0, 0), ++ [ALL_ATX_RESET] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 31, 31), ++ [HW_ANA_DIGI_OC] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 15, 15), ++ [HW_COMN_IRQ] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 10, 10), ++ [HW_DATA_BUS_WIDTH] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 8, 8), ++ [HW_DACK_POL_HIGH] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 6, 6), ++ [HW_DREQ_POL_HIGH] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 5, 5), ++ [HW_INTR_HIGH_ACT] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 2, 2), ++ [HW_INTR_EDGE_TRIG] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 1, 1), ++ [HW_GLOBAL_INTR_EN] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 0, 0), ++ [SW_RESET_RESET_ALL] = REG_FIELD(ISP176x_HC_RESET, 0, 0), ++ [INT_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 1, 1), ++ [ATL_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 0, 0), ++ [MEM_BANK_SEL] = REG_FIELD(ISP176x_HC_MEMORY, 16, 17), ++ [MEM_START_ADDR] = REG_FIELD(ISP176x_HC_MEMORY, 0, 15), ++ [HC_INT_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 7, 8), ++}; ++ ++static const struct regmap_range isp176x_dc_volatile_ranges[] = { ++ regmap_reg_range(ISP176x_DC_EPMAXPKTSZ, ISP176x_DC_EPTYPE), ++ regmap_reg_range(ISP176x_DC_BUFLEN, ISP176x_DC_EPINDEX), ++ regmap_reg_range(ISP1761_DC_OTG_CTRL_SET, ISP1761_DC_OTG_CTRL_CLEAR), ++}; ++ ++static const struct regmap_access_table isp176x_dc_volatile_table = { ++ .yes_ranges = isp176x_dc_volatile_ranges, ++ .n_yes_ranges = ARRAY_SIZE(isp176x_dc_volatile_ranges), ++}; ++ ++static struct regmap_config isp1761_dc_regmap_conf = { ++ .name = "isp1761-dc", ++ .reg_bits = 16, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .fast_io = true, ++ .max_register = ISP1761_DC_OTG_CTRL_CLEAR, ++ .volatile_table = &isp176x_dc_volatile_table, ++}; ++ ++static const struct reg_field isp1761_dc_reg_fields[] = { ++ [DC_DEVEN] = REG_FIELD(ISP176x_DC_ADDRESS, 7, 7), ++ [DC_DEVADDR] = REG_FIELD(ISP176x_DC_ADDRESS, 0, 6), ++ [DC_VBUSSTAT] = REG_FIELD(ISP176x_DC_MODE, 8, 8), ++ [DC_SFRESET] = REG_FIELD(ISP176x_DC_MODE, 4, 4), ++ [DC_GLINTENA] = REG_FIELD(ISP176x_DC_MODE, 3, 3), ++ [DC_CDBGMOD_ACK] = REG_FIELD(ISP176x_DC_INTCONF, 6, 6), ++ [DC_DDBGMODIN_ACK] = REG_FIELD(ISP176x_DC_INTCONF, 4, 4), ++ [DC_DDBGMODOUT_ACK] = REG_FIELD(ISP176x_DC_INTCONF, 2, 2), ++ [DC_INTPOL] = REG_FIELD(ISP176x_DC_INTCONF, 0, 0), ++ [DC_IEPRXTX_7] = REG_FIELD(ISP176x_DC_INTENABLE, 25, 25), ++ [DC_IEPRXTX_6] = REG_FIELD(ISP176x_DC_INTENABLE, 23, 23), ++ [DC_IEPRXTX_5] = REG_FIELD(ISP176x_DC_INTENABLE, 21, 21), ++ [DC_IEPRXTX_4] = REG_FIELD(ISP176x_DC_INTENABLE, 19, 19), ++ [DC_IEPRXTX_3] = REG_FIELD(ISP176x_DC_INTENABLE, 17, 17), ++ [DC_IEPRXTX_2] = REG_FIELD(ISP176x_DC_INTENABLE, 15, 15), ++ [DC_IEPRXTX_1] = REG_FIELD(ISP176x_DC_INTENABLE, 13, 13), ++ [DC_IEPRXTX_0] = REG_FIELD(ISP176x_DC_INTENABLE, 11, 11), ++ [DC_IEP0SETUP] = REG_FIELD(ISP176x_DC_INTENABLE, 8, 8), ++ [DC_IEVBUS] = REG_FIELD(ISP176x_DC_INTENABLE, 7, 7), ++ [DC_IEHS_STA] = REG_FIELD(ISP176x_DC_INTENABLE, 5, 5), ++ [DC_IERESM] = REG_FIELD(ISP176x_DC_INTENABLE, 4, 4), ++ [DC_IESUSP] = REG_FIELD(ISP176x_DC_INTENABLE, 3, 3), ++ [DC_IEBRST] = REG_FIELD(ISP176x_DC_INTENABLE, 0, 0), ++ [DC_EP0SETUP] = REG_FIELD(ISP176x_DC_EPINDEX, 5, 5), ++ [DC_ENDPIDX] = REG_FIELD(ISP176x_DC_EPINDEX, 1, 4), ++ [DC_EPDIR] = REG_FIELD(ISP176x_DC_EPINDEX, 0, 0), ++ [DC_CLBUF] = REG_FIELD(ISP176x_DC_CTRLFUNC, 4, 4), ++ [DC_VENDP] = REG_FIELD(ISP176x_DC_CTRLFUNC, 3, 3), ++ [DC_DSEN] = REG_FIELD(ISP176x_DC_CTRLFUNC, 2, 2), ++ [DC_STATUS] = REG_FIELD(ISP176x_DC_CTRLFUNC, 1, 1), ++ [DC_STALL] = REG_FIELD(ISP176x_DC_CTRLFUNC, 0, 0), ++ [DC_BUFLEN] = REG_FIELD(ISP176x_DC_BUFLEN, 0, 15), ++ [DC_FFOSZ] = REG_FIELD(ISP176x_DC_EPMAXPKTSZ, 0, 10), ++ [DC_EPENABLE] = REG_FIELD(ISP176x_DC_EPTYPE, 3, 3), ++ [DC_ENDPTYP] = REG_FIELD(ISP176x_DC_EPTYPE, 0, 1), ++ [DC_UFRAMENUM] = REG_FIELD(ISP176x_DC_FRAMENUM, 11, 13), ++ [DC_FRAMENUM] = REG_FIELD(ISP176x_DC_FRAMENUM, 0, 10), ++ [HW_OTG_DISABLE] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 10, 10), ++ [HW_SW_SEL_HC_DC] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 7, 7), ++ [HW_VBUS_DRV] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 4, 4), ++ [HW_SEL_CP_EXT] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 3, 3), ++ [HW_DM_PULLDOWN] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 2, 2), ++ [HW_DP_PULLDOWN] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 1, 1), ++ [HW_DP_PULLUP] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 0, 0), ++ [HW_OTG_DISABLE_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 10, 10), ++ [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 7, 7), ++ [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 4, 4), ++ [HW_SEL_CP_EXT_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 3, 3), ++ [HW_DM_PULLDOWN_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 2, 2), ++ [HW_DP_PULLDOWN_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 1, 1), ++ [HW_DP_PULLUP_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 0, 0), ++}; ++ + int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + struct device *dev, unsigned int devflags) + { + struct isp1760_device *isp; ++ struct isp1760_hcd *hcd; ++ struct isp1760_udc *udc; + bool udc_disabled = !(devflags & ISP1760_FLAG_ISP1761); ++ struct regmap_field *f; ++ void __iomem *base; + int ret; ++ int i; + + /* + * If neither the HCD not the UDC is enabled return an error, as no +@@ -126,19 +260,52 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + + isp->dev = dev; + isp->devflags = devflags; ++ hcd = &isp->hcd; ++ udc = &isp->udc; ++ ++ if (devflags & ISP1760_FLAG_BUS_WIDTH_16) { ++ isp1760_hc_regmap_conf.val_bits = 16; ++ isp1761_dc_regmap_conf.val_bits = 16; ++ } + + isp->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); + if (IS_ERR(isp->rst_gpio)) + return PTR_ERR(isp->rst_gpio); + +- isp->regs = devm_ioremap_resource(dev, mem); +- if (IS_ERR(isp->regs)) +- return PTR_ERR(isp->regs); ++ hcd->base = devm_ioremap_resource(dev, mem); ++ if (IS_ERR(hcd->base)) ++ return PTR_ERR(hcd->base); ++ ++ hcd->regs = devm_regmap_init_mmio(dev, base, &isp1760_hc_regmap_conf); ++ if (IS_ERR(hcd->regs)) ++ return PTR_ERR(hcd->regs); ++ ++ for (i = 0; i < HC_FIELD_MAX; i++) { ++ f = devm_regmap_field_alloc(dev, hcd->regs, ++ isp1760_hc_reg_fields[i]); ++ if (IS_ERR(f)) ++ return PTR_ERR(f); ++ ++ hcd->fields[i] = f; ++ } ++ ++ udc->regs = devm_regmap_init_mmio(dev, base, &isp1761_dc_regmap_conf); ++ if (IS_ERR(udc->regs)) ++ return PTR_ERR(udc->regs); ++ ++ for (i = 0; i < DC_FIELD_MAX; i++) { ++ f = devm_regmap_field_alloc(dev, udc->regs, ++ isp1761_dc_reg_fields[i]); ++ if (IS_ERR(f)) ++ return PTR_ERR(f); ++ ++ udc->fields[i] = f; ++ } + + isp1760_init_core(isp); + + if (IS_ENABLED(CONFIG_USB_ISP1760_HCD) && !usb_disabled()) { +- ret = isp1760_hcd_register(&isp->hcd, isp->regs, mem, irq, ++ ret = isp1760_hcd_register(hcd, mem, irq, + irqflags | IRQF_SHARED, dev); + if (ret < 0) + return ret; +@@ -147,7 +314,7 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + if (IS_ENABLED(CONFIG_USB_ISP1761_UDC) && !udc_disabled) { + ret = isp1760_udc_register(isp, irq, irqflags); + if (ret < 0) { +- isp1760_hcd_unregister(&isp->hcd); ++ isp1760_hcd_unregister(hcd); + return ret; + } + } +diff --git a/drivers/usb/isp1760/isp1760-core.h b/drivers/usb/isp1760/isp1760-core.h +index d9a0a4cc467c..8fec6395f19f 100644 +--- a/drivers/usb/isp1760/isp1760-core.h ++++ b/drivers/usb/isp1760/isp1760-core.h +@@ -14,6 +14,7 @@ + #define _ISP1760_CORE_H_ + + #include ++#include + + #include "isp1760-hcd.h" + #include "isp1760-udc.h" +@@ -38,7 +39,6 @@ struct gpio_desc; + struct isp1760_device { + struct device *dev; + +- void __iomem *regs; + unsigned int devflags; + struct gpio_desc *rst_gpio; + +@@ -52,14 +52,42 @@ void isp1760_unregister(struct device *dev); + + void isp1760_set_pullup(struct isp1760_device *isp, bool enable); + +-static inline u32 isp1760_read32(void __iomem *base, u32 reg) ++static inline u32 isp1760_field_read(struct regmap_field **fields, u32 field) + { +- return readl(base + reg); ++ unsigned int val; ++ ++ regmap_field_read(fields[field], &val); ++ ++ return val; ++} ++ ++static inline void isp1760_field_write(struct regmap_field **fields, u32 field, ++ u32 val) ++{ ++ regmap_field_write(fields[field], val); ++} ++ ++static inline void isp1760_field_set(struct regmap_field **fields, u32 field) ++{ ++ isp1760_field_write(fields, field, 0xFFFFFFFF); + } + +-static inline void isp1760_write32(void __iomem *base, u32 reg, u32 val) ++static inline void isp1760_field_clear(struct regmap_field **fields, u32 field) + { +- writel(val, base + reg); ++ isp1760_field_write(fields, field, 0); + } + ++static inline u32 isp1760_reg_read(struct regmap *regs, u32 reg) ++{ ++ unsigned int val; ++ ++ regmap_read(regs, reg, &val); ++ ++ return val; ++} ++ ++static inline void isp1760_reg_write(struct regmap *regs, u32 reg, u32 val) ++{ ++ regmap_write(regs, reg, val); ++} + #endif +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index 0e0a4b01c710..20d142140574 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -66,6 +66,11 @@ struct ptd { + #define ATL_PTD_OFFSET 0x0c00 + #define PAYLOAD_OFFSET 0x1000 + ++#define ISP_BANK_0 0x00 ++#define ISP_BANK_1 0x01 ++#define ISP_BANK_2 0x02 ++#define ISP_BANK_3 0x03 ++ + #define TO_DW(x) ((__force __dw)x) + #define TO_U32(x) ((__force u32)x) + +@@ -161,16 +166,59 @@ struct urb_listitem { + }; + + /* +- * Access functions for isp176x registers (addresses 0..0x03FF). ++ * Access functions for isp176x registers regmap fields + */ +-static u32 reg_read32(void __iomem *base, u32 reg) ++static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ return isp1760_field_read(priv->fields, field); ++} ++ ++static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ isp1760_field_write(priv->fields, field, val); ++} ++ ++static void isp1760_hcd_set(struct usb_hcd *hcd, u32 field) ++{ ++ isp1760_hcd_write(hcd, field, 0xFFFFFFFF); ++} ++ ++static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field) ++{ ++ isp1760_hcd_write(hcd, field, 0); ++} ++ ++static int isp1760_hcd_set_poll_timeout(struct usb_hcd *hcd, u32 field, ++ u32 timeout_us) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ unsigned int val; ++ ++ isp1760_hcd_set(hcd, field); ++ ++ return regmap_field_read_poll_timeout(priv->fields[field], val, 1, 1, ++ timeout_us); ++} ++ ++static int isp1760_hcd_clear_poll_timeout(struct usb_hcd *hcd, u32 field, ++ u32 timeout_us) + { +- return isp1760_read32(base, reg); ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ unsigned int val; ++ ++ isp1760_hcd_clear(hcd, field); ++ ++ return regmap_field_read_poll_timeout(priv->fields[field], val, 0, 1, ++ timeout_us); + } + +-static void reg_write32(void __iomem *base, u32 reg, u32 val) ++static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field) + { +- isp1760_write32(base, reg, val); ++ return !!isp1760_hcd_read(hcd, field); + } + + /* +@@ -233,12 +281,15 @@ static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, + } + } + +-static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, +- u32 bytes) ++static void mem_reads8(struct usb_hcd *hcd, void __iomem *src_base, ++ u32 src_offset, void *dst, u32 bytes) + { +- reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); ++ isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); ++ isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); ++ + ndelay(90); +- bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); ++ ++ bank_reads8(src_base, src_offset, ISP_BANK_0, dst, bytes); + } + + static void mem_writes8(void __iomem *dst_base, u32 dst_offset, +@@ -280,14 +331,15 @@ static void mem_writes8(void __iomem *dst_base, u32 dst_offset, + * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, + * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. + */ +-static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, +- struct ptd *ptd) ++static void ptd_read(struct usb_hcd *hcd, void __iomem *base, ++ u32 ptd_offset, u32 slot, struct ptd *ptd) + { +- reg_write32(base, HC_MEMORY_REG, +- ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd)); ++ isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); ++ isp1760_hcd_write(hcd, MEM_START_ADDR, ++ ptd_offset + slot * sizeof(*ptd)); + ndelay(90); +- bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), +- (void *) ptd, sizeof(*ptd)); ++ bank_reads8(base, ptd_offset + slot * sizeof(*ptd), ISP_BANK_0, ++ (void *)ptd, sizeof(*ptd)); + } + + static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, +@@ -379,34 +431,15 @@ static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) + qtd->payload_addr = 0; + } + +-static int handshake(struct usb_hcd *hcd, u32 reg, +- u32 mask, u32 done, int usec) +-{ +- u32 result; +- int ret; +- +- ret = readl_poll_timeout_atomic(hcd->regs + reg, result, +- ((result & mask) == done || +- result == U32_MAX), 1, usec); +- if (result == U32_MAX) +- return -ENODEV; +- +- return ret; +-} +- + /* reset a non-running (STS_HALT == 1) controller */ + static int ehci_reset(struct usb_hcd *hcd) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); + +- u32 command = reg_read32(hcd->regs, HC_USBCMD); +- +- command |= CMD_RESET; +- reg_write32(hcd->regs, HC_USBCMD, command); + hcd->state = HC_STATE_HALT; + priv->next_statechange = jiffies; + +- return handshake(hcd, HC_USBCMD, CMD_RESET, 0, 250 * 1000); ++ return isp1760_hcd_set_poll_timeout(hcd, CMD_RESET, 250 * 1000); + } + + static struct isp1760_qh *qh_alloc(gfp_t flags) +@@ -434,8 +467,10 @@ static void qh_free(struct isp1760_qh *qh) + /* one-time init, only for memory state */ + static int priv_init(struct usb_hcd *hcd) + { +- struct isp1760_hcd *priv = hcd_to_priv(hcd); +- u32 hcc_params; ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ u32 isoc_cache; ++ u32 isoc_thres; ++ + int i; + + spin_lock_init(&priv->lock); +@@ -450,12 +485,14 @@ static int priv_init(struct usb_hcd *hcd) + priv->periodic_size = DEFAULT_I_TDPS; + + /* controllers may cache some of the periodic schedule ... */ +- hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS); ++ isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE); ++ isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES); ++ + /* full frame cache */ +- if (HCC_ISOC_CACHE(hcc_params)) ++ if (isoc_cache) + priv->i_thresh = 8; + else /* N microframes cached */ +- priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); ++ priv->i_thresh = 2 + isoc_thres; + + return 0; + } +@@ -464,12 +501,13 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); + int result; +- u32 scratch, hwmode; ++ u32 scratch; ++ ++ isp1760_reg_write(priv->regs, ISP176x_HC_SCRATCH, 0xdeadbabe); + +- reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe); + /* Change bus pattern */ +- scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG); +- scratch = reg_read32(hcd->regs, HC_SCRATCH_REG); ++ scratch = isp1760_reg_read(priv->regs, ISP176x_HC_CHIP_ID); ++ scratch = isp1760_reg_read(priv->regs, ISP176x_HC_SCRATCH); + if (scratch != 0xdeadbabe) { + dev_err(hcd->self.controller, "Scratch test failed.\n"); + return -ENODEV; +@@ -483,10 +521,13 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) + * the host controller through the EHCI USB Command register. The device + * has been reset in core code anyway, so this shouldn't matter. + */ +- reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0); +- reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); +- reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); +- reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); ++ isp1760_reg_write(priv->regs, ISP176x_HC_BUFFER_STATUS, 0); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ATL_PTD_SKIPMAP, ++ NO_TRANSFER_ACTIVE); ++ isp1760_reg_write(priv->regs, ISP176x_HC_INT_PTD_SKIPMAP, ++ NO_TRANSFER_ACTIVE); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ISO_PTD_SKIPMAP, ++ NO_TRANSFER_ACTIVE); + + result = ehci_reset(hcd); + if (result) +@@ -495,14 +536,11 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) + /* Step 11 passed */ + + /* ATL reset */ +- hwmode = reg_read32(hcd->regs, HC_HW_MODE_CTRL) & ~ALL_ATX_RESET; +- reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET); ++ isp1760_hcd_set(hcd, ALL_ATX_RESET); + mdelay(10); +- reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); ++ isp1760_hcd_clear(hcd, ALL_ATX_RESET); + +- reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK); +- +- priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS); ++ isp1760_hcd_set(hcd, HC_INT_ENABLE); + + return priv_init(hcd); + } +@@ -732,12 +770,12 @@ static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, + + /* Make sure done map has not triggered from some unlinked transfer */ + if (ptd_offset == ATL_PTD_OFFSET) { +- priv->atl_done_map |= reg_read32(hcd->regs, +- HC_ATL_PTD_DONEMAP_REG); ++ priv->atl_done_map |= isp1760_reg_read(priv->regs, ++ ISP176x_HC_ATL_PTD_DONEMAP); + priv->atl_done_map &= ~(1 << slot); + } else { +- priv->int_done_map |= reg_read32(hcd->regs, +- HC_INT_PTD_DONEMAP_REG); ++ priv->int_done_map |= isp1760_reg_read(priv->regs, ++ ISP176x_HC_INT_PTD_DONEMAP); + priv->int_done_map &= ~(1 << slot); + } + +@@ -746,16 +784,20 @@ static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, + slots[slot].timestamp = jiffies; + slots[slot].qtd = qtd; + slots[slot].qh = qh; +- ptd_write(hcd->regs, ptd_offset, slot, ptd); ++ ptd_write(priv->base, ptd_offset, slot, ptd); + + if (ptd_offset == ATL_PTD_OFFSET) { +- skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); ++ skip_map = isp1760_reg_read(priv->regs, ++ ISP176x_HC_ATL_PTD_SKIPMAP); + skip_map &= ~(1 << qh->slot); +- reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ATL_PTD_SKIPMAP, ++ skip_map); + } else { +- skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); ++ skip_map = isp1760_reg_read(priv->regs, ++ ISP176x_HC_INT_PTD_SKIPMAP); + skip_map &= ~(1 << qh->slot); +- reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); ++ isp1760_reg_write(priv->regs, ISP176x_HC_INT_PTD_SKIPMAP, ++ skip_map); + } + } + +@@ -768,9 +810,10 @@ static int is_short_bulk(struct isp1760_qtd *qtd) + static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, + struct list_head *urb_list) + { +- int last_qtd; ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); + struct isp1760_qtd *qtd, *qtd_next; + struct urb_listitem *urb_listitem; ++ int last_qtd; + + list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { + if (qtd->status < QTD_XFER_COMPLETE) +@@ -785,9 +828,10 @@ static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, + if (qtd->actual_length) { + switch (qtd->packet_type) { + case IN_PID: +- mem_reads8(hcd->regs, qtd->payload_addr, +- qtd->data_buffer, +- qtd->actual_length); ++ mem_reads8(hcd, priv->base, ++ qtd->payload_addr, ++ qtd->data_buffer, ++ qtd->actual_length); + fallthrough; + case OUT_PID: + qtd->urb->actual_length += +@@ -875,8 +919,8 @@ static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) + if ((qtd->length) && + ((qtd->packet_type == SETUP_PID) || + (qtd->packet_type == OUT_PID))) { +- mem_writes8(hcd->regs, qtd->payload_addr, +- qtd->data_buffer, qtd->length); ++ mem_writes8(priv->base, qtd->payload_addr, ++ qtd->data_buffer, qtd->length); + } + + qtd->status = QTD_PAYLOAD_ALLOC; +@@ -1076,9 +1120,9 @@ static void handle_done_ptds(struct usb_hcd *hcd) + int modified; + int skip_map; + +- skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); ++ skip_map = isp1760_reg_read(priv->regs, ISP176x_HC_INT_PTD_SKIPMAP); + priv->int_done_map &= ~skip_map; +- skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); ++ skip_map = isp1760_reg_read(priv->regs, ISP176x_HC_ATL_PTD_SKIPMAP); + priv->atl_done_map &= ~skip_map; + + modified = priv->int_done_map || priv->atl_done_map; +@@ -1096,7 +1140,7 @@ static void handle_done_ptds(struct usb_hcd *hcd) + continue; + } + ptd_offset = INT_PTD_OFFSET; +- ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd); ++ ptd_read(hcd, priv->base, INT_PTD_OFFSET, slot, &ptd); + state = check_int_transfer(hcd, &ptd, + slots[slot].qtd->urb); + } else { +@@ -1111,7 +1155,7 @@ static void handle_done_ptds(struct usb_hcd *hcd) + continue; + } + ptd_offset = ATL_PTD_OFFSET; +- ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); ++ ptd_read(hcd, priv->base, ATL_PTD_OFFSET, slot, &ptd); + state = check_atl_transfer(hcd, &ptd, + slots[slot].qtd->urb); + } +@@ -1136,7 +1180,7 @@ static void handle_done_ptds(struct usb_hcd *hcd) + + qtd->status = QTD_XFER_COMPLETE; + if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || +- is_short_bulk(qtd)) ++ is_short_bulk(qtd)) + qtd = NULL; + else + qtd = list_entry(qtd->qtd_list.next, +@@ -1212,13 +1256,15 @@ static irqreturn_t isp1760_irq(struct usb_hcd *hcd) + if (!(hcd->state & HC_STATE_RUNNING)) + goto leave; + +- imask = reg_read32(hcd->regs, HC_INTERRUPT_REG); ++ imask = isp1760_reg_read(priv->regs, ISP176x_HC_INTERRUPT); + if (unlikely(!imask)) + goto leave; +- reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */ ++ isp1760_reg_write(priv->regs, ISP176x_HC_INTERRUPT, imask); /* Clear */ + +- priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG); +- priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG); ++ priv->int_done_map |= isp1760_reg_read(priv->regs, ++ ISP176x_HC_INT_PTD_DONEMAP); ++ priv->atl_done_map |= isp1760_reg_read(priv->regs, ++ ISP176x_HC_ATL_PTD_DONEMAP); + + handle_done_ptds(hcd); + +@@ -1273,7 +1319,7 @@ static void errata2_function(struct timer_list *unused) + if (priv->atl_slots[slot].qh && time_after(jiffies, + priv->atl_slots[slot].timestamp + + msecs_to_jiffies(SLOT_TIMEOUT))) { +- ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); ++ ptd_read(hcd, priv->base, ATL_PTD_OFFSET, slot, &ptd); + if (!FROM_DW0_VALID(ptd.dw0) && + !FROM_DW3_ACTIVE(ptd.dw3)) + priv->atl_done_map |= 1 << slot; +@@ -1290,9 +1336,8 @@ static void errata2_function(struct timer_list *unused) + + static int isp1760_run(struct usb_hcd *hcd) + { ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); + int retval; +- u32 temp; +- u32 command; + u32 chipid; + + hcd->uses_new_polling = 1; +@@ -1300,23 +1345,20 @@ static int isp1760_run(struct usb_hcd *hcd) + hcd->state = HC_STATE_RUNNING; + + /* Set PTD interrupt AND & OR maps */ +- reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0); +- reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff); +- reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0); +- reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff); +- reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0); +- reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ATL_IRQ_MASK_AND, 0); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ATL_IRQ_MASK_OR, 0xffffffff); ++ isp1760_reg_write(priv->regs, ISP176x_HC_INT_IRQ_MASK_AND, 0); ++ isp1760_reg_write(priv->regs, ISP176x_HC_INT_IRQ_MASK_OR, 0xffffffff); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ISO_IRQ_MASK_AND, 0); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ISO_IRQ_MASK_OR, 0xffffffff); + /* step 23 passed */ + +- temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); +- reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN); ++ isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); + +- command = reg_read32(hcd->regs, HC_USBCMD); +- command &= ~(CMD_LRESET|CMD_RESET); +- command |= CMD_RUN; +- reg_write32(hcd->regs, HC_USBCMD, command); ++ isp1760_hcd_clear(hcd, CMD_LRESET); ++ isp1760_hcd_clear(hcd, CMD_RESET); + +- retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000); ++ retval = isp1760_hcd_set_poll_timeout(hcd, CMD_RUN, 250 * 1000); + if (retval) + return retval; + +@@ -1326,9 +1368,8 @@ static int isp1760_run(struct usb_hcd *hcd) + * the semaphore while doing so. + */ + down_write(&ehci_cf_port_reset_rwsem); +- reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF); + +- retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000); ++ retval = isp1760_hcd_set_poll_timeout(hcd, FLAG_CF, 250 * 1000); + up_write(&ehci_cf_port_reset_rwsem); + if (retval) + return retval; +@@ -1338,21 +1379,22 @@ static int isp1760_run(struct usb_hcd *hcd) + errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD); + add_timer(&errata2_timer); + +- chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG); ++ chipid = isp1760_reg_read(priv->regs, ISP176x_HC_CHIP_ID); + dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", + chipid & 0xffff, chipid >> 16); + + /* PTD Register Init Part 2, Step 28 */ + + /* Setup registers controlling PTD checking */ +- reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000); +- reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000); +- reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001); +- reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff); +- reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff); +- reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff); +- reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, +- ATL_BUF_FILL | INT_BUF_FILL); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ATL_PTD_LASTPTD, 0x80000000); ++ isp1760_reg_write(priv->regs, ISP176x_HC_INT_PTD_LASTPTD, 0x80000000); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ISO_PTD_LASTPTD, 0x00000001); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ATL_PTD_SKIPMAP, 0xffffffff); ++ isp1760_reg_write(priv->regs, ISP176x_HC_INT_PTD_SKIPMAP, 0xffffffff); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ISO_PTD_SKIPMAP, 0xffffffff); ++ ++ isp1760_hcd_set(hcd, ATL_BUF_FILL); ++ isp1760_hcd_set(hcd, INT_BUF_FILL); + + /* GRR this is run-once init(), being done every time the HC starts. + * So long as they're part of class devices, we can't do it init() +@@ -1586,15 +1628,19 @@ static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, + /* We need to forcefully reclaim the slot since some transfers never + return, e.g. interrupt transfers and NAKed bulk transfers. */ + if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { +- skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); ++ skip_map = isp1760_reg_read(priv->regs, ++ ISP176x_HC_ATL_PTD_SKIPMAP); + skip_map |= (1 << qh->slot); +- reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); ++ isp1760_reg_write(priv->regs, ISP176x_HC_ATL_PTD_SKIPMAP, ++ skip_map); + priv->atl_slots[qh->slot].qh = NULL; + priv->atl_slots[qh->slot].qtd = NULL; + } else { +- skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); ++ skip_map = isp1760_reg_read(priv->regs, ++ ISP176x_HC_INT_PTD_SKIPMAP); + skip_map |= (1 << qh->slot); +- reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); ++ isp1760_reg_write(priv->regs, ISP176x_HC_INT_PTD_SKIPMAP, ++ skip_map); + priv->int_slots[qh->slot].qh = NULL; + priv->int_slots[qh->slot].qtd = NULL; + } +@@ -1707,8 +1753,7 @@ static void isp1760_endpoint_disable(struct usb_hcd *hcd, + static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); +- u32 temp, status = 0; +- u32 mask; ++ u32 status = 0; + int retval = 1; + unsigned long flags; + +@@ -1718,17 +1763,13 @@ static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) + + /* init status to no-changes */ + buf[0] = 0; +- mask = PORT_CSC; + + spin_lock_irqsave(&priv->lock, flags); +- temp = reg_read32(hcd->regs, HC_PORTSC1); + +- if (temp & PORT_OWNER) { +- if (temp & PORT_CSC) { +- temp &= ~PORT_CSC; +- reg_write32(hcd->regs, HC_PORTSC1, temp); +- goto done; +- } ++ if (isp1760_hcd_is_set(hcd, PORT_OWNER) && ++ isp1760_hcd_is_set(hcd, PORT_CSC)) { ++ isp1760_hcd_clear(hcd, PORT_CSC); ++ goto done; + } + + /* +@@ -1737,11 +1778,9 @@ static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) + * high-speed device is switched over to the companion + * controller by the user. + */ +- +- if ((temp & mask) != 0 +- || ((temp & PORT_RESUME) != 0 +- && time_after_eq(jiffies, +- priv->reset_done))) { ++ if (isp1760_hcd_is_set(hcd, PORT_CSC) || ++ (isp1760_hcd_is_set(hcd, PORT_RESUME) && ++ time_after_eq(jiffies, priv->reset_done))) { + buf [0] |= 1 << (0 + 1); + status = STS_PCD; + } +@@ -1754,9 +1793,11 @@ static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) + static void isp1760_hub_descriptor(struct isp1760_hcd *priv, + struct usb_hub_descriptor *desc) + { +- int ports = HCS_N_PORTS(priv->hcs_params); ++ int ports; + u16 temp; + ++ ports = isp1760_hcd_read(priv->hcd, HCS_N_PORTS); ++ + desc->bDescriptorType = USB_DT_HUB; + /* priv 1.0, 2.3.9 says 20ms max */ + desc->bPwrOn2PwrGood = 10; +@@ -1772,7 +1813,7 @@ static void isp1760_hub_descriptor(struct isp1760_hcd *priv, + + /* per-port overcurrent reporting */ + temp = HUB_CHAR_INDV_PORT_OCPM; +- if (HCS_PPC(priv->hcs_params)) ++ if (isp1760_hcd_is_set(priv->hcd, HCS_PPC)) + /* per-port power control */ + temp |= HUB_CHAR_INDV_PORT_LPSM; + else +@@ -1783,38 +1824,37 @@ static void isp1760_hub_descriptor(struct isp1760_hcd *priv, + + #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) + +-static int check_reset_complete(struct usb_hcd *hcd, int index, +- int port_status) ++static void check_reset_complete(struct usb_hcd *hcd, int index) + { +- if (!(port_status & PORT_CONNECT)) +- return port_status; ++ if (!(isp1760_hcd_is_set(hcd, PORT_CONNECT))) ++ return; + + /* if reset finished and it's still not enabled -- handoff */ +- if (!(port_status & PORT_PE)) { +- ++ if (!isp1760_hcd_is_set(hcd, PORT_PE)) { + dev_info(hcd->self.controller, +- "port %d full speed --> companion\n", +- index + 1); ++ "port %d full speed --> companion\n", index + 1); + +- port_status |= PORT_OWNER; +- port_status &= ~PORT_RWC_BITS; +- reg_write32(hcd->regs, HC_PORTSC1, port_status); ++ isp1760_hcd_set(hcd, PORT_OWNER); + +- } else ++ isp1760_hcd_clear(hcd, PORT_CSC); ++ } else { + dev_info(hcd->self.controller, "port %d high speed\n", +- index + 1); ++ index + 1); ++ } + +- return port_status; ++ return; + } + + static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + u16 wValue, u16 wIndex, char *buf, u16 wLength) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); +- int ports = HCS_N_PORTS(priv->hcs_params); +- u32 temp, status; ++ u32 status; + unsigned long flags; + int retval = 0; ++ int ports; ++ ++ ports = isp1760_hcd_read(hcd, HCS_N_PORTS); + + /* + * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. +@@ -1839,7 +1879,6 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + if (!wIndex || wIndex > ports) + goto error; + wIndex--; +- temp = reg_read32(hcd->regs, HC_PORTSC1); + + /* + * Even if OWNER is set, so the port is owned by the +@@ -1850,22 +1889,22 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + + switch (wValue) { + case USB_PORT_FEAT_ENABLE: +- reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE); ++ isp1760_hcd_clear(hcd, PORT_PE); + break; + case USB_PORT_FEAT_C_ENABLE: + /* XXX error? */ + break; + case USB_PORT_FEAT_SUSPEND: +- if (temp & PORT_RESET) ++ if (isp1760_hcd_is_set(hcd, PORT_RESET)) + goto error; + +- if (temp & PORT_SUSPEND) { +- if ((temp & PORT_PE) == 0) ++ if (isp1760_hcd_is_set(hcd, PORT_SUSPEND)) { ++ if (!isp1760_hcd_is_set(hcd, PORT_PE)) + goto error; + /* resume signaling for 20 msec */ +- temp &= ~(PORT_RWC_BITS); +- reg_write32(hcd->regs, HC_PORTSC1, +- temp | PORT_RESUME); ++ isp1760_hcd_clear(hcd, PORT_CSC); ++ isp1760_hcd_set(hcd, PORT_RESUME); ++ + priv->reset_done = jiffies + + msecs_to_jiffies(USB_RESUME_TIMEOUT); + } +@@ -1874,12 +1913,11 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + /* we auto-clear this feature */ + break; + case USB_PORT_FEAT_POWER: +- if (HCS_PPC(priv->hcs_params)) +- reg_write32(hcd->regs, HC_PORTSC1, +- temp & ~PORT_POWER); ++ if (isp1760_hcd_is_set(hcd, HCS_PPC)) ++ isp1760_hcd_clear(hcd, PORT_POWER); + break; + case USB_PORT_FEAT_C_CONNECTION: +- reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC); ++ isp1760_hcd_set(hcd, PORT_CSC); + break; + case USB_PORT_FEAT_C_OVER_CURRENT: + /* XXX error ?*/ +@@ -1890,7 +1928,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + default: + goto error; + } +- reg_read32(hcd->regs, HC_USBCMD); ++ isp1760_reg_read(priv->regs, ISP176x_HC_USBCMD); + break; + case GetHubDescriptor: + isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) +@@ -1905,15 +1943,14 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + goto error; + wIndex--; + status = 0; +- temp = reg_read32(hcd->regs, HC_PORTSC1); + + /* wPortChange bits */ +- if (temp & PORT_CSC) ++ if (isp1760_hcd_is_set(hcd, PORT_CSC)) + status |= USB_PORT_STAT_C_CONNECTION << 16; + + + /* whoever resumes must GetPortStatus to complete it!! */ +- if (temp & PORT_RESUME) { ++ if (isp1760_hcd_is_set(hcd, PORT_RESUME)) { + dev_err(hcd->self.controller, "Port resume should be skipped.\n"); + + /* Remote Wakeup received? */ +@@ -1932,35 +1969,31 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + priv->reset_done = 0; + + /* stop resume signaling */ +- temp = reg_read32(hcd->regs, HC_PORTSC1); +- reg_write32(hcd->regs, HC_PORTSC1, +- temp & ~(PORT_RWC_BITS | PORT_RESUME)); +- retval = handshake(hcd, HC_PORTSC1, +- PORT_RESUME, 0, 2000 /* 2msec */); ++ isp1760_hcd_clear(hcd, PORT_CSC); ++ ++ retval = isp1760_hcd_clear_poll_timeout(hcd, ++ PORT_RESUME, 2000); + if (retval != 0) { + dev_err(hcd->self.controller, + "port %d resume error %d\n", + wIndex + 1, retval); + goto error; + } +- temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); + } + } + + /* whoever resets must GetPortStatus to complete it!! */ +- if ((temp & PORT_RESET) +- && time_after_eq(jiffies, +- priv->reset_done)) { ++ if (isp1760_hcd_is_set(hcd, PORT_RESET) && ++ time_after_eq(jiffies, priv->reset_done)) { + status |= USB_PORT_STAT_C_RESET << 16; + priv->reset_done = 0; + + /* force reset to complete */ +- reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET); + /* REVISIT: some hardware needs 550+ usec to clear + * this bit; seems too long to spin routinely... + */ +- retval = handshake(hcd, HC_PORTSC1, +- PORT_RESET, 0, 750); ++ retval = isp1760_hcd_clear_poll_timeout(hcd, PORT_RESET, ++ 750); + if (retval != 0) { + dev_err(hcd->self.controller, "port %d reset error %d\n", + wIndex + 1, retval); +@@ -1968,8 +2001,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + } + + /* see what we found out */ +- temp = check_reset_complete(hcd, wIndex, +- reg_read32(hcd->regs, HC_PORTSC1)); ++ check_reset_complete(hcd, wIndex); + } + /* + * Even if OWNER is set, there's no harm letting hub_wq +@@ -1977,21 +2009,22 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + * for PORT_POWER anyway). + */ + +- if (temp & PORT_OWNER) ++ if (isp1760_hcd_is_set(hcd, PORT_OWNER)) + dev_err(hcd->self.controller, "PORT_OWNER is set\n"); + +- if (temp & PORT_CONNECT) { ++ if (isp1760_hcd_is_set(hcd, PORT_CONNECT)) { + status |= USB_PORT_STAT_CONNECTION; + /* status may be from integrated TT */ + status |= USB_PORT_STAT_HIGH_SPEED; + } +- if (temp & PORT_PE) ++ if (isp1760_hcd_is_set(hcd, PORT_PE)) + status |= USB_PORT_STAT_ENABLE; +- if (temp & (PORT_SUSPEND|PORT_RESUME)) ++ if (isp1760_hcd_is_set(hcd, PORT_SUSPEND) && ++ isp1760_hcd_is_set(hcd, PORT_RESUME)) + status |= USB_PORT_STAT_SUSPEND; +- if (temp & PORT_RESET) ++ if (isp1760_hcd_is_set(hcd, PORT_RESET)) + status |= USB_PORT_STAT_RESET; +- if (temp & PORT_POWER) ++ if (isp1760_hcd_is_set(hcd, PORT_POWER)) + status |= USB_PORT_STAT_POWER; + + put_unaligned(cpu_to_le32(status), (__le32 *) buf); +@@ -2011,41 +2044,39 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + if (!wIndex || wIndex > ports) + goto error; + wIndex--; +- temp = reg_read32(hcd->regs, HC_PORTSC1); +- if (temp & PORT_OWNER) ++ if (isp1760_hcd_is_set(hcd, PORT_OWNER)) + break; + +-/* temp &= ~PORT_RWC_BITS; */ + switch (wValue) { + case USB_PORT_FEAT_ENABLE: +- reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE); ++ isp1760_hcd_set(hcd, PORT_PE); + break; + + case USB_PORT_FEAT_SUSPEND: +- if ((temp & PORT_PE) == 0 +- || (temp & PORT_RESET) != 0) ++ if (!isp1760_hcd_is_set(hcd, PORT_PE) || ++ isp1760_hcd_is_set(hcd, PORT_RESET)) + goto error; + +- reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND); ++ isp1760_hcd_set(hcd, PORT_SUSPEND); + break; + case USB_PORT_FEAT_POWER: +- if (HCS_PPC(priv->hcs_params)) +- reg_write32(hcd->regs, HC_PORTSC1, +- temp | PORT_POWER); ++ if (isp1760_hcd_is_set(hcd, HCS_PPC)) ++ isp1760_hcd_set(hcd, PORT_POWER); + break; + case USB_PORT_FEAT_RESET: +- if (temp & PORT_RESUME) ++ if (isp1760_hcd_is_set(hcd, PORT_RESUME)) + goto error; + /* line status bits may report this as low speed, + * which can be fine if this root hub has a + * transaction translator built in. + */ +- if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT +- && PORT_USB11(temp)) { +- temp |= PORT_OWNER; ++ if ((isp1760_hcd_is_set(hcd, PORT_CONNECT) && ++ !isp1760_hcd_is_set(hcd, PORT_PE)) && ++ (isp1760_hcd_read(hcd, PORT_LSTATUS) == 1)) { ++ isp1760_hcd_set(hcd, PORT_OWNER); + } else { +- temp |= PORT_RESET; +- temp &= ~PORT_PE; ++ isp1760_hcd_set(hcd, PORT_RESET); ++ isp1760_hcd_clear(hcd, PORT_PE); + + /* + * caller must wait, then call GetPortStatus +@@ -2054,12 +2085,11 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + priv->reset_done = jiffies + + msecs_to_jiffies(50); + } +- reg_write32(hcd->regs, HC_PORTSC1, temp); + break; + default: + goto error; + } +- reg_read32(hcd->regs, HC_USBCMD); ++ isp1760_reg_read(priv->regs, ISP176x_HC_USBCMD); + break; + + default: +@@ -2076,14 +2106,13 @@ static int isp1760_get_frame(struct usb_hcd *hcd) + struct isp1760_hcd *priv = hcd_to_priv(hcd); + u32 fr; + +- fr = reg_read32(hcd->regs, HC_FRINDEX); ++ fr = isp1760_hcd_read(hcd, HC_FRINDEX); + return (fr >> 3) % priv->periodic_size; + } + + static void isp1760_stop(struct usb_hcd *hcd) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); +- u32 temp; + + del_timer(&errata2_timer); + +@@ -2094,24 +2123,19 @@ static void isp1760_stop(struct usb_hcd *hcd) + spin_lock_irq(&priv->lock); + ehci_reset(hcd); + /* Disable IRQ */ +- temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); +- reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); ++ isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN); + spin_unlock_irq(&priv->lock); + +- reg_write32(hcd->regs, HC_CONFIGFLAG, 0); ++ isp1760_hcd_clear(hcd, FLAG_CF); + } + + static void isp1760_shutdown(struct usb_hcd *hcd) + { +- u32 command, temp; +- + isp1760_stop(hcd); +- temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); +- reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); + +- command = reg_read32(hcd->regs, HC_USBCMD); +- command &= ~CMD_RUN; +- reg_write32(hcd->regs, HC_USBCMD, command); ++ isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN); ++ ++ isp1760_hcd_clear(hcd, CMD_RUN); + } + + static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd, +@@ -2184,8 +2208,8 @@ void isp1760_deinit_kmem_cache(void) + kmem_cache_destroy(urb_listitem_cachep); + } + +-int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs, +- struct resource *mem, int irq, unsigned long irqflags, ++int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, ++ int irq, unsigned long irqflags, + struct device *dev) + { + struct usb_hcd *hcd; +@@ -2202,7 +2226,6 @@ int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs, + init_memory(priv); + + hcd->irq = irq; +- hcd->regs = regs; + hcd->rsrc_start = mem->start; + hcd->rsrc_len = resource_size(mem); + +diff --git a/drivers/usb/isp1760/isp1760-hcd.h b/drivers/usb/isp1760/isp1760-hcd.h +index f1bb2deb1ccf..34e1899e52c4 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.h ++++ b/drivers/usb/isp1760/isp1760-hcd.h +@@ -3,6 +3,9 @@ + #define _ISP1760_HCD_H_ + + #include ++#include ++ ++#include "isp1760-regs.h" + + struct isp1760_qh; + struct isp1760_qtd; +@@ -48,10 +51,13 @@ enum isp1760_queue_head_types { + }; + + struct isp1760_hcd { +-#ifdef CONFIG_USB_ISP1760_HCD + struct usb_hcd *hcd; + +- u32 hcs_params; ++ void __iomem *base; ++ ++ struct regmap *regs; ++ struct regmap_field *fields[HC_FIELD_MAX]; ++ + spinlock_t lock; + struct isp1760_slotinfo atl_slots[32]; + int atl_done_map; +@@ -66,20 +72,18 @@ struct isp1760_hcd { + unsigned i_thresh; + unsigned long reset_done; + unsigned long next_statechange; +-#endif + }; + + #ifdef CONFIG_USB_ISP1760_HCD +-int isp1760_hcd_register(struct isp1760_hcd *priv, void __iomem *regs, +- struct resource *mem, int irq, unsigned long irqflags, +- struct device *dev); ++int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, ++ int irq, unsigned long irqflags, struct device *dev); + void isp1760_hcd_unregister(struct isp1760_hcd *priv); + + int isp1760_init_kmem_once(void); + void isp1760_deinit_kmem_cache(void); + #else + static inline int isp1760_hcd_register(struct isp1760_hcd *priv, +- void __iomem *regs, struct resource *mem, ++ struct resource *mem, + int irq, unsigned long irqflags, + struct device *dev) + { +diff --git a/drivers/usb/isp1760/isp1760-if.c b/drivers/usb/isp1760/isp1760-if.c +index ccd30f835888..abfba9f5ec23 100644 +--- a/drivers/usb/isp1760/isp1760-if.c ++++ b/drivers/usb/isp1760/isp1760-if.c +@@ -75,9 +75,9 @@ static int isp1761_pci_init(struct pci_dev *dev) + /*by default host is in 16bit mode, so + * io operations at this stage must be 16 bit + * */ +- writel(0xface, iobase + HC_SCRATCH_REG); ++ writel(0xface, iobase + ISP176x_HC_SCRATCH); + udelay(100); +- reg_data = readl(iobase + HC_SCRATCH_REG) & 0x0000ffff; ++ reg_data = readl(iobase + ISP176x_HC_SCRATCH) & 0x0000ffff; + retry_count--; + } + +diff --git a/drivers/usb/isp1760/isp1760-regs.h b/drivers/usb/isp1760/isp1760-regs.h +index fedc4f5cded0..0d5262c37c5b 100644 +--- a/drivers/usb/isp1760/isp1760-regs.h ++++ b/drivers/usb/isp1760/isp1760-regs.h +@@ -10,218 +10,182 @@ + * Laurent Pinchart + */ + +-#ifndef _ISP1760_REGS_H_ +-#define _ISP1760_REGS_H_ ++#ifndef _ISP176x_REGS_H_ ++#define _ISP176x_REGS_H_ + + /* ----------------------------------------------------------------------------- + * Host Controller + */ + + /* EHCI capability registers */ +-#define HC_CAPLENGTH 0x000 +-#define HC_LENGTH(p) (((p) >> 00) & 0x00ff) /* bits 7:0 */ +-#define HC_VERSION(p) (((p) >> 16) & 0xffff) /* bits 31:16 */ +- +-#define HC_HCSPARAMS 0x004 +-#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */ +-#define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */ +-#define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */ +- +-#define HC_HCCPARAMS 0x008 +-#define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */ +-#define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */ ++#define ISP176x_HC_CAPLENGTH 0x000 ++#define ISP176x_HC_VERSION 0x002 ++#define ISP176x_HC_HCSPARAMS 0x004 ++#define ISP176x_HC_HCCPARAMS 0x008 + + /* EHCI operational registers */ +-#define HC_USBCMD 0x020 +-#define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */ +-#define CMD_RESET (1 << 1) /* reset HC not bus */ +-#define CMD_RUN (1 << 0) /* start/stop HC */ +- +-#define HC_USBSTS 0x024 +-#define STS_PCD (1 << 2) /* port change detect */ +- +-#define HC_FRINDEX 0x02c +- +-#define HC_CONFIGFLAG 0x060 +-#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ +- +-#define HC_PORTSC1 0x064 +-#define PORT_OWNER (1 << 13) /* true: companion hc owns this port */ +-#define PORT_POWER (1 << 12) /* true: has power (see PPC) */ +-#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ +-#define PORT_RESET (1 << 8) /* reset port */ +-#define PORT_SUSPEND (1 << 7) /* suspend port */ +-#define PORT_RESUME (1 << 6) /* resume it */ +-#define PORT_PE (1 << 2) /* port enable */ +-#define PORT_CSC (1 << 1) /* connect status change */ +-#define PORT_CONNECT (1 << 0) /* device connected */ +-#define PORT_RWC_BITS (PORT_CSC) +- +-#define HC_ISO_PTD_DONEMAP_REG 0x130 +-#define HC_ISO_PTD_SKIPMAP_REG 0x134 +-#define HC_ISO_PTD_LASTPTD_REG 0x138 +-#define HC_INT_PTD_DONEMAP_REG 0x140 +-#define HC_INT_PTD_SKIPMAP_REG 0x144 +-#define HC_INT_PTD_LASTPTD_REG 0x148 +-#define HC_ATL_PTD_DONEMAP_REG 0x150 +-#define HC_ATL_PTD_SKIPMAP_REG 0x154 +-#define HC_ATL_PTD_LASTPTD_REG 0x158 ++#define ISP176x_HC_USBCMD 0x020 ++#define ISP176x_HC_USBSTS 0x024 ++#define ISP176x_HC_FRINDEX 0x02c ++ ++#define ISP176x_HC_CONFIGFLAG 0x060 ++#define ISP176x_HC_PORTSC1 0x064 ++ ++#define ISP176x_HC_ISO_PTD_DONEMAP 0x130 ++#define ISP176x_HC_ISO_PTD_SKIPMAP 0x134 ++#define ISP176x_HC_ISO_PTD_LASTPTD 0x138 ++#define ISP176x_HC_INT_PTD_DONEMAP 0x140 ++#define ISP176x_HC_INT_PTD_SKIPMAP 0x144 ++#define ISP176x_HC_INT_PTD_LASTPTD 0x148 ++#define ISP176x_HC_ATL_PTD_DONEMAP 0x150 ++#define ISP176x_HC_ATL_PTD_SKIPMAP 0x154 ++#define ISP176x_HC_ATL_PTD_LASTPTD 0x158 + + /* Configuration Register */ +-#define HC_HW_MODE_CTRL 0x300 +-#define ALL_ATX_RESET (1 << 31) +-#define HW_ANA_DIGI_OC (1 << 15) +-#define HW_DEV_DMA (1 << 11) +-#define HW_COMN_IRQ (1 << 10) +-#define HW_COMN_DMA (1 << 9) +-#define HW_DATA_BUS_32BIT (1 << 8) +-#define HW_DACK_POL_HIGH (1 << 6) +-#define HW_DREQ_POL_HIGH (1 << 5) +-#define HW_INTR_HIGH_ACT (1 << 2) +-#define HW_INTR_EDGE_TRIG (1 << 1) +-#define HW_GLOBAL_INTR_EN (1 << 0) +- +-#define HC_CHIP_ID_REG 0x304 +-#define HC_SCRATCH_REG 0x308 +- +-#define HC_RESET_REG 0x30c +-#define SW_RESET_RESET_HC (1 << 1) +-#define SW_RESET_RESET_ALL (1 << 0) +- +-#define HC_BUFFER_STATUS_REG 0x334 +-#define ISO_BUF_FILL (1 << 2) +-#define INT_BUF_FILL (1 << 1) +-#define ATL_BUF_FILL (1 << 0) +- +-#define HC_MEMORY_REG 0x33c +-#define ISP_BANK(x) ((x) << 16) +- +-#define HC_PORT1_CTRL 0x374 +-#define PORT1_POWER (3 << 3) +-#define PORT1_INIT1 (1 << 7) +-#define PORT1_INIT2 (1 << 23) +-#define HW_OTG_CTRL_SET 0x374 +-#define HW_OTG_CTRL_CLR 0x376 +-#define HW_OTG_DISABLE (1 << 10) +-#define HW_OTG_SE0_EN (1 << 9) +-#define HW_BDIS_ACON_EN (1 << 8) +-#define HW_SW_SEL_HC_DC (1 << 7) +-#define HW_VBUS_CHRG (1 << 6) +-#define HW_VBUS_DISCHRG (1 << 5) +-#define HW_VBUS_DRV (1 << 4) +-#define HW_SEL_CP_EXT (1 << 3) +-#define HW_DM_PULLDOWN (1 << 2) +-#define HW_DP_PULLDOWN (1 << 1) +-#define HW_DP_PULLUP (1 << 0) ++#define ISP176x_HC_HW_MODE_CTRL 0x300 ++#define ISP176x_HC_CHIP_ID 0x304 ++#define ISP176x_HC_SCRATCH 0x308 ++#define ISP176x_HC_RESET 0x30c ++#define ISP176x_HC_BUFFER_STATUS 0x334 ++#define ISP176x_HC_MEMORY 0x33c + + /* Interrupt Register */ +-#define HC_INTERRUPT_REG 0x310 +- +-#define HC_INTERRUPT_ENABLE 0x314 +-#define HC_ISO_INT (1 << 9) +-#define HC_ATL_INT (1 << 8) +-#define HC_INTL_INT (1 << 7) +-#define HC_EOT_INT (1 << 3) +-#define HC_SOT_INT (1 << 1) +-#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT) +- +-#define HC_ISO_IRQ_MASK_OR_REG 0x318 +-#define HC_INT_IRQ_MASK_OR_REG 0x31c +-#define HC_ATL_IRQ_MASK_OR_REG 0x320 +-#define HC_ISO_IRQ_MASK_AND_REG 0x324 +-#define HC_INT_IRQ_MASK_AND_REG 0x328 +-#define HC_ATL_IRQ_MASK_AND_REG 0x32c ++#define ISP176x_HC_INTERRUPT 0x310 ++#define ISP176x_HC_INTERRUPT_ENABLE 0x314 ++#define ISP176x_HC_ISO_IRQ_MASK_OR 0x318 ++#define ISP176x_HC_INT_IRQ_MASK_OR 0x31c ++#define ISP176x_HC_ATL_IRQ_MASK_OR 0x320 ++#define ISP176x_HC_ISO_IRQ_MASK_AND 0x324 ++#define ISP176x_HC_INT_IRQ_MASK_AND 0x328 ++#define ISP176x_HC_ATL_IRQ_MASK_AND 0x32c ++ ++enum isp176x_host_controller_fields { ++ /* HC_HCSPARAMS */ ++ HCS_PPC, HCS_N_PORTS, ++ /* HC_HCCPARAMS */ ++ HCC_ISOC_CACHE, HCC_ISOC_THRES, ++ /* HC_USBCMD */ ++ CMD_LRESET, CMD_RESET, CMD_RUN, ++ /* HC_USBSTS */ ++ STS_PCD, ++ /* HC_FRINDEX */ ++ HC_FRINDEX, ++ /* HC_CONFIGFLAG */ ++ FLAG_CF, ++ /* HC_PORTSC1 */ ++ PORT_OWNER, PORT_POWER, PORT_LSTATUS, PORT_RESET, PORT_SUSPEND, ++ PORT_RESUME, PORT_PE, PORT_CSC, PORT_CONNECT, ++ /* HC_HW_MODE_CTRL */ ++ ALL_ATX_RESET, HW_ANA_DIGI_OC, HW_DEV_DMA, HW_COMN_IRQ, HW_COMN_DMA, ++ HW_DATA_BUS_WIDTH, HW_DACK_POL_HIGH, HW_DREQ_POL_HIGH, HW_INTR_HIGH_ACT, ++ HW_INTR_EDGE_TRIG, HW_GLOBAL_INTR_EN, ++ /* HC_RESET */ ++ SW_RESET_RESET_HC, SW_RESET_RESET_ALL, ++ /* HC_BUFFER_STATUS */ ++ INT_BUF_FILL, ATL_BUF_FILL, ++ /* HC_MEMORY */ ++ MEM_BANK_SEL, MEM_START_ADDR, ++ /* HC_INTERRUPT_ENABLE */ ++ HC_INT_ENABLE, ++ /* Last element */ ++ HC_FIELD_MAX, ++}; + + /* ----------------------------------------------------------------------------- + * Peripheral Controller + */ + +-/* Initialization Registers */ +-#define DC_ADDRESS 0x0200 +-#define DC_DEVEN (1 << 7) +- +-#define DC_MODE 0x020c +-#define DC_DMACLKON (1 << 9) +-#define DC_VBUSSTAT (1 << 8) +-#define DC_CLKAON (1 << 7) +-#define DC_SNDRSU (1 << 6) +-#define DC_GOSUSP (1 << 5) +-#define DC_SFRESET (1 << 4) +-#define DC_GLINTENA (1 << 3) +-#define DC_WKUPCS (1 << 2) +- +-#define DC_INTCONF 0x0210 +-#define DC_CDBGMOD_ACK_NAK (0 << 6) +-#define DC_CDBGMOD_ACK (1 << 6) +-#define DC_CDBGMOD_ACK_1NAK (2 << 6) +-#define DC_DDBGMODIN_ACK_NAK (0 << 4) +-#define DC_DDBGMODIN_ACK (1 << 4) +-#define DC_DDBGMODIN_ACK_1NAK (2 << 4) +-#define DC_DDBGMODOUT_ACK_NYET_NAK (0 << 2) +-#define DC_DDBGMODOUT_ACK_NYET (1 << 2) +-#define DC_DDBGMODOUT_ACK_NYET_1NAK (2 << 2) +-#define DC_INTLVL (1 << 1) +-#define DC_INTPOL (1 << 0) +- +-#define DC_DEBUG 0x0212 +-#define DC_INTENABLE 0x0214 + #define DC_IEPTX(n) (1 << (11 + 2 * (n))) + #define DC_IEPRX(n) (1 << (10 + 2 * (n))) + #define DC_IEPRXTX(n) (3 << (10 + 2 * (n))) +-#define DC_IEP0SETUP (1 << 8) +-#define DC_IEVBUS (1 << 7) +-#define DC_IEDMA (1 << 6) +-#define DC_IEHS_STA (1 << 5) +-#define DC_IERESM (1 << 4) +-#define DC_IESUSP (1 << 3) +-#define DC_IEPSOF (1 << 2) +-#define DC_IESOF (1 << 1) +-#define DC_IEBRST (1 << 0) ++ ++#define ISP176x_DC_CDBGMOD_ACK BIT(6) ++#define ISP176x_DC_DDBGMODIN_ACK BIT(4) ++#define ISP176x_DC_DDBGMODOUT_ACK BIT(2) ++ ++#define ISP176x_DC_IEP0SETUP BIT(8) ++#define ISP176x_DC_IEVBUS BIT(7) ++#define ISP176x_DC_IEHS_STA BIT(5) ++#define ISP176x_DC_IERESM BIT(4) ++#define ISP176x_DC_IESUSP BIT(3) ++#define ISP176x_DC_IEBRST BIT(0) ++ ++#define ISP176x_DC_ENDPTYP_ISOC 0x01 ++#define ISP176x_DC_ENDPTYP_BULK 0x02 ++#define ISP176x_DC_ENDPTYP_INTERRUPT 0x03 ++ ++/* Initialization Registers */ ++#define ISP176x_DC_ADDRESS 0x0200 ++#define ISP176x_DC_MODE 0x020c ++#define ISP176x_DC_INTCONF 0x0210 ++#define ISP176x_DC_DEBUG 0x0212 ++#define ISP176x_DC_INTENABLE 0x0214 + + /* Data Flow Registers */ +-#define DC_EPINDEX 0x022c +-#define DC_EP0SETUP (1 << 5) +-#define DC_ENDPIDX(n) ((n) << 1) +-#define DC_EPDIR (1 << 0) +- +-#define DC_CTRLFUNC 0x0228 +-#define DC_CLBUF (1 << 4) +-#define DC_VENDP (1 << 3) +-#define DC_DSEN (1 << 2) +-#define DC_STATUS (1 << 1) +-#define DC_STALL (1 << 0) +- +-#define DC_DATAPORT 0x0220 +-#define DC_BUFLEN 0x021c +-#define DC_DATACOUNT_MASK 0xffff +-#define DC_BUFSTAT 0x021e +-#define DC_EPMAXPKTSZ 0x0204 +- +-#define DC_EPTYPE 0x0208 +-#define DC_NOEMPKT (1 << 4) +-#define DC_EPENABLE (1 << 3) +-#define DC_DBLBUF (1 << 2) +-#define DC_ENDPTYP_ISOC (1 << 0) +-#define DC_ENDPTYP_BULK (2 << 0) +-#define DC_ENDPTYP_INTERRUPT (3 << 0) ++#define ISP176x_DC_EPMAXPKTSZ 0x0204 ++#define ISP176x_DC_EPTYPE 0x0208 ++ ++#define ISP176x_DC_BUFLEN 0x021c ++#define ISP176x_DC_BUFSTAT 0x021e ++#define ISP176x_DC_DATAPORT 0x0220 ++ ++#define ISP176x_DC_CTRLFUNC 0x0228 ++#define ISP176x_DC_EPINDEX 0x022c ++ ++#define ISP1761_DC_OTG_CTRL_SET 0x374 ++#define ISP1761_DC_OTG_CTRL_CLEAR 0x376 + + /* DMA Registers */ +-#define DC_DMACMD 0x0230 +-#define DC_DMATXCOUNT 0x0234 +-#define DC_DMACONF 0x0238 +-#define DC_DMAHW 0x023c +-#define DC_DMAINTREASON 0x0250 +-#define DC_DMAINTEN 0x0254 +-#define DC_DMAEP 0x0258 +-#define DC_DMABURSTCOUNT 0x0264 ++#define ISP176x_DC_DMACMD 0x0230 ++#define ISP176x_DC_DMATXCOUNT 0x0234 ++#define ISP176x_DC_DMACONF 0x0238 ++#define ISP176x_DC_DMAHW 0x023c ++#define ISP176x_DC_DMAINTREASON 0x0250 ++#define ISP176x_DC_DMAINTEN 0x0254 ++#define ISP176x_DC_DMAEP 0x0258 ++#define ISP176x_DC_DMABURSTCOUNT 0x0264 + + /* General Registers */ +-#define DC_INTERRUPT 0x0218 +-#define DC_CHIPID 0x0270 +-#define DC_FRAMENUM 0x0274 +-#define DC_SCRATCH 0x0278 +-#define DC_UNLOCKDEV 0x027c +-#define DC_INTPULSEWIDTH 0x0280 +-#define DC_TESTMODE 0x0284 ++#define ISP176x_DC_INTERRUPT 0x0218 ++#define ISP176x_DC_CHIPID 0x0270 ++#define ISP176x_DC_FRAMENUM 0x0274 ++#define ISP176x_DC_SCRATCH 0x0278 ++#define ISP176x_DC_UNLOCKDEV 0x027c ++#define ISP176x_DC_INTPULSEWIDTH 0x0280 ++#define ISP176x_DC_TESTMODE 0x0284 ++ ++enum isp176x_device_controller_fields { ++ /* DC_ADDRESS */ ++ DC_DEVEN, DC_DEVADDR, ++ /* DC_MODE */ ++ DC_VBUSSTAT, DC_SFRESET, DC_GLINTENA, ++ /* DC_INTCONF */ ++ DC_CDBGMOD_ACK, DC_DDBGMODIN_ACK, DC_DDBGMODOUT_ACK, DC_INTPOL, ++ /* DC_INTENABLE */ ++ DC_IEPRXTX_7, DC_IEPRXTX_6, DC_IEPRXTX_5, DC_IEPRXTX_4, DC_IEPRXTX_3, ++ DC_IEPRXTX_2, DC_IEPRXTX_1, DC_IEPRXTX_0, ++ DC_IEP0SETUP, DC_IEVBUS, DC_IEHS_STA, DC_IERESM, DC_IESUSP, DC_IEBRST, ++ /* DC_EPINDEX */ ++ DC_EP0SETUP, DC_ENDPIDX, DC_EPDIR, ++ /* DC_CTRLFUNC */ ++ DC_CLBUF, DC_VENDP, DC_DSEN, DC_STATUS, DC_STALL, ++ /* DC_BUFLEN */ ++ DC_BUFLEN, ++ /* DC_EPMAXPKTSZ */ ++ DC_FFOSZ, ++ /* DC_EPTYPE */ ++ DC_EPENABLE, DC_ENDPTYP, ++ /* DC_FRAMENUM */ ++ DC_FRAMENUM, DC_UFRAMENUM, ++ /* HW_OTG_CTRL_SET */ ++ HW_OTG_DISABLE, HW_SW_SEL_HC_DC, HW_VBUS_DRV, HW_SEL_CP_EXT, ++ HW_DM_PULLDOWN, HW_DP_PULLDOWN, HW_DP_PULLUP, ++ /* HW_OTG_CTRL_CLR */ ++ HW_OTG_DISABLE_CLEAR, HW_SW_SEL_HC_DC_CLEAR, HW_VBUS_DRV_CLEAR, ++ HW_SEL_CP_EXT_CLEAR, HW_DM_PULLDOWN_CLEAR, HW_DP_PULLDOWN_CLEAR, ++ HW_DP_PULLUP_CLEAR, ++ /* Last element */ ++ DC_FIELD_MAX, ++}; + + #endif +diff --git a/drivers/usb/isp1760/isp1760-udc.c b/drivers/usb/isp1760/isp1760-udc.c +index 1714b2258b54..1e2ca43fb152 100644 +--- a/drivers/usb/isp1760/isp1760-udc.c ++++ b/drivers/usb/isp1760/isp1760-udc.c +@@ -45,16 +45,62 @@ static inline struct isp1760_request *req_to_udc_req(struct usb_request *req) + return container_of(req, struct isp1760_request, req); + } + +-static inline u32 isp1760_udc_read(struct isp1760_udc *udc, u16 reg) ++static u32 isp1760_udc_read(struct isp1760_udc *udc, u16 field) + { +- return isp1760_read32(udc->regs, reg); ++ return isp1760_field_read(udc->fields, field); + } + +-static inline void isp1760_udc_write(struct isp1760_udc *udc, u16 reg, u32 val) ++static void isp1760_udc_write(struct isp1760_udc *udc, u16 field, u32 val) + { +- isp1760_write32(udc->regs, reg, val); ++ isp1760_field_write(udc->fields, field, val); + } + ++static u32 isp1760_udc_read_raw(struct isp1760_udc *udc, u16 reg) ++{ ++ __le32 val; ++ ++ regmap_raw_read(udc->regs, reg, &val, 4); ++ ++ return le32_to_cpu(val); ++} ++ ++static u16 isp1760_udc_read_raw16(struct isp1760_udc *udc, u16 reg) ++{ ++ __le16 val; ++ ++ regmap_raw_read(udc->regs, reg, &val, 2); ++ ++ return le16_to_cpu(val); ++} ++ ++static void isp1760_udc_write_raw(struct isp1760_udc *udc, u16 reg, u32 val) ++{ ++ __le32 val_le = cpu_to_le32(val); ++ ++ regmap_raw_write(udc->regs, reg, &val_le, 4); ++} ++ ++static void isp1760_udc_write_raw16(struct isp1760_udc *udc, u16 reg, u16 val) ++{ ++ __le16 val_le = cpu_to_le16(val); ++ ++ regmap_raw_write(udc->regs, reg, &val_le, 2); ++} ++ ++static void isp1760_udc_set(struct isp1760_udc *udc, u32 field) ++{ ++ isp1760_udc_write(udc, field, 0xFFFFFFFF); ++} ++ ++static void isp1760_udc_clear(struct isp1760_udc *udc, u32 field) ++{ ++ isp1760_udc_write(udc, field, 0); ++} ++ ++static bool isp1760_udc_is_set(struct isp1760_udc *udc, u32 field) ++{ ++ return !!isp1760_udc_read(udc, field); ++} + /* ----------------------------------------------------------------------------- + * Endpoint Management + */ +@@ -75,11 +121,15 @@ static struct isp1760_ep *isp1760_udc_find_ep(struct isp1760_udc *udc, + return NULL; + } + +-static void __isp1760_udc_select_ep(struct isp1760_ep *ep, int dir) ++static void __isp1760_udc_select_ep(struct isp1760_udc *udc, ++ struct isp1760_ep *ep, int dir) + { +- isp1760_udc_write(ep->udc, DC_EPINDEX, +- DC_ENDPIDX(ep->addr & USB_ENDPOINT_NUMBER_MASK) | +- (dir == USB_DIR_IN ? DC_EPDIR : 0)); ++ isp1760_udc_write(udc, DC_ENDPIDX, ep->addr & USB_ENDPOINT_NUMBER_MASK); ++ ++ if (dir == USB_DIR_IN) ++ isp1760_udc_set(udc, DC_EPDIR); ++ else ++ isp1760_udc_clear(udc, DC_EPDIR); + } + + /** +@@ -93,9 +143,10 @@ static void __isp1760_udc_select_ep(struct isp1760_ep *ep, int dir) + * + * Called with the UDC spinlock held. + */ +-static void isp1760_udc_select_ep(struct isp1760_ep *ep) ++static void isp1760_udc_select_ep(struct isp1760_udc *udc, ++ struct isp1760_ep *ep) + { +- __isp1760_udc_select_ep(ep, ep->addr & USB_ENDPOINT_DIR_MASK); ++ __isp1760_udc_select_ep(udc, ep, ep->addr & USB_ENDPOINT_DIR_MASK); + } + + /* Called with the UDC spinlock held. */ +@@ -108,9 +159,13 @@ static void isp1760_udc_ctrl_send_status(struct isp1760_ep *ep, int dir) + * the direction opposite to the data stage data packets, we thus need + * to select the OUT/IN endpoint for IN/OUT transfers. + */ +- isp1760_udc_write(udc, DC_EPINDEX, DC_ENDPIDX(0) | +- (dir == USB_DIR_IN ? 0 : DC_EPDIR)); +- isp1760_udc_write(udc, DC_CTRLFUNC, DC_STATUS); ++ if (dir == USB_DIR_IN) ++ isp1760_udc_clear(udc, DC_EPDIR); ++ else ++ isp1760_udc_set(udc, DC_EPDIR); ++ ++ isp1760_udc_write(udc, DC_ENDPIDX, 1); ++ isp1760_udc_set(udc, DC_STATUS); + + /* + * The hardware will terminate the request automatically and go back to +@@ -157,10 +212,10 @@ static void isp1760_udc_ctrl_send_stall(struct isp1760_ep *ep) + spin_lock_irqsave(&udc->lock, flags); + + /* Stall both the IN and OUT endpoints. */ +- __isp1760_udc_select_ep(ep, USB_DIR_OUT); +- isp1760_udc_write(udc, DC_CTRLFUNC, DC_STALL); +- __isp1760_udc_select_ep(ep, USB_DIR_IN); +- isp1760_udc_write(udc, DC_CTRLFUNC, DC_STALL); ++ __isp1760_udc_select_ep(udc, ep, USB_DIR_OUT); ++ isp1760_udc_set(udc, DC_STALL); ++ __isp1760_udc_select_ep(udc, ep, USB_DIR_IN); ++ isp1760_udc_set(udc, DC_STALL); + + /* A protocol stall completes the control transaction. */ + udc->ep0_state = ISP1760_CTRL_SETUP; +@@ -181,8 +236,8 @@ static bool isp1760_udc_receive(struct isp1760_ep *ep, + u32 *buf; + int i; + +- isp1760_udc_select_ep(ep); +- len = isp1760_udc_read(udc, DC_BUFLEN) & DC_DATACOUNT_MASK; ++ isp1760_udc_select_ep(udc, ep); ++ len = isp1760_udc_read(udc, DC_BUFLEN); + + dev_dbg(udc->isp->dev, "%s: received %u bytes (%u/%u done)\n", + __func__, len, req->req.actual, req->req.length); +@@ -198,7 +253,7 @@ static bool isp1760_udc_receive(struct isp1760_ep *ep, + * datasheet doesn't clearly document how this should be + * handled. + */ +- isp1760_udc_write(udc, DC_CTRLFUNC, DC_CLBUF); ++ isp1760_udc_set(udc, DC_CLBUF); + return false; + } + +@@ -209,9 +264,9 @@ static bool isp1760_udc_receive(struct isp1760_ep *ep, + * the next packet might be removed from the FIFO. + */ + for (i = len; i > 2; i -= 4, ++buf) +- *buf = le32_to_cpu(isp1760_udc_read(udc, DC_DATAPORT)); ++ *buf = isp1760_udc_read_raw(udc, ISP176x_DC_DATAPORT); + if (i > 0) +- *(u16 *)buf = le16_to_cpu(readw(udc->regs + DC_DATAPORT)); ++ *(u16 *)buf = isp1760_udc_read_raw16(udc, ISP176x_DC_DATAPORT); + + req->req.actual += len; + +@@ -253,7 +308,7 @@ static void isp1760_udc_transmit(struct isp1760_ep *ep, + __func__, req->packet_size, req->req.actual, + req->req.length); + +- __isp1760_udc_select_ep(ep, USB_DIR_IN); ++ __isp1760_udc_select_ep(udc, ep, USB_DIR_IN); + + if (req->packet_size) + isp1760_udc_write(udc, DC_BUFLEN, req->packet_size); +@@ -265,14 +320,14 @@ static void isp1760_udc_transmit(struct isp1760_ep *ep, + * the FIFO for this kind of conditions, but doesn't seem to work. + */ + for (i = req->packet_size; i > 2; i -= 4, ++buf) +- isp1760_udc_write(udc, DC_DATAPORT, cpu_to_le32(*buf)); ++ isp1760_udc_write_raw(udc, ISP176x_DC_DATAPORT, *buf); + if (i > 0) +- writew(cpu_to_le16(*(u16 *)buf), udc->regs + DC_DATAPORT); ++ isp1760_udc_write_raw16(udc, ISP176x_DC_DATAPORT, *(u16 *)buf); + + if (ep->addr == 0) +- isp1760_udc_write(udc, DC_CTRLFUNC, DC_DSEN); ++ isp1760_udc_set(udc, DC_DSEN); + if (!req->packet_size) +- isp1760_udc_write(udc, DC_CTRLFUNC, DC_VENDP); ++ isp1760_udc_set(udc, DC_VENDP); + } + + static void isp1760_ep_rx_ready(struct isp1760_ep *ep) +@@ -408,19 +463,24 @@ static int __isp1760_udc_set_halt(struct isp1760_ep *ep, bool halt) + return -EINVAL; + } + +- isp1760_udc_select_ep(ep); +- isp1760_udc_write(udc, DC_CTRLFUNC, halt ? DC_STALL : 0); ++ isp1760_udc_select_ep(udc, ep); ++ ++ if (halt) ++ isp1760_udc_set(udc, DC_STALL); ++ else ++ isp1760_udc_clear(udc, DC_STALL); + + if (ep->addr == 0) { + /* When halting the control endpoint, stall both IN and OUT. */ +- __isp1760_udc_select_ep(ep, USB_DIR_IN); +- isp1760_udc_write(udc, DC_CTRLFUNC, halt ? DC_STALL : 0); ++ __isp1760_udc_select_ep(udc, ep, USB_DIR_IN); ++ if (halt) ++ isp1760_udc_set(udc, DC_STALL); ++ else ++ isp1760_udc_clear(udc, DC_STALL); + } else if (!halt) { + /* Reset the data PID by cycling the endpoint enable bit. */ +- u16 eptype = isp1760_udc_read(udc, DC_EPTYPE); +- +- isp1760_udc_write(udc, DC_EPTYPE, eptype & ~DC_EPENABLE); +- isp1760_udc_write(udc, DC_EPTYPE, eptype); ++ isp1760_udc_clear(udc, DC_EPENABLE); ++ isp1760_udc_set(udc, DC_EPENABLE); + + /* + * Disabling the endpoint emptied the transmit FIFO, fill it +@@ -479,12 +539,14 @@ static int isp1760_udc_get_status(struct isp1760_udc *udc, + return -EINVAL; + } + +- isp1760_udc_write(udc, DC_EPINDEX, DC_ENDPIDX(0) | DC_EPDIR); ++ isp1760_udc_set(udc, DC_EPDIR); ++ isp1760_udc_write(udc, DC_ENDPIDX, 1); ++ + isp1760_udc_write(udc, DC_BUFLEN, 2); + +- writew(cpu_to_le16(status), udc->regs + DC_DATAPORT); ++ isp1760_udc_write_raw16(udc, ISP176x_DC_DATAPORT, status); + +- isp1760_udc_write(udc, DC_CTRLFUNC, DC_DSEN); ++ isp1760_udc_set(udc, DC_DSEN); + + dev_dbg(udc->isp->dev, "%s: status 0x%04x\n", __func__, status); + +@@ -508,7 +570,8 @@ static int isp1760_udc_set_address(struct isp1760_udc *udc, u16 addr) + usb_gadget_set_state(&udc->gadget, addr ? USB_STATE_ADDRESS : + USB_STATE_DEFAULT); + +- isp1760_udc_write(udc, DC_ADDRESS, DC_DEVEN | addr); ++ isp1760_udc_write(udc, DC_DEVADDR, addr); ++ isp1760_udc_set(udc, DC_DEVEN); + + spin_lock(&udc->lock); + isp1760_udc_ctrl_send_status(&udc->ep[0], USB_DIR_OUT); +@@ -650,9 +713,9 @@ static void isp1760_ep0_setup(struct isp1760_udc *udc) + + spin_lock(&udc->lock); + +- isp1760_udc_write(udc, DC_EPINDEX, DC_EP0SETUP); ++ isp1760_udc_set(udc, DC_EP0SETUP); + +- count = isp1760_udc_read(udc, DC_BUFLEN) & DC_DATACOUNT_MASK; ++ count = isp1760_udc_read(udc, DC_BUFLEN); + if (count != sizeof(req)) { + spin_unlock(&udc->lock); + +@@ -663,8 +726,8 @@ static void isp1760_ep0_setup(struct isp1760_udc *udc) + return; + } + +- req.data[0] = isp1760_udc_read(udc, DC_DATAPORT); +- req.data[1] = isp1760_udc_read(udc, DC_DATAPORT); ++ req.data[0] = isp1760_udc_read_raw(udc, ISP176x_DC_DATAPORT); ++ req.data[1] = isp1760_udc_read_raw(udc, ISP176x_DC_DATAPORT); + + if (udc->ep0_state != ISP1760_CTRL_SETUP) { + spin_unlock(&udc->lock); +@@ -732,13 +795,13 @@ static int isp1760_ep_enable(struct usb_ep *ep, + + switch (usb_endpoint_type(desc)) { + case USB_ENDPOINT_XFER_ISOC: +- type = DC_ENDPTYP_ISOC; ++ type = ISP176x_DC_ENDPTYP_ISOC; + break; + case USB_ENDPOINT_XFER_BULK: +- type = DC_ENDPTYP_BULK; ++ type = ISP176x_DC_ENDPTYP_BULK; + break; + case USB_ENDPOINT_XFER_INT: +- type = DC_ENDPTYP_INTERRUPT; ++ type = ISP176x_DC_ENDPTYP_INTERRUPT; + break; + case USB_ENDPOINT_XFER_CONTROL: + default: +@@ -755,10 +818,13 @@ static int isp1760_ep_enable(struct usb_ep *ep, + uep->halted = false; + uep->wedged = false; + +- isp1760_udc_select_ep(uep); +- isp1760_udc_write(udc, DC_EPMAXPKTSZ, uep->maxpacket); ++ isp1760_udc_select_ep(udc, uep); ++ ++ isp1760_udc_write(udc, DC_FFOSZ, uep->maxpacket); + isp1760_udc_write(udc, DC_BUFLEN, uep->maxpacket); +- isp1760_udc_write(udc, DC_EPTYPE, DC_EPENABLE | type); ++ ++ isp1760_udc_write(udc, DC_ENDPTYP, type); ++ isp1760_udc_set(udc, DC_EPENABLE); + + spin_unlock_irqrestore(&udc->lock, flags); + +@@ -786,8 +852,9 @@ static int isp1760_ep_disable(struct usb_ep *ep) + uep->desc = NULL; + uep->maxpacket = 0; + +- isp1760_udc_select_ep(uep); +- isp1760_udc_write(udc, DC_EPTYPE, 0); ++ isp1760_udc_select_ep(udc, uep); ++ isp1760_udc_clear(udc, DC_EPENABLE); ++ isp1760_udc_clear(udc, DC_ENDPTYP); + + /* TODO Synchronize with the IRQ handler */ + +@@ -864,8 +931,8 @@ static int isp1760_ep_queue(struct usb_ep *ep, struct usb_request *_req, + + case ISP1760_CTRL_DATA_OUT: + list_add_tail(&req->queue, &uep->queue); +- __isp1760_udc_select_ep(uep, USB_DIR_OUT); +- isp1760_udc_write(udc, DC_CTRLFUNC, DC_DSEN); ++ __isp1760_udc_select_ep(udc, uep, USB_DIR_OUT); ++ isp1760_udc_set(udc, DC_DSEN); + break; + + case ISP1760_CTRL_STATUS: +@@ -1025,14 +1092,14 @@ static void isp1760_ep_fifo_flush(struct usb_ep *ep) + + spin_lock_irqsave(&udc->lock, flags); + +- isp1760_udc_select_ep(uep); ++ isp1760_udc_select_ep(udc, uep); + + /* + * Set the CLBUF bit twice to flush both buffers in case double + * buffering is enabled. + */ +- isp1760_udc_write(udc, DC_CTRLFUNC, DC_CLBUF); +- isp1760_udc_write(udc, DC_CTRLFUNC, DC_CLBUF); ++ isp1760_udc_set(udc, DC_CLBUF); ++ isp1760_udc_set(udc, DC_CLBUF); + + spin_unlock_irqrestore(&udc->lock, flags); + } +@@ -1091,19 +1158,22 @@ static void isp1760_udc_init_hw(struct isp1760_udc *udc) + * ACK tokens only (and NYET for the out pipe). The default + * configuration also generates an interrupt on the first NACK token. + */ +- isp1760_udc_write(udc, DC_INTCONF, DC_CDBGMOD_ACK | DC_DDBGMODIN_ACK | +- DC_DDBGMODOUT_ACK_NYET); +- +- isp1760_udc_write(udc, DC_INTENABLE, DC_IEPRXTX(7) | DC_IEPRXTX(6) | +- DC_IEPRXTX(5) | DC_IEPRXTX(4) | DC_IEPRXTX(3) | +- DC_IEPRXTX(2) | DC_IEPRXTX(1) | DC_IEPRXTX(0) | +- DC_IEP0SETUP | DC_IEVBUS | DC_IERESM | DC_IESUSP | +- DC_IEHS_STA | DC_IEBRST); ++ isp1760_reg_write(udc->regs, ISP176x_DC_INTCONF, ++ ISP176x_DC_CDBGMOD_ACK | ISP176x_DC_DDBGMODIN_ACK | ++ ISP176x_DC_DDBGMODOUT_ACK); ++ ++ isp1760_reg_write(udc->regs, ISP176x_DC_INTENABLE, DC_IEPRXTX(7) | ++ DC_IEPRXTX(6) | DC_IEPRXTX(5) | DC_IEPRXTX(4) | ++ DC_IEPRXTX(3) | DC_IEPRXTX(2) | DC_IEPRXTX(1) | ++ DC_IEPRXTX(0) | ISP176x_DC_IEP0SETUP | ++ ISP176x_DC_IEVBUS | ISP176x_DC_IERESM | ++ ISP176x_DC_IESUSP | ISP176x_DC_IEHS_STA | ++ ISP176x_DC_IEBRST); + + if (udc->connected) + isp1760_set_pullup(udc->isp, true); + +- isp1760_udc_write(udc, DC_ADDRESS, DC_DEVEN); ++ isp1760_udc_set(udc, DC_DEVEN); + } + + static void isp1760_udc_reset(struct isp1760_udc *udc) +@@ -1152,7 +1222,7 @@ static int isp1760_udc_get_frame(struct usb_gadget *gadget) + { + struct isp1760_udc *udc = gadget_to_udc(gadget); + +- return isp1760_udc_read(udc, DC_FRAMENUM) & ((1 << 11) - 1); ++ return isp1760_udc_read(udc, DC_FRAMENUM); + } + + static int isp1760_udc_wakeup(struct usb_gadget *gadget) +@@ -1219,7 +1289,7 @@ static int isp1760_udc_start(struct usb_gadget *gadget, + usb_gadget_set_state(&udc->gadget, USB_STATE_ATTACHED); + + /* DMA isn't supported yet, don't enable the DMA clock. */ +- isp1760_udc_write(udc, DC_MODE, DC_GLINTENA); ++ isp1760_udc_set(udc, DC_GLINTENA); + + isp1760_udc_init_hw(udc); + +@@ -1238,7 +1308,7 @@ static int isp1760_udc_stop(struct usb_gadget *gadget) + + del_timer_sync(&udc->vbus_timer); + +- isp1760_udc_write(udc, DC_MODE, 0); ++ isp1760_reg_write(udc->regs, ISP176x_DC_MODE, 0); + + spin_lock_irqsave(&udc->lock, flags); + udc->driver = NULL; +@@ -1266,9 +1336,9 @@ static irqreturn_t isp1760_udc_irq(int irq, void *dev) + unsigned int i; + u32 status; + +- status = isp1760_udc_read(udc, DC_INTERRUPT) +- & isp1760_udc_read(udc, DC_INTENABLE); +- isp1760_udc_write(udc, DC_INTERRUPT, status); ++ status = isp1760_reg_read(udc->regs, ISP176x_DC_INTERRUPT) ++ & isp1760_reg_read(udc->regs, ISP176x_DC_INTENABLE); ++ isp1760_reg_write(udc->regs, ISP176x_DC_INTERRUPT, status); + + if (status & DC_IEVBUS) { + dev_dbg(udc->isp->dev, "%s(VBUS)\n", __func__); +@@ -1313,7 +1383,7 @@ static irqreturn_t isp1760_udc_irq(int irq, void *dev) + dev_dbg(udc->isp->dev, "%s(SUSP)\n", __func__); + + spin_lock(&udc->lock); +- if (!(isp1760_udc_read(udc, DC_MODE) & DC_VBUSSTAT)) ++ if (!isp1760_udc_is_set(udc, DC_VBUSSTAT)) + isp1760_udc_disconnect(udc); + else + isp1760_udc_suspend(udc); +@@ -1335,7 +1405,7 @@ static void isp1760_udc_vbus_poll(struct timer_list *t) + + spin_lock_irqsave(&udc->lock, flags); + +- if (!(isp1760_udc_read(udc, DC_MODE) & DC_VBUSSTAT)) ++ if (!(isp1760_udc_is_set(udc, DC_VBUSSTAT))) + isp1760_udc_disconnect(udc); + else if (udc->gadget.state >= USB_STATE_POWERED) + mod_timer(&udc->vbus_timer, +@@ -1412,9 +1482,9 @@ static int isp1760_udc_init(struct isp1760_udc *udc) + * register, and reading the scratch register value back. The chip ID + * and scratch register contents must match the expected values. + */ +- isp1760_udc_write(udc, DC_SCRATCH, 0xbabe); +- chipid = isp1760_udc_read(udc, DC_CHIPID); +- scratch = isp1760_udc_read(udc, DC_SCRATCH); ++ isp1760_reg_write(udc->regs, ISP176x_DC_SCRATCH, 0xbabe); ++ chipid = isp1760_reg_read(udc->regs, ISP176x_DC_CHIPID); ++ scratch = isp1760_reg_read(udc->regs, ISP176x_DC_SCRATCH); + + if (scratch != 0xbabe) { + dev_err(udc->isp->dev, +@@ -1429,9 +1499,9 @@ static int isp1760_udc_init(struct isp1760_udc *udc) + } + + /* Reset the device controller. */ +- isp1760_udc_write(udc, DC_MODE, DC_SFRESET); ++ isp1760_udc_set(udc, DC_SFRESET); + usleep_range(10000, 11000); +- isp1760_udc_write(udc, DC_MODE, 0); ++ isp1760_reg_write(udc->regs, ISP176x_DC_MODE, 0); + usleep_range(10000, 11000); + + return 0; +@@ -1445,7 +1515,6 @@ int isp1760_udc_register(struct isp1760_device *isp, int irq, + + udc->irq = -1; + udc->isp = isp; +- udc->regs = isp->regs; + + spin_lock_init(&udc->lock); + timer_setup(&udc->vbus_timer, isp1760_udc_vbus_poll, 0); +diff --git a/drivers/usb/isp1760/isp1760-udc.h b/drivers/usb/isp1760/isp1760-udc.h +index d2df650d54e9..a49096c0ac8e 100644 +--- a/drivers/usb/isp1760/isp1760-udc.h ++++ b/drivers/usb/isp1760/isp1760-udc.h +@@ -17,6 +17,8 @@ + #include + #include + ++#include "isp1760-regs.h" ++ + struct isp1760_device; + struct isp1760_udc; + +@@ -48,7 +50,7 @@ struct isp1760_ep { + * struct isp1760_udc - UDC state information + * irq: IRQ number + * irqname: IRQ name (as passed to request_irq) +- * regs: Base address of the UDC registers ++ * regs: regmap for UDC registers + * driver: Gadget driver + * gadget: Gadget device + * lock: Protects driver, vbus_timer, ep, ep0_*, DC_EPINDEX register +@@ -59,12 +61,13 @@ struct isp1760_ep { + * connected: Tracks gadget driver bus connection state + */ + struct isp1760_udc { +-#ifdef CONFIG_USB_ISP1761_UDC + struct isp1760_device *isp; + + int irq; + char *irqname; +- void __iomem *regs; ++ ++ struct regmap *regs; ++ struct regmap_field *fields[DC_FIELD_MAX]; + + struct usb_gadget_driver *driver; + struct usb_gadget gadget; +@@ -81,7 +84,6 @@ struct isp1760_udc { + bool connected; + + unsigned int devstatus; +-#endif + }; + + #ifdef CONFIG_USB_ISP1761_UDC +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0003-usb-isp1760-use-relaxed-primitives.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0003-usb-isp1760-use-relaxed-primitives.patch new file mode 100644 index 0000000..2e2e97a --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0003-usb-isp1760-use-relaxed-primitives.patch @@ -0,0 +1,64 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From 03e28d5233d50fb2a27fa02d032e77974d03eb2b Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 13 May 2021 09:47:11 +0100 +Subject: [PATCH 03/23] usb: isp1760: use relaxed primitives + +Use io relaxed access memory primitives to satisfy strict type +checking (__force). + +This will fix some existing sparse warnings: +sparse: warning: cast to restricted __le32 + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210513084717.2487366-4-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-hcd.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index 20d142140574..2cc0555e029d 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -246,7 +246,7 @@ static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, + + if (src_offset < PAYLOAD_OFFSET) { + while (bytes >= 4) { +- *dst = le32_to_cpu(__raw_readl(src)); ++ *dst = readl_relaxed(src); + bytes -= 4; + src++; + dst++; +@@ -267,7 +267,7 @@ static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, + * allocated. + */ + if (src_offset < PAYLOAD_OFFSET) +- val = le32_to_cpu(__raw_readl(src)); ++ val = readl_relaxed(src); + else + val = __raw_readl(src); + +@@ -301,7 +301,7 @@ static void mem_writes8(void __iomem *dst_base, u32 dst_offset, + + if (dst_offset < PAYLOAD_OFFSET) { + while (bytes >= 4) { +- __raw_writel(cpu_to_le32(*src), dst); ++ writel_relaxed(*src, dst); + bytes -= 4; + src++; + dst++; +@@ -322,7 +322,7 @@ static void mem_writes8(void __iomem *dst_base, u32 dst_offset, + */ + + if (dst_offset < PAYLOAD_OFFSET) +- __raw_writel(cpu_to_le32(*src), dst); ++ writel_relaxed(*src, dst); + else + __raw_writel(*src, dst); + } +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0004-usb-isp1760-remove-platform-data-struct-and-code.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0004-usb-isp1760-remove-platform-data-struct-and-code.patch new file mode 100644 index 0000000..b8a3fab --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0004-usb-isp1760-remove-platform-data-struct-and-code.patch @@ -0,0 +1,62 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From f9a88370e6751c68a8f0d1c3f23100ca20596249 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 13 May 2021 09:47:12 +0100 +Subject: [PATCH 04/23] usb: isp1760: remove platform data struct and code + +Since the removal of the Blackfin port with: +commit 4ba66a976072 ("arch: remove blackfin port") + +No one is using or referencing this header and platform data struct. +Remove them. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210513084717.2487366-5-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-if.c | 20 +++----------------- + 1 file changed, 3 insertions(+), 17 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-if.c b/drivers/usb/isp1760/isp1760-if.c +index abfba9f5ec23..fb6701608cd8 100644 +--- a/drivers/usb/isp1760/isp1760-if.c ++++ b/drivers/usb/isp1760/isp1760-if.c +@@ -16,7 +16,6 @@ + #include + #include + #include +-#include + #include + + #include "isp1760-core.h" +@@ -225,22 +224,9 @@ static int isp1760_plat_probe(struct platform_device *pdev) + + if (of_property_read_bool(dp, "dreq-polarity")) + devflags |= ISP1760_FLAG_DREQ_POL_HIGH; +- } else if (dev_get_platdata(&pdev->dev)) { +- struct isp1760_platform_data *pdata = +- dev_get_platdata(&pdev->dev); +- +- if (pdata->is_isp1761) +- devflags |= ISP1760_FLAG_ISP1761; +- if (pdata->bus_width_16) +- devflags |= ISP1760_FLAG_BUS_WIDTH_16; +- if (pdata->port1_otg) +- devflags |= ISP1760_FLAG_OTG_EN; +- if (pdata->analog_oc) +- devflags |= ISP1760_FLAG_ANALOG_OC; +- if (pdata->dack_polarity_high) +- devflags |= ISP1760_FLAG_DACK_POL_HIGH; +- if (pdata->dreq_polarity_high) +- devflags |= ISP1760_FLAG_DREQ_POL_HIGH; ++ } else { ++ pr_err("isp1760: no platform data\n"); ++ return -ENXIO; + } + + ret = isp1760_register(mem_res, irq_res->start, irqflags, &pdev->dev, +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0005-usb-isp1760-hcd-refactor-mempool-config-and-setup.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0005-usb-isp1760-hcd-refactor-mempool-config-and-setup.patch new file mode 100644 index 0000000..238c1bd --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0005-usb-isp1760-hcd-refactor-mempool-config-and-setup.patch @@ -0,0 +1,304 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From a74f639c5b5618e2c9f311c93bc3e7405de8ca85 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 13 May 2021 09:47:13 +0100 +Subject: [PATCH 05/23] usb: isp1760: hcd: refactor mempool config and setup + +In preparation to support other family member IP, which may have +different memory layout. Drop macros and setup a configuration +struct. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210513084717.2487366-6-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-core.c | 21 ++++++++ + drivers/usb/isp1760/isp1760-hcd.c | 83 ++++++++++++++++++++---------- + drivers/usb/isp1760/isp1760-hcd.h | 37 ++++++------- + 3 files changed, 92 insertions(+), 49 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-core.c b/drivers/usb/isp1760/isp1760-core.c +index c79ba98df9f9..35a7667e411c 100644 +--- a/drivers/usb/isp1760/isp1760-core.c ++++ b/drivers/usb/isp1760/isp1760-core.c +@@ -101,6 +101,25 @@ void isp1760_set_pullup(struct isp1760_device *isp, bool enable) + isp1760_field_set(udc->fields, HW_DP_PULLUP_CLEAR); + } + ++/* ++ * 60kb divided in: ++ * - 32 blocks @ 256 bytes ++ * - 20 blocks @ 1024 bytes ++ * - 4 blocks @ 8192 bytes ++ */ ++static const struct isp1760_memory_layout isp176x_memory_conf = { ++ .blocks[0] = 32, ++ .blocks_size[0] = 256, ++ .blocks[1] = 20, ++ .blocks_size[1] = 1024, ++ .blocks[2] = 4, ++ .blocks_size[2] = 8192, ++ ++ .ptd_num = 32, ++ .payload_blocks = 32 + 20 + 4, ++ .payload_area_size = 0xf000, ++}; ++ + static const struct regmap_range isp176x_hc_volatile_ranges[] = { + regmap_reg_range(ISP176x_HC_USBCMD, ISP176x_HC_ATL_PTD_LASTPTD), + regmap_reg_range(ISP176x_HC_BUFFER_STATUS, ISP176x_HC_MEMORY), +@@ -302,6 +321,8 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + udc->fields[i] = f; + } + ++ hcd->memory_layout = &isp176x_memory_conf; ++ + isp1760_init_core(isp); + + if (IS_ENABLED(CONFIG_USB_ISP1760_HCD) && !usb_disabled()) { +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index 2cc0555e029d..a65f5f917ebe 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -358,39 +358,29 @@ static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, + /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ + static void init_memory(struct isp1760_hcd *priv) + { +- int i, curr; ++ const struct isp1760_memory_layout *mem = priv->memory_layout; ++ int i, j, curr; + u32 payload_addr; + + payload_addr = PAYLOAD_OFFSET; +- for (i = 0; i < BLOCK_1_NUM; i++) { +- priv->memory_pool[i].start = payload_addr; +- priv->memory_pool[i].size = BLOCK_1_SIZE; +- priv->memory_pool[i].free = 1; +- payload_addr += priv->memory_pool[i].size; +- } +- +- curr = i; +- for (i = 0; i < BLOCK_2_NUM; i++) { +- priv->memory_pool[curr + i].start = payload_addr; +- priv->memory_pool[curr + i].size = BLOCK_2_SIZE; +- priv->memory_pool[curr + i].free = 1; +- payload_addr += priv->memory_pool[curr + i].size; +- } + +- curr = i; +- for (i = 0; i < BLOCK_3_NUM; i++) { +- priv->memory_pool[curr + i].start = payload_addr; +- priv->memory_pool[curr + i].size = BLOCK_3_SIZE; +- priv->memory_pool[curr + i].free = 1; +- payload_addr += priv->memory_pool[curr + i].size; ++ for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++) { ++ for (j = 0; j < mem->blocks[i]; j++, curr++) { ++ priv->memory_pool[curr + j].start = payload_addr; ++ priv->memory_pool[curr + j].size = mem->blocks_size[i]; ++ priv->memory_pool[curr + j].free = 1; ++ payload_addr += priv->memory_pool[curr + j].size; ++ } + } + +- WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE); ++ WARN_ON(payload_addr - priv->memory_pool[0].start > ++ mem->payload_area_size); + } + + static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; + int i; + + WARN_ON(qtd->payload_addr); +@@ -398,7 +388,7 @@ static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) + if (!qtd->length) + return; + +- for (i = 0; i < BLOCKS; i++) { ++ for (i = 0; i < mem->payload_blocks; i++) { + if (priv->memory_pool[i].size >= qtd->length && + priv->memory_pool[i].free) { + priv->memory_pool[i].free = 0; +@@ -411,12 +401,13 @@ static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) + static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; + int i; + + if (!qtd->payload_addr) + return; + +- for (i = 0; i < BLOCKS; i++) { ++ for (i = 0; i < mem->payload_blocks; i++) { + if (priv->memory_pool[i].start == qtd->payload_addr) { + WARN_ON(priv->memory_pool[i].free); + priv->memory_pool[i].free = 1; +@@ -1407,8 +1398,6 @@ static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) + { + qtd->data_buffer = databuffer; + +- if (len > MAX_PAYLOAD_SIZE) +- len = MAX_PAYLOAD_SIZE; + qtd->length = len; + + return qtd->length; +@@ -1432,6 +1421,8 @@ static void qtd_list_free(struct list_head *qtd_list) + static void packetize_urb(struct usb_hcd *hcd, + struct urb *urb, struct list_head *head, gfp_t flags) + { ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; + struct isp1760_qtd *qtd; + void *buf; + int len, maxpacketsize; +@@ -1484,6 +1475,10 @@ static void packetize_urb(struct usb_hcd *hcd, + qtd = qtd_alloc(flags, urb, packet_type); + if (!qtd) + goto cleanup; ++ ++ if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1]) ++ len = mem->blocks_size[ISP176x_BLOCK_NUM - 1]; ++ + this_qtd_len = qtd_fill(qtd, buf, len); + list_add_tail(&qtd->qtd_list, head); + +@@ -2212,6 +2207,7 @@ int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, + int irq, unsigned long irqflags, + struct device *dev) + { ++ const struct isp1760_memory_layout *mem_layout = priv->memory_layout; + struct usb_hcd *hcd; + int ret; + +@@ -2223,6 +2219,28 @@ int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, + + priv->hcd = hcd; + ++ priv->memory_pool = kcalloc(mem_layout->payload_blocks, ++ sizeof(struct isp1760_memory_chunk), ++ GFP_KERNEL); ++ if (!priv->memory_pool) { ++ ret = -ENOMEM; ++ goto put_hcd; ++ } ++ ++ priv->atl_slots = kcalloc(mem_layout->ptd_num, ++ sizeof(struct isp1760_slotinfo), GFP_KERNEL); ++ if (!priv->atl_slots) { ++ ret = -ENOMEM; ++ goto free_mem_pool; ++ } ++ ++ priv->int_slots = kcalloc(mem_layout->ptd_num, ++ sizeof(struct isp1760_slotinfo), GFP_KERNEL); ++ if (!priv->int_slots) { ++ ret = -ENOMEM; ++ goto free_atl_slots; ++ } ++ + init_memory(priv); + + hcd->irq = irq; +@@ -2234,13 +2252,19 @@ int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, + + ret = usb_add_hcd(hcd, irq, irqflags); + if (ret) +- goto error; ++ goto free_int_slots; + + device_wakeup_enable(hcd->self.controller); + + return 0; + +-error: ++free_int_slots: ++ kfree(priv->int_slots); ++free_atl_slots: ++ kfree(priv->atl_slots); ++free_mem_pool: ++ kfree(priv->memory_pool); ++put_hcd: + usb_put_hcd(hcd); + return ret; + } +@@ -2252,4 +2276,7 @@ void isp1760_hcd_unregister(struct isp1760_hcd *priv) + + usb_remove_hcd(priv->hcd); + usb_put_hcd(priv->hcd); ++ kfree(priv->atl_slots); ++ kfree(priv->int_slots); ++ kfree(priv->memory_pool); + } +diff --git a/drivers/usb/isp1760/isp1760-hcd.h b/drivers/usb/isp1760/isp1760-hcd.h +index 34e1899e52c4..9d2427ce3f1a 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.h ++++ b/drivers/usb/isp1760/isp1760-hcd.h +@@ -12,24 +12,6 @@ struct isp1760_qtd; + struct resource; + struct usb_hcd; + +-/* +- * 60kb divided in: +- * - 32 blocks @ 256 bytes +- * - 20 blocks @ 1024 bytes +- * - 4 blocks @ 8192 bytes +- */ +- +-#define BLOCK_1_NUM 32 +-#define BLOCK_2_NUM 20 +-#define BLOCK_3_NUM 4 +- +-#define BLOCK_1_SIZE 256 +-#define BLOCK_2_SIZE 1024 +-#define BLOCK_3_SIZE 8192 +-#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM) +-#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE +-#define PAYLOAD_AREA_SIZE 0xf000 +- + struct isp1760_slotinfo { + struct isp1760_qh *qh; + struct isp1760_qtd *qtd; +@@ -37,6 +19,17 @@ struct isp1760_slotinfo { + }; + + /* chip memory management */ ++#define ISP176x_BLOCK_NUM 3 ++ ++struct isp1760_memory_layout { ++ unsigned int blocks[ISP176x_BLOCK_NUM]; ++ unsigned int blocks_size[ISP176x_BLOCK_NUM]; ++ ++ unsigned int ptd_num; ++ unsigned int payload_blocks; ++ unsigned int payload_area_size; ++}; ++ + struct isp1760_memory_chunk { + unsigned int start; + unsigned int size; +@@ -58,12 +51,14 @@ struct isp1760_hcd { + struct regmap *regs; + struct regmap_field *fields[HC_FIELD_MAX]; + ++ const struct isp1760_memory_layout *memory_layout; ++ + spinlock_t lock; +- struct isp1760_slotinfo atl_slots[32]; ++ struct isp1760_slotinfo *atl_slots; + int atl_done_map; +- struct isp1760_slotinfo int_slots[32]; ++ struct isp1760_slotinfo *int_slots; + int int_done_map; +- struct isp1760_memory_chunk memory_pool[BLOCKS]; ++ struct isp1760_memory_chunk *memory_pool; + struct list_head qh_list[QH_END]; + + /* periodic schedule support */ +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0006-usb-isp1760-use-dr_mode-binding.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0006-usb-isp1760-use-dr_mode-binding.patch new file mode 100644 index 0000000..e696535 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0006-usb-isp1760-use-dr_mode-binding.patch @@ -0,0 +1,78 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From 3eb96e04be9918afa54b64fac943de86a9798bda Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 13 May 2021 09:47:14 +0100 +Subject: [PATCH 06/23] usb: isp1760: use dr_mode binding + +There is already a binding to describe the dual role mode (dr_mode), +use that instead of defining a new one (port1-otg). + +Update driver code and devicetree files that use that port1-otg +binding. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210513084717.2487366-7-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-core.c | 3 +-- + drivers/usb/isp1760/isp1760-core.h | 2 +- + drivers/usb/isp1760/isp1760-if.c | 5 +++-- + 3 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-core.c b/drivers/usb/isp1760/isp1760-core.c +index 35a7667e411c..0aeeb12d3bfe 100644 +--- a/drivers/usb/isp1760/isp1760-core.c ++++ b/drivers/usb/isp1760/isp1760-core.c +@@ -73,10 +73,9 @@ static void isp1760_init_core(struct isp1760_device *isp) + * on ISP1761. + * + * TODO: Really support OTG. For now we configure port 1 in device mode +- * when OTG is requested. + */ + if ((isp->devflags & ISP1760_FLAG_ISP1761) && +- (isp->devflags & ISP1760_FLAG_OTG_EN)) { ++ (isp->devflags & ISP1760_FLAG_PERIPHERAL_EN)) { + isp1760_field_set(hcd->fields, HW_DM_PULLDOWN); + isp1760_field_set(hcd->fields, HW_DP_PULLDOWN); + isp1760_field_set(hcd->fields, HW_OTG_DISABLE); +diff --git a/drivers/usb/isp1760/isp1760-core.h b/drivers/usb/isp1760/isp1760-core.h +index 8fec6395f19f..7a6755d68d41 100644 +--- a/drivers/usb/isp1760/isp1760-core.h ++++ b/drivers/usb/isp1760/isp1760-core.h +@@ -28,7 +28,7 @@ struct gpio_desc; + * a sane default configuration. + */ + #define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */ +-#define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */ ++#define ISP1760_FLAG_PERIPHERAL_EN 0x00000004 /* Port 1 supports Peripheral mode*/ + #define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */ + #define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */ + #define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */ +diff --git a/drivers/usb/isp1760/isp1760-if.c b/drivers/usb/isp1760/isp1760-if.c +index fb6701608cd8..cb3e4d782315 100644 +--- a/drivers/usb/isp1760/isp1760-if.c ++++ b/drivers/usb/isp1760/isp1760-if.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + + #include "isp1760-core.h" + #include "isp1760-regs.h" +@@ -213,8 +214,8 @@ static int isp1760_plat_probe(struct platform_device *pdev) + if (bus_width == 16) + devflags |= ISP1760_FLAG_BUS_WIDTH_16; + +- if (of_property_read_bool(dp, "port1-otg")) +- devflags |= ISP1760_FLAG_OTG_EN; ++ if (usb_get_dr_mode(&pdev->dev) == USB_DR_MODE_PERIPHERAL) ++ devflags |= ISP1760_FLAG_PERIPHERAL_EN; + + if (of_property_read_bool(dp, "analog-oc")) + devflags |= ISP1760_FLAG_ANALOG_OC; +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0007-usb-isp1760-add-support-for-isp1763.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0007-usb-isp1760-add-support-for-isp1763.patch new file mode 100644 index 0000000..78a483c --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0007-usb-isp1760-add-support-for-isp1763.patch @@ -0,0 +1,1894 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From 60d789f3bfbb7428e6ba2949de70a6db8e12e8fa Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 13 May 2021 09:47:15 +0100 +Subject: [PATCH 07/23] usb: isp1760: add support for isp1763 + +isp1763 have some differences from the isp1760, 8 bit address for +registers and 16 bit for values, no bulk access to memory addresses, +16 PTD's instead of 32. + +Following the regmap work done before add the registers, memory access +and add the functions to support differences in setup sequences. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210513084717.2487366-8-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/Kconfig | 4 +- + drivers/usb/isp1760/isp1760-core.c | 301 ++++++++++++-- + drivers/usb/isp1760/isp1760-core.h | 4 + + drivers/usb/isp1760/isp1760-hcd.c | 627 ++++++++++++++++++++++------- + drivers/usb/isp1760/isp1760-hcd.h | 6 +- + drivers/usb/isp1760/isp1760-if.c | 12 +- + drivers/usb/isp1760/isp1760-regs.h | 95 ++++- + drivers/usb/isp1760/isp1760-udc.c | 2 + + drivers/usb/isp1760/isp1760-udc.h | 2 + + 9 files changed, 849 insertions(+), 204 deletions(-) + +diff --git a/drivers/usb/isp1760/Kconfig b/drivers/usb/isp1760/Kconfig +index d23853f601b1..2ed2b73291d1 100644 +--- a/drivers/usb/isp1760/Kconfig ++++ b/drivers/usb/isp1760/Kconfig +@@ -1,11 +1,11 @@ + # SPDX-License-Identifier: GPL-2.0 + + config USB_ISP1760 +- tristate "NXP ISP 1760/1761 support" ++ tristate "NXP ISP 1760/1761/1763 support" + depends on USB || USB_GADGET + select REGMAP_MMIO + help +- Say Y or M here if your system as an ISP1760 USB host controller ++ Say Y or M here if your system as an ISP1760/1763 USB host controller + or an ISP1761 USB dual-role controller. + + This driver does not support isochronous transfers or OTG. +diff --git a/drivers/usb/isp1760/isp1760-core.c b/drivers/usb/isp1760/isp1760-core.c +index 0aeeb12d3bfe..1d847f13abab 100644 +--- a/drivers/usb/isp1760/isp1760-core.c ++++ b/drivers/usb/isp1760/isp1760-core.c +@@ -2,12 +2,14 @@ + /* + * Driver for the NXP ISP1760 chip + * ++ * Copyright 2021 Linaro, Rui Miguel Silva + * Copyright 2014 Laurent Pinchart + * Copyright 2007 Sebastian Siewior + * + * Contacts: + * Sebastian Siewior + * Laurent Pinchart ++ * Rui Miguel Silva + */ + + #include +@@ -24,7 +26,7 @@ + #include "isp1760-regs.h" + #include "isp1760-udc.h" + +-static void isp1760_init_core(struct isp1760_device *isp) ++static int isp1760_init_core(struct isp1760_device *isp) + { + struct isp1760_hcd *hcd = &isp->hcd; + struct isp1760_udc *udc = &isp->udc; +@@ -44,8 +46,15 @@ static void isp1760_init_core(struct isp1760_device *isp) + msleep(100); + + /* Setup HW Mode Control: This assumes a level active-low interrupt */ ++ if ((isp->devflags & ISP1760_FLAG_ANALOG_OC) && hcd->is_isp1763) { ++ dev_err(isp->dev, "isp1763 analog overcurrent not available\n"); ++ return -EINVAL; ++ } ++ + if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_16) + isp1760_field_clear(hcd->fields, HW_DATA_BUS_WIDTH); ++ if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_8) ++ isp1760_field_set(hcd->fields, HW_DATA_BUS_WIDTH); + if (isp->devflags & ISP1760_FLAG_ANALOG_OC) + isp1760_field_set(hcd->fields, HW_ANA_DIGI_OC); + if (isp->devflags & ISP1760_FLAG_DACK_POL_HIGH) +@@ -85,9 +94,14 @@ static void isp1760_init_core(struct isp1760_device *isp) + isp1760_field_set(hcd->fields, HW_SEL_CP_EXT); + } + +- dev_info(isp->dev, "bus width: %u, oc: %s\n", ++ dev_info(isp->dev, "%s bus width: %u, oc: %s\n", ++ hcd->is_isp1763 ? "isp1763" : "isp1760", ++ isp->devflags & ISP1760_FLAG_BUS_WIDTH_8 ? 8 : + isp->devflags & ISP1760_FLAG_BUS_WIDTH_16 ? 16 : 32, ++ hcd->is_isp1763 ? "not available" : + isp->devflags & ISP1760_FLAG_ANALOG_OC ? "analog" : "digital"); ++ ++ return 0; + } + + void isp1760_set_pullup(struct isp1760_device *isp, bool enable) +@@ -101,6 +115,8 @@ void isp1760_set_pullup(struct isp1760_device *isp, bool enable) + } + + /* ++ * ISP1760/61: ++ * + * 60kb divided in: + * - 32 blocks @ 256 bytes + * - 20 blocks @ 1024 bytes +@@ -114,15 +130,36 @@ static const struct isp1760_memory_layout isp176x_memory_conf = { + .blocks[2] = 4, + .blocks_size[2] = 8192, + +- .ptd_num = 32, ++ .slot_num = 32, + .payload_blocks = 32 + 20 + 4, + .payload_area_size = 0xf000, + }; + ++/* ++ * ISP1763: ++ * ++ * 20kb divided in: ++ * - 8 blocks @ 256 bytes ++ * - 2 blocks @ 1024 bytes ++ * - 4 blocks @ 4096 bytes ++ */ ++static const struct isp1760_memory_layout isp1763_memory_conf = { ++ .blocks[0] = 8, ++ .blocks_size[0] = 256, ++ .blocks[1] = 2, ++ .blocks_size[1] = 1024, ++ .blocks[2] = 4, ++ .blocks_size[2] = 4096, ++ ++ .slot_num = 16, ++ .payload_blocks = 8 + 2 + 4, ++ .payload_area_size = 0x5000, ++}; ++ + static const struct regmap_range isp176x_hc_volatile_ranges[] = { + regmap_reg_range(ISP176x_HC_USBCMD, ISP176x_HC_ATL_PTD_LASTPTD), + regmap_reg_range(ISP176x_HC_BUFFER_STATUS, ISP176x_HC_MEMORY), +- regmap_reg_range(ISP176x_HC_INTERRUPT, ISP176x_HC_ATL_IRQ_MASK_AND), ++ regmap_reg_range(ISP176x_HC_INTERRUPT, ISP176x_HC_OTG_CTRL_CLEAR), + }; + + static const struct regmap_access_table isp176x_hc_volatile_table = { +@@ -130,13 +167,13 @@ static const struct regmap_access_table isp176x_hc_volatile_table = { + .n_yes_ranges = ARRAY_SIZE(isp176x_hc_volatile_ranges), + }; + +-static struct regmap_config isp1760_hc_regmap_conf = { ++static const struct regmap_config isp1760_hc_regmap_conf = { + .name = "isp1760-hc", + .reg_bits = 16, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +- .max_register = ISP176x_HC_MEMORY, ++ .max_register = ISP176x_HC_OTG_CTRL_CLEAR, + .volatile_table = &isp176x_hc_volatile_table, + }; + +@@ -151,6 +188,15 @@ static const struct reg_field isp1760_hc_reg_fields[] = { + [STS_PCD] = REG_FIELD(ISP176x_HC_USBSTS, 2, 2), + [HC_FRINDEX] = REG_FIELD(ISP176x_HC_FRINDEX, 0, 13), + [FLAG_CF] = REG_FIELD(ISP176x_HC_CONFIGFLAG, 0, 0), ++ [HC_ISO_PTD_DONEMAP] = REG_FIELD(ISP176x_HC_ISO_PTD_DONEMAP, 0, 31), ++ [HC_ISO_PTD_SKIPMAP] = REG_FIELD(ISP176x_HC_ISO_PTD_SKIPMAP, 0, 31), ++ [HC_ISO_PTD_LASTPTD] = REG_FIELD(ISP176x_HC_ISO_PTD_LASTPTD, 0, 31), ++ [HC_INT_PTD_DONEMAP] = REG_FIELD(ISP176x_HC_INT_PTD_DONEMAP, 0, 31), ++ [HC_INT_PTD_SKIPMAP] = REG_FIELD(ISP176x_HC_INT_PTD_SKIPMAP, 0, 31), ++ [HC_INT_PTD_LASTPTD] = REG_FIELD(ISP176x_HC_INT_PTD_LASTPTD, 0, 31), ++ [HC_ATL_PTD_DONEMAP] = REG_FIELD(ISP176x_HC_ATL_PTD_DONEMAP, 0, 31), ++ [HC_ATL_PTD_SKIPMAP] = REG_FIELD(ISP176x_HC_ATL_PTD_SKIPMAP, 0, 31), ++ [HC_ATL_PTD_LASTPTD] = REG_FIELD(ISP176x_HC_ATL_PTD_LASTPTD, 0, 31), + [PORT_OWNER] = REG_FIELD(ISP176x_HC_PORTSC1, 13, 13), + [PORT_POWER] = REG_FIELD(ISP176x_HC_PORTSC1, 12, 12), + [PORT_LSTATUS] = REG_FIELD(ISP176x_HC_PORTSC1, 10, 11), +@@ -169,18 +215,135 @@ static const struct reg_field isp1760_hc_reg_fields[] = { + [HW_INTR_HIGH_ACT] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 2, 2), + [HW_INTR_EDGE_TRIG] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 1, 1), + [HW_GLOBAL_INTR_EN] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 0, 0), ++ [HC_CHIP_REV] = REG_FIELD(ISP176x_HC_CHIP_ID, 16, 31), ++ [HC_CHIP_ID_HIGH] = REG_FIELD(ISP176x_HC_CHIP_ID, 8, 15), ++ [HC_CHIP_ID_LOW] = REG_FIELD(ISP176x_HC_CHIP_ID, 0, 7), ++ [HC_SCRATCH] = REG_FIELD(ISP176x_HC_SCRATCH, 0, 31), + [SW_RESET_RESET_ALL] = REG_FIELD(ISP176x_HC_RESET, 0, 0), ++ [ISO_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 2, 2), + [INT_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 1, 1), + [ATL_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 0, 0), + [MEM_BANK_SEL] = REG_FIELD(ISP176x_HC_MEMORY, 16, 17), + [MEM_START_ADDR] = REG_FIELD(ISP176x_HC_MEMORY, 0, 15), +- [HC_INT_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 7, 8), ++ [HC_INTERRUPT] = REG_FIELD(ISP176x_HC_INTERRUPT, 0, 9), ++ [HC_ATL_IRQ_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 8, 8), ++ [HC_INT_IRQ_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 7, 7), ++ [HC_ISO_IRQ_MASK_OR] = REG_FIELD(ISP176x_HC_ISO_IRQ_MASK_OR, 0, 31), ++ [HC_INT_IRQ_MASK_OR] = REG_FIELD(ISP176x_HC_INT_IRQ_MASK_OR, 0, 31), ++ [HC_ATL_IRQ_MASK_OR] = REG_FIELD(ISP176x_HC_ATL_IRQ_MASK_OR, 0, 31), ++ [HC_ISO_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_ISO_IRQ_MASK_AND, 0, 31), ++ [HC_INT_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_INT_IRQ_MASK_AND, 0, 31), ++ [HC_ATL_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_ATL_IRQ_MASK_AND, 0, 31), ++ [HW_OTG_DISABLE] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 10, 10), ++ [HW_SW_SEL_HC_DC] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 7, 7), ++ [HW_VBUS_DRV] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 4, 4), ++ [HW_SEL_CP_EXT] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 3, 3), ++ [HW_DM_PULLDOWN] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 2, 2), ++ [HW_DP_PULLDOWN] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 1, 1), ++ [HW_DP_PULLUP] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 0, 0), ++ [HW_OTG_DISABLE_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 10, 10), ++ [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 7, 7), ++ [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 4, 4), ++ [HW_SEL_CP_EXT_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 3, 3), ++ [HW_DM_PULLDOWN_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 2, 2), ++ [HW_DP_PULLDOWN_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 1, 1), ++ [HW_DP_PULLUP_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 0, 0), ++}; ++ ++static const struct reg_field isp1763_hc_reg_fields[] = { ++ [CMD_LRESET] = REG_FIELD(ISP1763_HC_USBCMD, 7, 7), ++ [CMD_RESET] = REG_FIELD(ISP1763_HC_USBCMD, 1, 1), ++ [CMD_RUN] = REG_FIELD(ISP1763_HC_USBCMD, 0, 0), ++ [STS_PCD] = REG_FIELD(ISP1763_HC_USBSTS, 2, 2), ++ [HC_FRINDEX] = REG_FIELD(ISP1763_HC_FRINDEX, 0, 13), ++ [FLAG_CF] = REG_FIELD(ISP1763_HC_CONFIGFLAG, 0, 0), ++ [HC_ISO_PTD_DONEMAP] = REG_FIELD(ISP1763_HC_ISO_PTD_DONEMAP, 0, 15), ++ [HC_ISO_PTD_SKIPMAP] = REG_FIELD(ISP1763_HC_ISO_PTD_SKIPMAP, 0, 15), ++ [HC_ISO_PTD_LASTPTD] = REG_FIELD(ISP1763_HC_ISO_PTD_LASTPTD, 0, 15), ++ [HC_INT_PTD_DONEMAP] = REG_FIELD(ISP1763_HC_INT_PTD_DONEMAP, 0, 15), ++ [HC_INT_PTD_SKIPMAP] = REG_FIELD(ISP1763_HC_INT_PTD_SKIPMAP, 0, 15), ++ [HC_INT_PTD_LASTPTD] = REG_FIELD(ISP1763_HC_INT_PTD_LASTPTD, 0, 15), ++ [HC_ATL_PTD_DONEMAP] = REG_FIELD(ISP1763_HC_ATL_PTD_DONEMAP, 0, 15), ++ [HC_ATL_PTD_SKIPMAP] = REG_FIELD(ISP1763_HC_ATL_PTD_SKIPMAP, 0, 15), ++ [HC_ATL_PTD_LASTPTD] = REG_FIELD(ISP1763_HC_ATL_PTD_LASTPTD, 0, 15), ++ [PORT_OWNER] = REG_FIELD(ISP1763_HC_PORTSC1, 13, 13), ++ [PORT_POWER] = REG_FIELD(ISP1763_HC_PORTSC1, 12, 12), ++ [PORT_LSTATUS] = REG_FIELD(ISP1763_HC_PORTSC1, 10, 11), ++ [PORT_RESET] = REG_FIELD(ISP1763_HC_PORTSC1, 8, 8), ++ [PORT_SUSPEND] = REG_FIELD(ISP1763_HC_PORTSC1, 7, 7), ++ [PORT_RESUME] = REG_FIELD(ISP1763_HC_PORTSC1, 6, 6), ++ [PORT_PE] = REG_FIELD(ISP1763_HC_PORTSC1, 2, 2), ++ [PORT_CSC] = REG_FIELD(ISP1763_HC_PORTSC1, 1, 1), ++ [PORT_CONNECT] = REG_FIELD(ISP1763_HC_PORTSC1, 0, 0), ++ [HW_DATA_BUS_WIDTH] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 4, 4), ++ [HW_DACK_POL_HIGH] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 6, 6), ++ [HW_DREQ_POL_HIGH] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 5, 5), ++ [HW_INTF_LOCK] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 3, 3), ++ [HW_INTR_HIGH_ACT] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 2, 2), ++ [HW_INTR_EDGE_TRIG] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 1, 1), ++ [HW_GLOBAL_INTR_EN] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 0, 0), ++ [SW_RESET_RESET_ATX] = REG_FIELD(ISP1763_HC_RESET, 3, 3), ++ [SW_RESET_RESET_ALL] = REG_FIELD(ISP1763_HC_RESET, 0, 0), ++ [HC_CHIP_ID_HIGH] = REG_FIELD(ISP1763_HC_CHIP_ID, 0, 15), ++ [HC_CHIP_ID_LOW] = REG_FIELD(ISP1763_HC_CHIP_REV, 8, 15), ++ [HC_CHIP_REV] = REG_FIELD(ISP1763_HC_CHIP_REV, 0, 7), ++ [HC_SCRATCH] = REG_FIELD(ISP1763_HC_SCRATCH, 0, 15), ++ [ISO_BUF_FILL] = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 2, 2), ++ [INT_BUF_FILL] = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 1, 1), ++ [ATL_BUF_FILL] = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 0, 0), ++ [MEM_START_ADDR] = REG_FIELD(ISP1763_HC_MEMORY, 0, 15), ++ [HC_DATA] = REG_FIELD(ISP1763_HC_DATA, 0, 15), ++ [HC_INTERRUPT] = REG_FIELD(ISP1763_HC_INTERRUPT, 0, 10), ++ [HC_ATL_IRQ_ENABLE] = REG_FIELD(ISP1763_HC_INTERRUPT_ENABLE, 8, 8), ++ [HC_INT_IRQ_ENABLE] = REG_FIELD(ISP1763_HC_INTERRUPT_ENABLE, 7, 7), ++ [HC_ISO_IRQ_MASK_OR] = REG_FIELD(ISP1763_HC_ISO_IRQ_MASK_OR, 0, 15), ++ [HC_INT_IRQ_MASK_OR] = REG_FIELD(ISP1763_HC_INT_IRQ_MASK_OR, 0, 15), ++ [HC_ATL_IRQ_MASK_OR] = REG_FIELD(ISP1763_HC_ATL_IRQ_MASK_OR, 0, 15), ++ [HC_ISO_IRQ_MASK_AND] = REG_FIELD(ISP1763_HC_ISO_IRQ_MASK_AND, 0, 15), ++ [HC_INT_IRQ_MASK_AND] = REG_FIELD(ISP1763_HC_INT_IRQ_MASK_AND, 0, 15), ++ [HC_ATL_IRQ_MASK_AND] = REG_FIELD(ISP1763_HC_ATL_IRQ_MASK_AND, 0, 15), ++ [HW_HC_2_DIS] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 15, 15), ++ [HW_OTG_DISABLE] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 10, 10), ++ [HW_SW_SEL_HC_DC] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 7, 7), ++ [HW_VBUS_DRV] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 4, 4), ++ [HW_SEL_CP_EXT] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 3, 3), ++ [HW_DM_PULLDOWN] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 2, 2), ++ [HW_DP_PULLDOWN] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 1, 1), ++ [HW_DP_PULLUP] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 0, 0), ++ [HW_HC_2_DIS_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 15, 15), ++ [HW_OTG_DISABLE_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 10, 10), ++ [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 7, 7), ++ [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 4, 4), ++ [HW_SEL_CP_EXT_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 3, 3), ++ [HW_DM_PULLDOWN_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 2, 2), ++ [HW_DP_PULLDOWN_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 1, 1), ++ [HW_DP_PULLUP_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 0, 0), ++}; ++ ++static const struct regmap_range isp1763_hc_volatile_ranges[] = { ++ regmap_reg_range(ISP1763_HC_USBCMD, ISP1763_HC_ATL_PTD_LASTPTD), ++ regmap_reg_range(ISP1763_HC_BUFFER_STATUS, ISP1763_HC_DATA), ++ regmap_reg_range(ISP1763_HC_INTERRUPT, ISP1763_HC_OTG_CTRL_CLEAR), ++}; ++ ++static const struct regmap_access_table isp1763_hc_volatile_table = { ++ .yes_ranges = isp1763_hc_volatile_ranges, ++ .n_yes_ranges = ARRAY_SIZE(isp1763_hc_volatile_ranges), ++}; ++ ++static const struct regmap_config isp1763_hc_regmap_conf = { ++ .name = "isp1763-hc", ++ .reg_bits = 8, ++ .reg_stride = 2, ++ .val_bits = 16, ++ .fast_io = true, ++ .max_register = ISP1763_HC_OTG_CTRL_CLEAR, ++ .volatile_table = &isp1763_hc_volatile_table, + }; + + static const struct regmap_range isp176x_dc_volatile_ranges[] = { + regmap_reg_range(ISP176x_DC_EPMAXPKTSZ, ISP176x_DC_EPTYPE), + regmap_reg_range(ISP176x_DC_BUFLEN, ISP176x_DC_EPINDEX), +- regmap_reg_range(ISP1761_DC_OTG_CTRL_SET, ISP1761_DC_OTG_CTRL_CLEAR), + }; + + static const struct regmap_access_table isp176x_dc_volatile_table = { +@@ -188,13 +351,13 @@ static const struct regmap_access_table isp176x_dc_volatile_table = { + .n_yes_ranges = ARRAY_SIZE(isp176x_dc_volatile_ranges), + }; + +-static struct regmap_config isp1761_dc_regmap_conf = { ++static const struct regmap_config isp1761_dc_regmap_conf = { + .name = "isp1761-dc", + .reg_bits = 16, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +- .max_register = ISP1761_DC_OTG_CTRL_CLEAR, ++ .max_register = ISP176x_DC_TESTMODE, + .volatile_table = &isp176x_dc_volatile_table, + }; + +@@ -236,31 +399,84 @@ static const struct reg_field isp1761_dc_reg_fields[] = { + [DC_ENDPTYP] = REG_FIELD(ISP176x_DC_EPTYPE, 0, 1), + [DC_UFRAMENUM] = REG_FIELD(ISP176x_DC_FRAMENUM, 11, 13), + [DC_FRAMENUM] = REG_FIELD(ISP176x_DC_FRAMENUM, 0, 10), +- [HW_OTG_DISABLE] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 10, 10), +- [HW_SW_SEL_HC_DC] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 7, 7), +- [HW_VBUS_DRV] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 4, 4), +- [HW_SEL_CP_EXT] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 3, 3), +- [HW_DM_PULLDOWN] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 2, 2), +- [HW_DP_PULLDOWN] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 1, 1), +- [HW_DP_PULLUP] = REG_FIELD(ISP1761_DC_OTG_CTRL_SET, 0, 0), +- [HW_OTG_DISABLE_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 10, 10), +- [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 7, 7), +- [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 4, 4), +- [HW_SEL_CP_EXT_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 3, 3), +- [HW_DM_PULLDOWN_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 2, 2), +- [HW_DP_PULLDOWN_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 1, 1), +- [HW_DP_PULLUP_CLEAR] = REG_FIELD(ISP1761_DC_OTG_CTRL_CLEAR, 0, 0), ++ [DC_CHIP_ID_HIGH] = REG_FIELD(ISP176x_DC_CHIPID, 16, 31), ++ [DC_CHIP_ID_LOW] = REG_FIELD(ISP176x_DC_CHIPID, 0, 15), ++ [DC_SCRATCH] = REG_FIELD(ISP176x_DC_SCRATCH, 0, 15), ++}; ++ ++static const struct regmap_range isp1763_dc_volatile_ranges[] = { ++ regmap_reg_range(ISP1763_DC_EPMAXPKTSZ, ISP1763_DC_EPTYPE), ++ regmap_reg_range(ISP1763_DC_BUFLEN, ISP1763_DC_EPINDEX), ++}; ++ ++static const struct regmap_access_table isp1763_dc_volatile_table = { ++ .yes_ranges = isp1763_dc_volatile_ranges, ++ .n_yes_ranges = ARRAY_SIZE(isp1763_dc_volatile_ranges), ++}; ++ ++static const struct reg_field isp1763_dc_reg_fields[] = { ++ [DC_DEVEN] = REG_FIELD(ISP1763_DC_ADDRESS, 7, 7), ++ [DC_DEVADDR] = REG_FIELD(ISP1763_DC_ADDRESS, 0, 6), ++ [DC_VBUSSTAT] = REG_FIELD(ISP1763_DC_MODE, 8, 8), ++ [DC_SFRESET] = REG_FIELD(ISP1763_DC_MODE, 4, 4), ++ [DC_GLINTENA] = REG_FIELD(ISP1763_DC_MODE, 3, 3), ++ [DC_CDBGMOD_ACK] = REG_FIELD(ISP1763_DC_INTCONF, 6, 6), ++ [DC_DDBGMODIN_ACK] = REG_FIELD(ISP1763_DC_INTCONF, 4, 4), ++ [DC_DDBGMODOUT_ACK] = REG_FIELD(ISP1763_DC_INTCONF, 2, 2), ++ [DC_INTPOL] = REG_FIELD(ISP1763_DC_INTCONF, 0, 0), ++ [DC_IEPRXTX_7] = REG_FIELD(ISP1763_DC_INTENABLE, 25, 25), ++ [DC_IEPRXTX_6] = REG_FIELD(ISP1763_DC_INTENABLE, 23, 23), ++ [DC_IEPRXTX_5] = REG_FIELD(ISP1763_DC_INTENABLE, 21, 21), ++ [DC_IEPRXTX_4] = REG_FIELD(ISP1763_DC_INTENABLE, 19, 19), ++ [DC_IEPRXTX_3] = REG_FIELD(ISP1763_DC_INTENABLE, 17, 17), ++ [DC_IEPRXTX_2] = REG_FIELD(ISP1763_DC_INTENABLE, 15, 15), ++ [DC_IEPRXTX_1] = REG_FIELD(ISP1763_DC_INTENABLE, 13, 13), ++ [DC_IEPRXTX_0] = REG_FIELD(ISP1763_DC_INTENABLE, 11, 11), ++ [DC_IEP0SETUP] = REG_FIELD(ISP1763_DC_INTENABLE, 8, 8), ++ [DC_IEVBUS] = REG_FIELD(ISP1763_DC_INTENABLE, 7, 7), ++ [DC_IEHS_STA] = REG_FIELD(ISP1763_DC_INTENABLE, 5, 5), ++ [DC_IERESM] = REG_FIELD(ISP1763_DC_INTENABLE, 4, 4), ++ [DC_IESUSP] = REG_FIELD(ISP1763_DC_INTENABLE, 3, 3), ++ [DC_IEBRST] = REG_FIELD(ISP1763_DC_INTENABLE, 0, 0), ++ [DC_EP0SETUP] = REG_FIELD(ISP1763_DC_EPINDEX, 5, 5), ++ [DC_ENDPIDX] = REG_FIELD(ISP1763_DC_EPINDEX, 1, 4), ++ [DC_EPDIR] = REG_FIELD(ISP1763_DC_EPINDEX, 0, 0), ++ [DC_CLBUF] = REG_FIELD(ISP1763_DC_CTRLFUNC, 4, 4), ++ [DC_VENDP] = REG_FIELD(ISP1763_DC_CTRLFUNC, 3, 3), ++ [DC_DSEN] = REG_FIELD(ISP1763_DC_CTRLFUNC, 2, 2), ++ [DC_STATUS] = REG_FIELD(ISP1763_DC_CTRLFUNC, 1, 1), ++ [DC_STALL] = REG_FIELD(ISP1763_DC_CTRLFUNC, 0, 0), ++ [DC_BUFLEN] = REG_FIELD(ISP1763_DC_BUFLEN, 0, 15), ++ [DC_FFOSZ] = REG_FIELD(ISP1763_DC_EPMAXPKTSZ, 0, 10), ++ [DC_EPENABLE] = REG_FIELD(ISP1763_DC_EPTYPE, 3, 3), ++ [DC_ENDPTYP] = REG_FIELD(ISP1763_DC_EPTYPE, 0, 1), ++ [DC_UFRAMENUM] = REG_FIELD(ISP1763_DC_FRAMENUM, 11, 13), ++ [DC_FRAMENUM] = REG_FIELD(ISP1763_DC_FRAMENUM, 0, 10), ++ [DC_CHIP_ID_HIGH] = REG_FIELD(ISP1763_DC_CHIPID_HIGH, 0, 15), ++ [DC_CHIP_ID_LOW] = REG_FIELD(ISP1763_DC_CHIPID_LOW, 0, 15), ++ [DC_SCRATCH] = REG_FIELD(ISP1763_DC_SCRATCH, 0, 15), ++}; ++ ++static const struct regmap_config isp1763_dc_regmap_conf = { ++ .name = "isp1763-dc", ++ .reg_bits = 8, ++ .reg_stride = 2, ++ .val_bits = 16, ++ .fast_io = true, ++ .max_register = ISP1763_DC_TESTMODE, ++ .volatile_table = &isp1763_dc_volatile_table, + }; + + int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + struct device *dev, unsigned int devflags) + { ++ bool udc_disabled = !(devflags & ISP1760_FLAG_ISP1761); ++ const struct regmap_config *hc_regmap; ++ const struct reg_field *hc_reg_fields; + struct isp1760_device *isp; + struct isp1760_hcd *hcd; + struct isp1760_udc *udc; +- bool udc_disabled = !(devflags & ISP1760_FLAG_ISP1761); + struct regmap_field *f; +- void __iomem *base; + int ret; + int i; + +@@ -281,9 +497,19 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + hcd = &isp->hcd; + udc = &isp->udc; + +- if (devflags & ISP1760_FLAG_BUS_WIDTH_16) { +- isp1760_hc_regmap_conf.val_bits = 16; +- isp1761_dc_regmap_conf.val_bits = 16; ++ hcd->is_isp1763 = !!(devflags & ISP1760_FLAG_ISP1763); ++ ++ if (!hcd->is_isp1763 && (devflags & ISP1760_FLAG_BUS_WIDTH_8)) { ++ dev_err(dev, "isp1760/61 do not support data width 8\n"); ++ return -EINVAL; ++ } ++ ++ if (hcd->is_isp1763) { ++ hc_regmap = &isp1763_hc_regmap_conf; ++ hc_reg_fields = &isp1763_hc_reg_fields[0]; ++ } else { ++ hc_regmap = &isp1760_hc_regmap_conf; ++ hc_reg_fields = &isp1760_hc_reg_fields[0]; + } + + isp->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); +@@ -294,20 +520,20 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + if (IS_ERR(hcd->base)) + return PTR_ERR(hcd->base); + +- hcd->regs = devm_regmap_init_mmio(dev, base, &isp1760_hc_regmap_conf); ++ hcd->regs = devm_regmap_init_mmio(dev, hcd->base, hc_regmap); + if (IS_ERR(hcd->regs)) + return PTR_ERR(hcd->regs); + + for (i = 0; i < HC_FIELD_MAX; i++) { +- f = devm_regmap_field_alloc(dev, hcd->regs, +- isp1760_hc_reg_fields[i]); ++ f = devm_regmap_field_alloc(dev, hcd->regs, hc_reg_fields[i]); + if (IS_ERR(f)) + return PTR_ERR(f); + + hcd->fields[i] = f; + } + +- udc->regs = devm_regmap_init_mmio(dev, base, &isp1761_dc_regmap_conf); ++ udc->regs = devm_regmap_init_mmio(dev, hcd->base, ++ &isp1761_dc_regmap_conf); + if (IS_ERR(udc->regs)) + return PTR_ERR(udc->regs); + +@@ -320,9 +546,14 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + udc->fields[i] = f; + } + +- hcd->memory_layout = &isp176x_memory_conf; ++ if (hcd->is_isp1763) ++ hcd->memory_layout = &isp1763_memory_conf; ++ else ++ hcd->memory_layout = &isp176x_memory_conf; + +- isp1760_init_core(isp); ++ ret = isp1760_init_core(isp); ++ if (ret < 0) ++ return ret; + + if (IS_ENABLED(CONFIG_USB_ISP1760_HCD) && !usb_disabled()) { + ret = isp1760_hcd_register(hcd, mem, irq, +diff --git a/drivers/usb/isp1760/isp1760-core.h b/drivers/usb/isp1760/isp1760-core.h +index 7a6755d68d41..91e0ee3992a7 100644 +--- a/drivers/usb/isp1760/isp1760-core.h ++++ b/drivers/usb/isp1760/isp1760-core.h +@@ -2,12 +2,14 @@ + /* + * Driver for the NXP ISP1760 chip + * ++ * Copyright 2021 Linaro, Rui Miguel Silva + * Copyright 2014 Laurent Pinchart + * Copyright 2007 Sebastian Siewior + * + * Contacts: + * Sebastian Siewior + * Laurent Pinchart ++ * Rui Miguel Silva + */ + + #ifndef _ISP1760_CORE_H_ +@@ -35,6 +37,8 @@ struct gpio_desc; + #define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */ + #define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */ + #define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */ ++#define ISP1760_FLAG_ISP1763 0x00000200 /* Chip is ISP1763 */ ++#define ISP1760_FLAG_BUS_WIDTH_8 0x00000400 /* 8-bit data bus width */ + + struct isp1760_device { + struct device *dev; +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index a65f5f917ebe..016a54ea76f4 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -11,6 +11,8 @@ + * + * (c) 2011 Arvid Brodin + * ++ * Copyright 2021 Linaro, Rui Miguel Silva ++ * + */ + #include + #include +@@ -44,6 +46,9 @@ static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) + return *(struct isp1760_hcd **)hcd->hcd_priv; + } + ++#define dw_to_le32(x) (cpu_to_le32((__force u32)x)) ++#define le32_to_dw(x) ((__force __dw)(le32_to_cpu(x))) ++ + /* urb state*/ + #define DELETE_URB (0x0008) + #define NO_TRANSFER_ACTIVE (0xffffffff) +@@ -60,6 +65,18 @@ struct ptd { + __dw dw6; + __dw dw7; + }; ++ ++struct ptd_le32 { ++ __le32 dw0; ++ __le32 dw1; ++ __le32 dw2; ++ __le32 dw3; ++ __le32 dw4; ++ __le32 dw5; ++ __le32 dw6; ++ __le32 dw7; ++}; ++ + #define PTD_OFFSET 0x0400 + #define ISO_PTD_OFFSET 0x0400 + #define INT_PTD_OFFSET 0x0800 +@@ -96,7 +113,7 @@ struct ptd { + #define TO_DW2_RL(x) TO_DW(((x) << 25)) + #define FROM_DW2_RL(x) ((TO_U32(x) >> 25) & 0xf) + /* DW3 */ +-#define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x7fff) ++#define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x3fff) + #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x07ff) + #define TO_DW3_NAKCOUNT(x) TO_DW(((x) << 19)) + #define FROM_DW3_NAKCOUNT(x) ((TO_U32(x) >> 19) & 0xf) +@@ -123,7 +140,7 @@ struct ptd { + /* Errata 1 */ + #define RL_COUNTER (0) + #define NAK_COUNTER (0) +-#define ERR_COUNTER (2) ++#define ERR_COUNTER (3) + + struct isp1760_qtd { + u8 packet_type; +@@ -165,6 +182,18 @@ struct urb_listitem { + struct urb *urb; + }; + ++static const u32 isp1763_hc_portsc1_fields[] = { ++ [PORT_OWNER] = BIT(13), ++ [PORT_POWER] = BIT(12), ++ [PORT_LSTATUS] = BIT(10), ++ [PORT_RESET] = BIT(8), ++ [PORT_SUSPEND] = BIT(7), ++ [PORT_RESUME] = BIT(6), ++ [PORT_PE] = BIT(2), ++ [PORT_CSC] = BIT(1), ++ [PORT_CONNECT] = BIT(0), ++}; ++ + /* + * Access functions for isp176x registers regmap fields + */ +@@ -175,10 +204,30 @@ static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field) + return isp1760_field_read(priv->fields, field); + } + ++/* ++ * We need, in isp1763, to write directly the values to the portsc1 ++ * register so it will make the other values to trigger. ++ */ ++static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field, ++ u32 val) ++{ ++ u32 bit = isp1763_hc_portsc1_fields[field]; ++ u32 port_status = readl(priv->base + ISP1763_HC_PORTSC1); ++ ++ if (val) ++ writel(port_status | bit, priv->base + ISP1763_HC_PORTSC1); ++ else ++ writel(port_status & ~bit, priv->base + ISP1763_HC_PORTSC1); ++} ++ + static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); + ++ if (unlikely(priv->is_isp1763 && ++ (field >= PORT_OWNER && field <= PORT_CONNECT))) ++ return isp1760_hcd_portsc1_set_clear(priv, field, val); ++ + isp1760_field_write(priv->fields, field, val); + } + +@@ -192,28 +241,40 @@ static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field) + isp1760_hcd_write(hcd, field, 0); + } + +-static int isp1760_hcd_set_poll_timeout(struct usb_hcd *hcd, u32 field, +- u32 timeout_us) ++static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field, ++ u32 timeout_us) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ u32 val; ++ ++ isp1760_hcd_set(hcd, field); ++ ++ return regmap_field_read_poll_timeout(priv->fields[field], val, ++ val, 10, timeout_us); ++} ++ ++static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field, ++ u32 timeout_us) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); +- unsigned int val; ++ u32 val; + + isp1760_hcd_set(hcd, field); + +- return regmap_field_read_poll_timeout(priv->fields[field], val, 1, 1, +- timeout_us); ++ return regmap_field_read_poll_timeout(priv->fields[field], val, ++ !val, 10, timeout_us); + } + +-static int isp1760_hcd_clear_poll_timeout(struct usb_hcd *hcd, u32 field, +- u32 timeout_us) ++static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field, ++ u32 timeout_us) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); +- unsigned int val; ++ u32 val; + + isp1760_hcd_clear(hcd, field); + +- return regmap_field_read_poll_timeout(priv->fields[field], val, 0, 1, +- timeout_us); ++ return regmap_field_read_poll_timeout(priv->fields[field], val, ++ !val, 10, timeout_us); + } + + static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field) +@@ -221,12 +282,32 @@ static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field) + return !!isp1760_hcd_read(hcd, field); + } + ++static bool isp1760_hcd_ppc_is_set(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (priv->is_isp1763) ++ return true; ++ ++ return isp1760_hcd_is_set(hcd, HCS_PPC); ++} ++ ++static u32 isp1760_hcd_n_ports(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (priv->is_isp1763) ++ return 1; ++ ++ return isp1760_hcd_read(hcd, HCS_N_PORTS); ++} ++ + /* + * Access functions for isp176x memory (offset >= 0x0400). + * + * bank_reads8() reads memory locations prefetched by an earlier write to + * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- +- * bank optimizations, you should use the more generic mem_reads8() below. ++ * bank optimizations, you should use the more generic mem_read() below. + * + * For access to ptd memory, use the specialized ptd_read() and ptd_write() + * below. +@@ -281,19 +362,59 @@ static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, + } + } + +-static void mem_reads8(struct usb_hcd *hcd, void __iomem *src_base, +- u32 src_offset, void *dst, u32 bytes) ++static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst, ++ u32 bytes) + { ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ + isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); + isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); ++ ndelay(100); + +- ndelay(90); ++ bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes); ++} + +- bank_reads8(src_base, src_offset, ISP_BANK_0, dst, bytes); ++/* ++ * ISP1763 does not have the banks direct host controller memory access, ++ * needs to use the HC_DATA register. Add data read/write according to this, ++ * and also adjust 16bit access. ++ */ ++static void isp1763_mem_read(struct usb_hcd *hcd, u16 srcaddr, ++ u16 *dstptr, u32 bytes) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ /* Write the starting device address to the hcd memory register */ ++ isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, srcaddr); ++ ndelay(100); /* Delay between consecutive access */ ++ ++ /* As long there are at least 16-bit to read ... */ ++ while (bytes >= 2) { ++ *dstptr = __raw_readw(priv->base + ISP1763_HC_DATA); ++ bytes -= 2; ++ dstptr++; ++ } ++ ++ /* If there are no more bytes to read, return */ ++ if (bytes <= 0) ++ return; ++ ++ *((u8 *)dstptr) = (u8)(readw(priv->base + ISP1763_HC_DATA) & 0xFF); ++} ++ ++static void mem_read(struct usb_hcd *hcd, u32 src_offset, __u32 *dst, ++ u32 bytes) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (!priv->is_isp1763) ++ return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes); ++ ++ isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes); + } + +-static void mem_writes8(void __iomem *dst_base, u32 dst_offset, +- __u32 const *src, u32 bytes) ++static void isp1760_mem_write(void __iomem *dst_base, u32 dst_offset, ++ __u32 const *src, u32 bytes) + { + __u32 __iomem *dst; + +@@ -327,33 +448,136 @@ static void mem_writes8(void __iomem *dst_base, u32 dst_offset, + __raw_writel(*src, dst); + } + ++static void isp1763_mem_write(struct usb_hcd *hcd, u16 dstaddr, u16 *src, ++ u32 bytes) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ /* Write the starting device address to the hcd memory register */ ++ isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, dstaddr); ++ ndelay(100); /* Delay between consecutive access */ ++ ++ while (bytes >= 2) { ++ /* Get and write the data; then adjust the data ptr and len */ ++ __raw_writew(*src, priv->base + ISP1763_HC_DATA); ++ bytes -= 2; ++ src++; ++ } ++ ++ /* If there are no more bytes to process, return */ ++ if (bytes <= 0) ++ return; ++ ++ /* ++ * The only way to get here is if there is a single byte left, ++ * get it and write it to the data reg; ++ */ ++ writew(*((u8 *)src), priv->base + ISP1763_HC_DATA); ++} ++ ++static void mem_write(struct usb_hcd *hcd, u32 dst_offset, __u32 *src, ++ u32 bytes) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (!priv->is_isp1763) ++ return isp1760_mem_write(priv->base, dst_offset, src, bytes); ++ ++ isp1763_mem_write(hcd, dst_offset, (u16 *)src, bytes); ++} ++ + /* + * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, + * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. + */ +-static void ptd_read(struct usb_hcd *hcd, void __iomem *base, +- u32 ptd_offset, u32 slot, struct ptd *ptd) ++static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, ++ struct ptd *ptd) + { ++ u16 src_offset = ptd_offset + slot * sizeof(*ptd); ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ + isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); +- isp1760_hcd_write(hcd, MEM_START_ADDR, +- ptd_offset + slot * sizeof(*ptd)); ++ isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); + ndelay(90); +- bank_reads8(base, ptd_offset + slot * sizeof(*ptd), ISP_BANK_0, +- (void *)ptd, sizeof(*ptd)); ++ ++ bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd, ++ sizeof(*ptd)); ++} ++ ++static void isp1763_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, ++ struct ptd *ptd) ++{ ++ u16 src_offset = ptd_offset + slot * sizeof(*ptd); ++ struct ptd_le32 le32_ptd; ++ ++ isp1763_mem_read(hcd, src_offset, (u16 *)&le32_ptd, sizeof(le32_ptd)); ++ /* Normalize the data obtained */ ++ ptd->dw0 = le32_to_dw(le32_ptd.dw0); ++ ptd->dw1 = le32_to_dw(le32_ptd.dw1); ++ ptd->dw2 = le32_to_dw(le32_ptd.dw2); ++ ptd->dw3 = le32_to_dw(le32_ptd.dw3); ++ ptd->dw4 = le32_to_dw(le32_ptd.dw4); ++ ptd->dw5 = le32_to_dw(le32_ptd.dw5); ++ ptd->dw6 = le32_to_dw(le32_ptd.dw6); ++ ptd->dw7 = le32_to_dw(le32_ptd.dw7); ++} ++ ++static void ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, ++ struct ptd *ptd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (!priv->is_isp1763) ++ return isp1760_ptd_read(hcd, ptd_offset, slot, ptd); ++ ++ isp1763_ptd_read(hcd, ptd_offset, slot, ptd); ++} ++ ++static void isp1763_ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, ++ struct ptd *cpu_ptd) ++{ ++ u16 dst_offset = ptd_offset + slot * sizeof(*cpu_ptd); ++ struct ptd_le32 ptd; ++ ++ ptd.dw0 = dw_to_le32(cpu_ptd->dw0); ++ ptd.dw1 = dw_to_le32(cpu_ptd->dw1); ++ ptd.dw2 = dw_to_le32(cpu_ptd->dw2); ++ ptd.dw3 = dw_to_le32(cpu_ptd->dw3); ++ ptd.dw4 = dw_to_le32(cpu_ptd->dw4); ++ ptd.dw5 = dw_to_le32(cpu_ptd->dw5); ++ ptd.dw6 = dw_to_le32(cpu_ptd->dw6); ++ ptd.dw7 = dw_to_le32(cpu_ptd->dw7); ++ ++ isp1763_mem_write(hcd, dst_offset, (u16 *)&ptd.dw0, ++ 8 * sizeof(ptd.dw0)); + } + +-static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, +- struct ptd *ptd) ++static void isp1760_ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, ++ struct ptd *ptd) + { +- mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), +- (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1)); +- /* Make sure dw0 gets written last (after other dw's and after payload) +- since it contains the enable bit */ ++ u32 dst_offset = ptd_offset + slot * sizeof(*ptd); ++ ++ /* ++ * Make sure dw0 gets written last (after other dw's and after payload) ++ * since it contains the enable bit ++ */ ++ isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0), ++ (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1)); + wmb(); +- mem_writes8(base, ptd_offset + slot * sizeof(*ptd), +- (__force u32 *)&ptd->dw0, sizeof(ptd->dw0)); ++ isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0, ++ sizeof(ptd->dw0)); + } + ++static void ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, ++ struct ptd *ptd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (!priv->is_isp1763) ++ return isp1760_ptd_write(priv->base, ptd_offset, slot, ptd); ++ ++ isp1763_ptd_write(hcd, ptd_offset, slot, ptd); ++} + + /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ + static void init_memory(struct isp1760_hcd *priv) +@@ -430,7 +654,7 @@ static int ehci_reset(struct usb_hcd *hcd) + hcd->state = HC_STATE_HALT; + priv->next_statechange = jiffies; + +- return isp1760_hcd_set_poll_timeout(hcd, CMD_RESET, 250 * 1000); ++ return isp1760_hcd_set_and_wait_swap(hcd, CMD_RESET, 250 * 1000); + } + + static struct isp1760_qh *qh_alloc(gfp_t flags) +@@ -461,7 +685,6 @@ static int priv_init(struct usb_hcd *hcd) + struct isp1760_hcd *priv = hcd_to_priv(hcd); + u32 isoc_cache; + u32 isoc_thres; +- + int i; + + spin_lock_init(&priv->lock); +@@ -475,6 +698,11 @@ static int priv_init(struct usb_hcd *hcd) + */ + priv->periodic_size = DEFAULT_I_TDPS; + ++ if (priv->is_isp1763) { ++ priv->i_thresh = 2; ++ return 0; ++ } ++ + /* controllers may cache some of the periodic schedule ... */ + isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE); + isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES); +@@ -491,16 +719,24 @@ static int priv_init(struct usb_hcd *hcd) + static int isp1760_hc_setup(struct usb_hcd *hcd) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ u32 atx_reset; + int result; + u32 scratch; ++ u32 pattern; + +- isp1760_reg_write(priv->regs, ISP176x_HC_SCRATCH, 0xdeadbabe); ++ if (priv->is_isp1763) ++ pattern = 0xcafe; ++ else ++ pattern = 0xdeadcafe; ++ ++ isp1760_hcd_write(hcd, HC_SCRATCH, pattern); + + /* Change bus pattern */ +- scratch = isp1760_reg_read(priv->regs, ISP176x_HC_CHIP_ID); +- scratch = isp1760_reg_read(priv->regs, ISP176x_HC_SCRATCH); +- if (scratch != 0xdeadbabe) { +- dev_err(hcd->self.controller, "Scratch test failed.\n"); ++ scratch = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); ++ dev_err(hcd->self.controller, "Scratch test 0x%08x\n", scratch); ++ scratch = isp1760_hcd_read(hcd, HC_SCRATCH); ++ if (scratch != pattern) { ++ dev_err(hcd->self.controller, "Scratch test failed. 0x%08x\n", scratch); + return -ENODEV; + } + +@@ -512,13 +748,13 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) + * the host controller through the EHCI USB Command register. The device + * has been reset in core code anyway, so this shouldn't matter. + */ +- isp1760_reg_write(priv->regs, ISP176x_HC_BUFFER_STATUS, 0); +- isp1760_reg_write(priv->regs, ISP176x_HC_ATL_PTD_SKIPMAP, +- NO_TRANSFER_ACTIVE); +- isp1760_reg_write(priv->regs, ISP176x_HC_INT_PTD_SKIPMAP, +- NO_TRANSFER_ACTIVE); +- isp1760_reg_write(priv->regs, ISP176x_HC_ISO_PTD_SKIPMAP, +- NO_TRANSFER_ACTIVE); ++ isp1760_hcd_clear(hcd, ISO_BUF_FILL); ++ isp1760_hcd_clear(hcd, INT_BUF_FILL); ++ isp1760_hcd_clear(hcd, ATL_BUF_FILL); ++ ++ isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); + + result = ehci_reset(hcd); + if (result) +@@ -527,11 +763,26 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) + /* Step 11 passed */ + + /* ATL reset */ +- isp1760_hcd_set(hcd, ALL_ATX_RESET); ++ if (priv->is_isp1763) ++ atx_reset = SW_RESET_RESET_ATX; ++ else ++ atx_reset = ALL_ATX_RESET; ++ ++ isp1760_hcd_set(hcd, atx_reset); + mdelay(10); +- isp1760_hcd_clear(hcd, ALL_ATX_RESET); ++ isp1760_hcd_clear(hcd, atx_reset); + +- isp1760_hcd_set(hcd, HC_INT_ENABLE); ++ if (priv->is_isp1763) { ++ isp1760_hcd_set(hcd, HW_OTG_DISABLE); ++ isp1760_hcd_set(hcd, HW_SW_SEL_HC_DC_CLEAR); ++ isp1760_hcd_set(hcd, HW_HC_2_DIS_CLEAR); ++ mdelay(10); ++ ++ isp1760_hcd_set(hcd, HW_INTF_LOCK); ++ } ++ ++ isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); ++ isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); + + return priv_init(hcd); + } +@@ -751,45 +1002,45 @@ static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, + struct ptd *ptd) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; + int skip_map; + +- WARN_ON((slot < 0) || (slot > 31)); ++ WARN_ON((slot < 0) || (slot > mem->slot_num - 1)); + WARN_ON(qtd->length && !qtd->payload_addr); + WARN_ON(slots[slot].qtd); + WARN_ON(slots[slot].qh); + WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); + ++ if (priv->is_isp1763) ++ ndelay(100); ++ + /* Make sure done map has not triggered from some unlinked transfer */ + if (ptd_offset == ATL_PTD_OFFSET) { +- priv->atl_done_map |= isp1760_reg_read(priv->regs, +- ISP176x_HC_ATL_PTD_DONEMAP); ++ skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); ++ isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, ++ skip_map | (1 << slot)); ++ priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); + priv->atl_done_map &= ~(1 << slot); + } else { +- priv->int_done_map |= isp1760_reg_read(priv->regs, +- ISP176x_HC_INT_PTD_DONEMAP); ++ skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); ++ isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, ++ skip_map | (1 << slot)); ++ priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); + priv->int_done_map &= ~(1 << slot); + } + ++ skip_map &= ~(1 << slot); + qh->slot = slot; + qtd->status = QTD_XFER_STARTED; + slots[slot].timestamp = jiffies; + slots[slot].qtd = qtd; + slots[slot].qh = qh; +- ptd_write(priv->base, ptd_offset, slot, ptd); ++ ptd_write(hcd, ptd_offset, slot, ptd); + +- if (ptd_offset == ATL_PTD_OFFSET) { +- skip_map = isp1760_reg_read(priv->regs, +- ISP176x_HC_ATL_PTD_SKIPMAP); +- skip_map &= ~(1 << qh->slot); +- isp1760_reg_write(priv->regs, ISP176x_HC_ATL_PTD_SKIPMAP, +- skip_map); +- } else { +- skip_map = isp1760_reg_read(priv->regs, +- ISP176x_HC_INT_PTD_SKIPMAP); +- skip_map &= ~(1 << qh->slot); +- isp1760_reg_write(priv->regs, ISP176x_HC_INT_PTD_SKIPMAP, +- skip_map); +- } ++ if (ptd_offset == ATL_PTD_OFFSET) ++ isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); ++ else ++ isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); + } + + static int is_short_bulk(struct isp1760_qtd *qtd) +@@ -801,7 +1052,6 @@ static int is_short_bulk(struct isp1760_qtd *qtd) + static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, + struct list_head *urb_list) + { +- struct isp1760_hcd *priv = hcd_to_priv(hcd); + struct isp1760_qtd *qtd, *qtd_next; + struct urb_listitem *urb_listitem; + int last_qtd; +@@ -819,10 +1069,9 @@ static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, + if (qtd->actual_length) { + switch (qtd->packet_type) { + case IN_PID: +- mem_reads8(hcd, priv->base, +- qtd->payload_addr, +- qtd->data_buffer, +- qtd->actual_length); ++ mem_read(hcd, qtd->payload_addr, ++ qtd->data_buffer, ++ qtd->actual_length); + fallthrough; + case OUT_PID: + qtd->urb->actual_length += +@@ -866,6 +1115,8 @@ static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, + static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; ++ int slot_num = mem->slot_num; + int ptd_offset; + struct isp1760_slotinfo *slots; + int curr_slot, free_slot; +@@ -892,7 +1143,7 @@ static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) + } + + free_slot = -1; +- for (curr_slot = 0; curr_slot < 32; curr_slot++) { ++ for (curr_slot = 0; curr_slot < slot_num; curr_slot++) { + if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) + free_slot = curr_slot; + if (slots[curr_slot].qh == qh) +@@ -907,11 +1158,10 @@ static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) + if ((qtd->length) && (!qtd->payload_addr)) + break; + +- if ((qtd->length) && +- ((qtd->packet_type == SETUP_PID) || +- (qtd->packet_type == OUT_PID))) { +- mem_writes8(priv->base, qtd->payload_addr, +- qtd->data_buffer, qtd->length); ++ if (qtd->length && (qtd->packet_type == SETUP_PID || ++ qtd->packet_type == OUT_PID)) { ++ mem_write(hcd, qtd->payload_addr, ++ qtd->data_buffer, qtd->length); + } + + qtd->status = QTD_PAYLOAD_ALLOC; +@@ -924,7 +1174,7 @@ static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) + "available for transfer\n", __func__); + */ + /* Start xfer for this endpoint if not already done */ +- if ((curr_slot > 31) && (free_slot > -1)) { ++ if ((curr_slot > slot_num - 1) && (free_slot > -1)) { + if (usb_pipeint(qtd->urb->pipe)) + create_ptd_int(qh, qtd, &ptd); + else +@@ -1111,9 +1361,9 @@ static void handle_done_ptds(struct usb_hcd *hcd) + int modified; + int skip_map; + +- skip_map = isp1760_reg_read(priv->regs, ISP176x_HC_INT_PTD_SKIPMAP); ++ skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); + priv->int_done_map &= ~skip_map; +- skip_map = isp1760_reg_read(priv->regs, ISP176x_HC_ATL_PTD_SKIPMAP); ++ skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); + priv->atl_done_map &= ~skip_map; + + modified = priv->int_done_map || priv->atl_done_map; +@@ -1131,7 +1381,7 @@ static void handle_done_ptds(struct usb_hcd *hcd) + continue; + } + ptd_offset = INT_PTD_OFFSET; +- ptd_read(hcd, priv->base, INT_PTD_OFFSET, slot, &ptd); ++ ptd_read(hcd, INT_PTD_OFFSET, slot, &ptd); + state = check_int_transfer(hcd, &ptd, + slots[slot].qtd->urb); + } else { +@@ -1146,7 +1396,7 @@ static void handle_done_ptds(struct usb_hcd *hcd) + continue; + } + ptd_offset = ATL_PTD_OFFSET; +- ptd_read(hcd, priv->base, ATL_PTD_OFFSET, slot, &ptd); ++ ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd); + state = check_atl_transfer(hcd, &ptd, + slots[slot].qtd->urb); + } +@@ -1239,27 +1489,30 @@ static void handle_done_ptds(struct usb_hcd *hcd) + static irqreturn_t isp1760_irq(struct usb_hcd *hcd) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); +- u32 imask; + irqreturn_t irqret = IRQ_NONE; ++ u32 int_reg; ++ u32 imask; + + spin_lock(&priv->lock); + + if (!(hcd->state & HC_STATE_RUNNING)) + goto leave; + +- imask = isp1760_reg_read(priv->regs, ISP176x_HC_INTERRUPT); ++ imask = isp1760_hcd_read(hcd, HC_INTERRUPT); + if (unlikely(!imask)) + goto leave; +- isp1760_reg_write(priv->regs, ISP176x_HC_INTERRUPT, imask); /* Clear */ + +- priv->int_done_map |= isp1760_reg_read(priv->regs, +- ISP176x_HC_INT_PTD_DONEMAP); +- priv->atl_done_map |= isp1760_reg_read(priv->regs, +- ISP176x_HC_ATL_PTD_DONEMAP); ++ int_reg = priv->is_isp1763 ? ISP1763_HC_INTERRUPT : ++ ISP176x_HC_INTERRUPT; ++ isp1760_reg_write(priv->regs, int_reg, imask); ++ ++ priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); ++ priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); + + handle_done_ptds(hcd); + + irqret = IRQ_HANDLED; ++ + leave: + spin_unlock(&priv->lock); + +@@ -1300,17 +1553,18 @@ static void errata2_function(struct timer_list *unused) + { + struct usb_hcd *hcd = errata2_timer_hcd; + struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; + int slot; + struct ptd ptd; + unsigned long spinflags; + + spin_lock_irqsave(&priv->lock, spinflags); + +- for (slot = 0; slot < 32; slot++) ++ for (slot = 0; slot < mem->slot_num; slot++) + if (priv->atl_slots[slot].qh && time_after(jiffies, + priv->atl_slots[slot].timestamp + + msecs_to_jiffies(SLOT_TIMEOUT))) { +- ptd_read(hcd, priv->base, ATL_PTD_OFFSET, slot, &ptd); ++ ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd); + if (!FROM_DW0_VALID(ptd.dw0) && + !FROM_DW3_ACTIVE(ptd.dw3)) + priv->atl_done_map |= 1 << slot; +@@ -1325,23 +1579,113 @@ static void errata2_function(struct timer_list *unused) + add_timer(&errata2_timer); + } + ++static int isp1763_run(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ int retval; ++ u32 chipid_h; ++ u32 chipid_l; ++ u32 chip_rev; ++ u32 ptd_atl_int; ++ u32 ptd_iso; ++ ++ hcd->uses_new_polling = 1; ++ hcd->state = HC_STATE_RUNNING; ++ ++ chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); ++ chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); ++ chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); ++ dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n", ++ chipid_h, chipid_l, chip_rev); ++ ++ isp1760_hcd_clear(hcd, ISO_BUF_FILL); ++ isp1760_hcd_clear(hcd, INT_BUF_FILL); ++ isp1760_hcd_clear(hcd, ATL_BUF_FILL); ++ ++ isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); ++ ndelay(100); ++ isp1760_hcd_clear(hcd, HC_ATL_PTD_DONEMAP); ++ isp1760_hcd_clear(hcd, HC_INT_PTD_DONEMAP); ++ isp1760_hcd_clear(hcd, HC_ISO_PTD_DONEMAP); ++ ++ isp1760_hcd_set(hcd, HW_OTG_DISABLE); ++ isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(7)); ++ isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(15)); ++ mdelay(10); ++ ++ isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); ++ isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); ++ ++ isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); ++ ++ isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); ++ isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); ++ isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); ++ ++ isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); ++ isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); ++ isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); ++ ++ ptd_atl_int = 0x8000; ++ ptd_iso = 0x0001; ++ ++ isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); ++ isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); ++ isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); ++ ++ isp1760_hcd_set(hcd, ATL_BUF_FILL); ++ isp1760_hcd_set(hcd, INT_BUF_FILL); ++ ++ isp1760_hcd_clear(hcd, CMD_LRESET); ++ isp1760_hcd_clear(hcd, CMD_RESET); ++ ++ retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); ++ if (retval) ++ return retval; ++ ++ down_write(&ehci_cf_port_reset_rwsem); ++ retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); ++ up_write(&ehci_cf_port_reset_rwsem); ++ retval = 0; ++ if (retval) ++ return retval; ++ ++ return 0; ++} ++ + static int isp1760_run(struct usb_hcd *hcd) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); + int retval; +- u32 chipid; ++ u32 chipid_h; ++ u32 chipid_l; ++ u32 chip_rev; ++ u32 ptd_atl_int; ++ u32 ptd_iso; ++ ++ /* ++ * ISP1763 have some differences in the setup and order to enable ++ * the ports, disable otg, setup buffers, and ATL, INT, ISO status. ++ * So, just handle it a separate sequence. ++ */ ++ if (priv->is_isp1763) ++ return isp1763_run(hcd); + + hcd->uses_new_polling = 1; + + hcd->state = HC_STATE_RUNNING; + + /* Set PTD interrupt AND & OR maps */ +- isp1760_reg_write(priv->regs, ISP176x_HC_ATL_IRQ_MASK_AND, 0); +- isp1760_reg_write(priv->regs, ISP176x_HC_ATL_IRQ_MASK_OR, 0xffffffff); +- isp1760_reg_write(priv->regs, ISP176x_HC_INT_IRQ_MASK_AND, 0); +- isp1760_reg_write(priv->regs, ISP176x_HC_INT_IRQ_MASK_OR, 0xffffffff); +- isp1760_reg_write(priv->regs, ISP176x_HC_ISO_IRQ_MASK_AND, 0); +- isp1760_reg_write(priv->regs, ISP176x_HC_ISO_IRQ_MASK_OR, 0xffffffff); ++ isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); ++ isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); ++ isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); ++ ++ isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); ++ isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); ++ isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); ++ + /* step 23 passed */ + + isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); +@@ -1349,7 +1693,7 @@ static int isp1760_run(struct usb_hcd *hcd) + isp1760_hcd_clear(hcd, CMD_LRESET); + isp1760_hcd_clear(hcd, CMD_RESET); + +- retval = isp1760_hcd_set_poll_timeout(hcd, CMD_RUN, 250 * 1000); ++ retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); + if (retval) + return retval; + +@@ -1360,7 +1704,7 @@ static int isp1760_run(struct usb_hcd *hcd) + */ + down_write(&ehci_cf_port_reset_rwsem); + +- retval = isp1760_hcd_set_poll_timeout(hcd, FLAG_CF, 250 * 1000); ++ retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); + up_write(&ehci_cf_port_reset_rwsem); + if (retval) + return retval; +@@ -1370,19 +1714,25 @@ static int isp1760_run(struct usb_hcd *hcd) + errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD); + add_timer(&errata2_timer); + +- chipid = isp1760_reg_read(priv->regs, ISP176x_HC_CHIP_ID); +- dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", +- chipid & 0xffff, chipid >> 16); ++ chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); ++ chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); ++ chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); ++ dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n", ++ chipid_h, chipid_l, chip_rev); + + /* PTD Register Init Part 2, Step 28 */ + + /* Setup registers controlling PTD checking */ +- isp1760_reg_write(priv->regs, ISP176x_HC_ATL_PTD_LASTPTD, 0x80000000); +- isp1760_reg_write(priv->regs, ISP176x_HC_INT_PTD_LASTPTD, 0x80000000); +- isp1760_reg_write(priv->regs, ISP176x_HC_ISO_PTD_LASTPTD, 0x00000001); +- isp1760_reg_write(priv->regs, ISP176x_HC_ATL_PTD_SKIPMAP, 0xffffffff); +- isp1760_reg_write(priv->regs, ISP176x_HC_INT_PTD_SKIPMAP, 0xffffffff); +- isp1760_reg_write(priv->regs, ISP176x_HC_ISO_PTD_SKIPMAP, 0xffffffff); ++ ptd_atl_int = 0x80000000; ++ ptd_iso = 0x00000001; ++ ++ isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); ++ isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); ++ isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); ++ ++ isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); + + isp1760_hcd_set(hcd, ATL_BUF_FILL); + isp1760_hcd_set(hcd, INT_BUF_FILL); +@@ -1623,19 +1973,16 @@ static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, + /* We need to forcefully reclaim the slot since some transfers never + return, e.g. interrupt transfers and NAKed bulk transfers. */ + if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { +- skip_map = isp1760_reg_read(priv->regs, +- ISP176x_HC_ATL_PTD_SKIPMAP); ++ skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); + skip_map |= (1 << qh->slot); +- isp1760_reg_write(priv->regs, ISP176x_HC_ATL_PTD_SKIPMAP, +- skip_map); ++ isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); ++ ndelay(100); + priv->atl_slots[qh->slot].qh = NULL; + priv->atl_slots[qh->slot].qtd = NULL; + } else { +- skip_map = isp1760_reg_read(priv->regs, +- ISP176x_HC_INT_PTD_SKIPMAP); ++ skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); + skip_map |= (1 << qh->slot); +- isp1760_reg_write(priv->regs, ISP176x_HC_INT_PTD_SKIPMAP, +- skip_map); ++ isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); + priv->int_slots[qh->slot].qh = NULL; + priv->int_slots[qh->slot].qtd = NULL; + } +@@ -1791,7 +2138,7 @@ static void isp1760_hub_descriptor(struct isp1760_hcd *priv, + int ports; + u16 temp; + +- ports = isp1760_hcd_read(priv->hcd, HCS_N_PORTS); ++ ports = isp1760_hcd_n_ports(priv->hcd); + + desc->bDescriptorType = USB_DT_HUB; + /* priv 1.0, 2.3.9 says 20ms max */ +@@ -1808,7 +2155,7 @@ static void isp1760_hub_descriptor(struct isp1760_hcd *priv, + + /* per-port overcurrent reporting */ + temp = HUB_CHAR_INDV_PORT_OCPM; +- if (isp1760_hcd_is_set(priv->hcd, HCS_PPC)) ++ if (isp1760_hcd_ppc_is_set(priv->hcd)) + /* per-port power control */ + temp |= HUB_CHAR_INDV_PORT_LPSM; + else +@@ -1849,7 +2196,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + int retval = 0; + int ports; + +- ports = isp1760_hcd_read(hcd, HCS_N_PORTS); ++ ports = isp1760_hcd_n_ports(hcd); + + /* + * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. +@@ -1908,7 +2255,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + /* we auto-clear this feature */ + break; + case USB_PORT_FEAT_POWER: +- if (isp1760_hcd_is_set(hcd, HCS_PPC)) ++ if (isp1760_hcd_ppc_is_set(hcd)) + isp1760_hcd_clear(hcd, PORT_POWER); + break; + case USB_PORT_FEAT_C_CONNECTION: +@@ -1923,7 +2270,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + default: + goto error; + } +- isp1760_reg_read(priv->regs, ISP176x_HC_USBCMD); ++ isp1760_hcd_read(hcd, CMD_RUN); + break; + case GetHubDescriptor: + isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) +@@ -1943,7 +2290,6 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + if (isp1760_hcd_is_set(hcd, PORT_CSC)) + status |= USB_PORT_STAT_C_CONNECTION << 16; + +- + /* whoever resumes must GetPortStatus to complete it!! */ + if (isp1760_hcd_is_set(hcd, PORT_RESUME)) { + dev_err(hcd->self.controller, "Port resume should be skipped.\n"); +@@ -1966,7 +2312,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + /* stop resume signaling */ + isp1760_hcd_clear(hcd, PORT_CSC); + +- retval = isp1760_hcd_clear_poll_timeout(hcd, ++ retval = isp1760_hcd_clear_and_wait(hcd, + PORT_RESUME, 2000); + if (retval != 0) { + dev_err(hcd->self.controller, +@@ -1987,11 +2333,11 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + /* REVISIT: some hardware needs 550+ usec to clear + * this bit; seems too long to spin routinely... + */ +- retval = isp1760_hcd_clear_poll_timeout(hcd, PORT_RESET, +- 750); ++ retval = isp1760_hcd_clear_and_wait(hcd, PORT_RESET, ++ 750); + if (retval != 0) { + dev_err(hcd->self.controller, "port %d reset error %d\n", +- wIndex + 1, retval); ++ wIndex + 1, retval); + goto error; + } + +@@ -2039,6 +2385,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + if (!wIndex || wIndex > ports) + goto error; + wIndex--; ++ + if (isp1760_hcd_is_set(hcd, PORT_OWNER)) + break; + +@@ -2055,7 +2402,7 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + isp1760_hcd_set(hcd, PORT_SUSPEND); + break; + case USB_PORT_FEAT_POWER: +- if (isp1760_hcd_is_set(hcd, HCS_PPC)) ++ if (isp1760_hcd_ppc_is_set(hcd)) + isp1760_hcd_set(hcd, PORT_POWER); + break; + case USB_PORT_FEAT_RESET: +@@ -2084,7 +2431,6 @@ static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, + default: + goto error; + } +- isp1760_reg_read(priv->regs, ISP176x_HC_USBCMD); + break; + + default: +@@ -2219,22 +2565,14 @@ int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, + + priv->hcd = hcd; + +- priv->memory_pool = kcalloc(mem_layout->payload_blocks, +- sizeof(struct isp1760_memory_chunk), +- GFP_KERNEL); +- if (!priv->memory_pool) { +- ret = -ENOMEM; +- goto put_hcd; +- } +- +- priv->atl_slots = kcalloc(mem_layout->ptd_num, ++ priv->atl_slots = kcalloc(mem_layout->slot_num, + sizeof(struct isp1760_slotinfo), GFP_KERNEL); + if (!priv->atl_slots) { + ret = -ENOMEM; +- goto free_mem_pool; ++ goto put_hcd; + } + +- priv->int_slots = kcalloc(mem_layout->ptd_num, ++ priv->int_slots = kcalloc(mem_layout->slot_num, + sizeof(struct isp1760_slotinfo), GFP_KERNEL); + if (!priv->int_slots) { + ret = -ENOMEM; +@@ -2262,8 +2600,6 @@ int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, + kfree(priv->int_slots); + free_atl_slots: + kfree(priv->atl_slots); +-free_mem_pool: +- kfree(priv->memory_pool); + put_hcd: + usb_put_hcd(hcd); + return ret; +@@ -2278,5 +2614,4 @@ void isp1760_hcd_unregister(struct isp1760_hcd *priv) + usb_put_hcd(priv->hcd); + kfree(priv->atl_slots); + kfree(priv->int_slots); +- kfree(priv->memory_pool); + } +diff --git a/drivers/usb/isp1760/isp1760-hcd.h b/drivers/usb/isp1760/isp1760-hcd.h +index 9d2427ce3f1a..ee3063a34de3 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.h ++++ b/drivers/usb/isp1760/isp1760-hcd.h +@@ -19,13 +19,14 @@ struct isp1760_slotinfo { + }; + + /* chip memory management */ ++#define ISP176x_BLOCK_MAX (32 + 20 + 4) + #define ISP176x_BLOCK_NUM 3 + + struct isp1760_memory_layout { + unsigned int blocks[ISP176x_BLOCK_NUM]; + unsigned int blocks_size[ISP176x_BLOCK_NUM]; + +- unsigned int ptd_num; ++ unsigned int slot_num; + unsigned int payload_blocks; + unsigned int payload_area_size; + }; +@@ -51,6 +52,7 @@ struct isp1760_hcd { + struct regmap *regs; + struct regmap_field *fields[HC_FIELD_MAX]; + ++ bool is_isp1763; + const struct isp1760_memory_layout *memory_layout; + + spinlock_t lock; +@@ -58,7 +60,7 @@ struct isp1760_hcd { + int atl_done_map; + struct isp1760_slotinfo *int_slots; + int int_done_map; +- struct isp1760_memory_chunk *memory_pool; ++ struct isp1760_memory_chunk memory_pool[ISP176x_BLOCK_MAX]; + struct list_head qh_list[QH_END]; + + /* periodic schedule support */ +diff --git a/drivers/usb/isp1760/isp1760-if.c b/drivers/usb/isp1760/isp1760-if.c +index cb3e4d782315..7cc349c0b2ad 100644 +--- a/drivers/usb/isp1760/isp1760-if.c ++++ b/drivers/usb/isp1760/isp1760-if.c +@@ -7,6 +7,7 @@ + * - PDEV (generic platform device centralized driver model) + * + * (c) 2007 Sebastian Siewior ++ * Copyright 2021 Linaro, Rui Miguel Silva + * + */ + +@@ -209,10 +210,18 @@ static int isp1760_plat_probe(struct platform_device *pdev) + if (of_device_is_compatible(dp, "nxp,usb-isp1761")) + devflags |= ISP1760_FLAG_ISP1761; + +- /* Some systems wire up only 16 of the 32 data lines */ ++ if (of_device_is_compatible(dp, "nxp,usb-isp1763")) ++ devflags |= ISP1760_FLAG_ISP1763; ++ ++ /* ++ * Some systems wire up only 8 of 16 data lines or ++ * 16 of the 32 data lines ++ */ + of_property_read_u32(dp, "bus-width", &bus_width); + if (bus_width == 16) + devflags |= ISP1760_FLAG_BUS_WIDTH_16; ++ else if (bus_width == 8) ++ devflags |= ISP1760_FLAG_BUS_WIDTH_8; + + if (usb_get_dr_mode(&pdev->dev) == USB_DR_MODE_PERIPHERAL) + devflags |= ISP1760_FLAG_PERIPHERAL_EN; +@@ -250,6 +259,7 @@ static int isp1760_plat_remove(struct platform_device *pdev) + static const struct of_device_id isp1760_of_match[] = { + { .compatible = "nxp,usb-isp1760", }, + { .compatible = "nxp,usb-isp1761", }, ++ { .compatible = "nxp,usb-isp1763", }, + { }, + }; + MODULE_DEVICE_TABLE(of, isp1760_of_match); +diff --git a/drivers/usb/isp1760/isp1760-regs.h b/drivers/usb/isp1760/isp1760-regs.h +index 0d5262c37c5b..4f632cbbbd1f 100644 +--- a/drivers/usb/isp1760/isp1760-regs.h ++++ b/drivers/usb/isp1760/isp1760-regs.h +@@ -2,12 +2,14 @@ + /* + * Driver for the NXP ISP1760 chip + * ++ * Copyright 2021 Linaro, Rui Miguel Silva + * Copyright 2014 Laurent Pinchart + * Copyright 2007 Sebastian Siewior + * + * Contacts: + * Sebastian Siewior + * Laurent Pinchart ++ * Rui Miguel Silva + */ + + #ifndef _ISP176x_REGS_H_ +@@ -17,8 +19,8 @@ + * Host Controller + */ + ++/* ISP1760/31 */ + /* EHCI capability registers */ +-#define ISP176x_HC_CAPLENGTH 0x000 + #define ISP176x_HC_VERSION 0x002 + #define ISP176x_HC_HCSPARAMS 0x004 + #define ISP176x_HC_HCCPARAMS 0x008 +@@ -59,7 +61,13 @@ + #define ISP176x_HC_INT_IRQ_MASK_AND 0x328 + #define ISP176x_HC_ATL_IRQ_MASK_AND 0x32c + ++#define ISP176x_HC_OTG_CTRL_SET 0x374 ++#define ISP176x_HC_OTG_CTRL_CLEAR 0x376 ++ + enum isp176x_host_controller_fields { ++ /* HC_PORTSC1 */ ++ PORT_OWNER, PORT_POWER, PORT_LSTATUS, PORT_RESET, PORT_SUSPEND, ++ PORT_RESUME, PORT_PE, PORT_CSC, PORT_CONNECT, + /* HC_HCSPARAMS */ + HCS_PPC, HCS_N_PORTS, + /* HC_HCCPARAMS */ +@@ -72,25 +80,86 @@ enum isp176x_host_controller_fields { + HC_FRINDEX, + /* HC_CONFIGFLAG */ + FLAG_CF, +- /* HC_PORTSC1 */ +- PORT_OWNER, PORT_POWER, PORT_LSTATUS, PORT_RESET, PORT_SUSPEND, +- PORT_RESUME, PORT_PE, PORT_CSC, PORT_CONNECT, ++ /* ISO/INT/ATL PTD */ ++ HC_ISO_PTD_DONEMAP, HC_ISO_PTD_SKIPMAP, HC_ISO_PTD_LASTPTD, ++ HC_INT_PTD_DONEMAP, HC_INT_PTD_SKIPMAP, HC_INT_PTD_LASTPTD, ++ HC_ATL_PTD_DONEMAP, HC_ATL_PTD_SKIPMAP, HC_ATL_PTD_LASTPTD, + /* HC_HW_MODE_CTRL */ + ALL_ATX_RESET, HW_ANA_DIGI_OC, HW_DEV_DMA, HW_COMN_IRQ, HW_COMN_DMA, + HW_DATA_BUS_WIDTH, HW_DACK_POL_HIGH, HW_DREQ_POL_HIGH, HW_INTR_HIGH_ACT, +- HW_INTR_EDGE_TRIG, HW_GLOBAL_INTR_EN, ++ HW_INTF_LOCK, HW_INTR_EDGE_TRIG, HW_GLOBAL_INTR_EN, ++ /* HC_CHIP_ID */ ++ HC_CHIP_ID_HIGH, HC_CHIP_ID_LOW, HC_CHIP_REV, ++ /* HC_SCRATCH */ ++ HC_SCRATCH, + /* HC_RESET */ +- SW_RESET_RESET_HC, SW_RESET_RESET_ALL, ++ SW_RESET_RESET_ATX, SW_RESET_RESET_HC, SW_RESET_RESET_ALL, + /* HC_BUFFER_STATUS */ +- INT_BUF_FILL, ATL_BUF_FILL, ++ ISO_BUF_FILL, INT_BUF_FILL, ATL_BUF_FILL, + /* HC_MEMORY */ + MEM_BANK_SEL, MEM_START_ADDR, ++ /* HC_DATA */ ++ HC_DATA, ++ /* HC_INTERRUPT */ ++ HC_INTERRUPT, + /* HC_INTERRUPT_ENABLE */ +- HC_INT_ENABLE, ++ HC_INT_IRQ_ENABLE, HC_ATL_IRQ_ENABLE, ++ /* INTERRUPT MASKS */ ++ HC_ISO_IRQ_MASK_OR, HC_INT_IRQ_MASK_OR, HC_ATL_IRQ_MASK_OR, ++ HC_ISO_IRQ_MASK_AND, HC_INT_IRQ_MASK_AND, HC_ATL_IRQ_MASK_AND, ++ /* HW_OTG_CTRL_SET */ ++ HW_OTG_DISABLE, HW_SW_SEL_HC_DC, HW_VBUS_DRV, HW_SEL_CP_EXT, ++ HW_DM_PULLDOWN, HW_DP_PULLDOWN, HW_DP_PULLUP, HW_HC_2_DIS, ++ /* HW_OTG_CTRL_CLR */ ++ HW_OTG_DISABLE_CLEAR, HW_SW_SEL_HC_DC_CLEAR, HW_VBUS_DRV_CLEAR, ++ HW_SEL_CP_EXT_CLEAR, HW_DM_PULLDOWN_CLEAR, HW_DP_PULLDOWN_CLEAR, ++ HW_DP_PULLUP_CLEAR, HW_HC_2_DIS_CLEAR, + /* Last element */ + HC_FIELD_MAX, + }; + ++/* ISP1763 */ ++/* EHCI operational registers */ ++#define ISP1763_HC_USBCMD 0x8c ++#define ISP1763_HC_USBSTS 0x90 ++#define ISP1763_HC_FRINDEX 0x98 ++ ++#define ISP1763_HC_CONFIGFLAG 0x9c ++#define ISP1763_HC_PORTSC1 0xa0 ++ ++#define ISP1763_HC_ISO_PTD_DONEMAP 0xa4 ++#define ISP1763_HC_ISO_PTD_SKIPMAP 0xa6 ++#define ISP1763_HC_ISO_PTD_LASTPTD 0xa8 ++#define ISP1763_HC_INT_PTD_DONEMAP 0xaa ++#define ISP1763_HC_INT_PTD_SKIPMAP 0xac ++#define ISP1763_HC_INT_PTD_LASTPTD 0xae ++#define ISP1763_HC_ATL_PTD_DONEMAP 0xb0 ++#define ISP1763_HC_ATL_PTD_SKIPMAP 0xb2 ++#define ISP1763_HC_ATL_PTD_LASTPTD 0xb4 ++ ++/* Configuration Register */ ++#define ISP1763_HC_HW_MODE_CTRL 0xb6 ++#define ISP1763_HC_CHIP_REV 0x70 ++#define ISP1763_HC_CHIP_ID 0x72 ++#define ISP1763_HC_SCRATCH 0x78 ++#define ISP1763_HC_RESET 0xb8 ++#define ISP1763_HC_BUFFER_STATUS 0xba ++#define ISP1763_HC_MEMORY 0xc4 ++#define ISP1763_HC_DATA 0xc6 ++ ++/* Interrupt Register */ ++#define ISP1763_HC_INTERRUPT 0xd4 ++#define ISP1763_HC_INTERRUPT_ENABLE 0xd6 ++#define ISP1763_HC_ISO_IRQ_MASK_OR 0xd8 ++#define ISP1763_HC_INT_IRQ_MASK_OR 0xda ++#define ISP1763_HC_ATL_IRQ_MASK_OR 0xdc ++#define ISP1763_HC_ISO_IRQ_MASK_AND 0xde ++#define ISP1763_HC_INT_IRQ_MASK_AND 0xe0 ++#define ISP1763_HC_ATL_IRQ_MASK_AND 0xe2 ++ ++#define ISP1763_HC_OTG_CTRL_SET 0xe4 ++#define ISP1763_HC_OTG_CTRL_CLEAR 0xe6 ++ + /* ----------------------------------------------------------------------------- + * Peripheral Controller + */ +@@ -132,9 +201,6 @@ enum isp176x_host_controller_fields { + #define ISP176x_DC_CTRLFUNC 0x0228 + #define ISP176x_DC_EPINDEX 0x022c + +-#define ISP1761_DC_OTG_CTRL_SET 0x374 +-#define ISP1761_DC_OTG_CTRL_CLEAR 0x376 +- + /* DMA Registers */ + #define ISP176x_DC_DMACMD 0x0230 + #define ISP176x_DC_DMATXCOUNT 0x0234 +@@ -177,13 +243,6 @@ enum isp176x_device_controller_fields { + DC_EPENABLE, DC_ENDPTYP, + /* DC_FRAMENUM */ + DC_FRAMENUM, DC_UFRAMENUM, +- /* HW_OTG_CTRL_SET */ +- HW_OTG_DISABLE, HW_SW_SEL_HC_DC, HW_VBUS_DRV, HW_SEL_CP_EXT, +- HW_DM_PULLDOWN, HW_DP_PULLDOWN, HW_DP_PULLUP, +- /* HW_OTG_CTRL_CLR */ +- HW_OTG_DISABLE_CLEAR, HW_SW_SEL_HC_DC_CLEAR, HW_VBUS_DRV_CLEAR, +- HW_SEL_CP_EXT_CLEAR, HW_DM_PULLDOWN_CLEAR, HW_DP_PULLDOWN_CLEAR, +- HW_DP_PULLUP_CLEAR, + /* Last element */ + DC_FIELD_MAX, + }; +diff --git a/drivers/usb/isp1760/isp1760-udc.c b/drivers/usb/isp1760/isp1760-udc.c +index 1e2ca43fb152..30efc9d32506 100644 +--- a/drivers/usb/isp1760/isp1760-udc.c ++++ b/drivers/usb/isp1760/isp1760-udc.c +@@ -2,10 +2,12 @@ + /* + * Driver for the NXP ISP1761 device controller + * ++ * Copyright 2021 Linaro, Rui Miguel Silva + * Copyright 2014 Ideas on Board Oy + * + * Contacts: + * Laurent Pinchart ++ * Rui Miguel Silva + */ + + #include +diff --git a/drivers/usb/isp1760/isp1760-udc.h b/drivers/usb/isp1760/isp1760-udc.h +index a49096c0ac8e..f2ab5929cc9f 100644 +--- a/drivers/usb/isp1760/isp1760-udc.h ++++ b/drivers/usb/isp1760/isp1760-udc.h +@@ -2,10 +2,12 @@ + /* + * Driver for the NXP ISP1761 device controller + * ++ * Copyright 2021 Linaro, Rui Miguel Silva + * Copyright 2014 Ideas on Board Oy + * + * Contacts: + * Laurent Pinchart ++ * Rui Miguel Silva + */ + + #ifndef _ISP1760_UDC_H_ +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0008-dt-bindings-usb-nxp-isp1760-add-bindings.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0008-dt-bindings-usb-nxp-isp1760-add-bindings.patch new file mode 100644 index 0000000..88a701c --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0008-dt-bindings-usb-nxp-isp1760-add-bindings.patch @@ -0,0 +1,99 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From e7a990e00cb13ce66d4008e3b77e8507be0c2e27 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 13 May 2021 09:47:16 +0100 +Subject: [PATCH 8/9] dt-bindings: usb: nxp,isp1760: add bindings + +The nxp,isp1760 driver is old in the tree, but did not had a bindings +entry, since I am extend it to support isp1763 in the same family, use +this to add a proper yaml bindings file. + +Reviewed-by: Rob Herring +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210513084717.2487366-9-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + .../devicetree/bindings/usb/nxp,isp1760.yaml | 69 +++++++++++++++++++ + 1 file changed, 69 insertions(+) + create mode 100644 Documentation/devicetree/bindings/usb/nxp,isp1760.yaml + +diff --git a/Documentation/devicetree/bindings/usb/nxp,isp1760.yaml b/Documentation/devicetree/bindings/usb/nxp,isp1760.yaml +new file mode 100644 +index 000000000000..a88f99adfe8e +--- /dev/null ++++ b/Documentation/devicetree/bindings/usb/nxp,isp1760.yaml +@@ -0,0 +1,69 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/usb/nxp,isp1760.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: NXP ISP1760 family controller bindings ++ ++maintainers: ++ - Sebastian Siewior ++ - Laurent Pinchart ++ ++description: | ++ NXP ISP1760 family, which includes ISP1760/1761/1763 devicetree controller ++ bindings ++ ++properties: ++ compatible: ++ enum: ++ - nxp,usb-isp1760 ++ - nxp,usb-isp1761 ++ - nxp,usb-isp1763 ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ minItems: 1 ++ maxItems: 2 ++ items: ++ - description: Host controller interrupt ++ - description: Device controller interrupt in isp1761 ++ ++ interrupt-names: ++ minItems: 1 ++ maxItems: 2 ++ items: ++ - const: host ++ - const: peripheral ++ ++ bus-width: ++ description: ++ Number of data lines. ++ enum: [8, 16, 32] ++ default: 32 ++ ++ dr_mode: ++ enum: ++ - host ++ - peripheral ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ usb@40200000 { ++ compatible = "nxp,usb-isp1763"; ++ reg = <0x40200000 0x100000>; ++ interrupts = ; ++ bus-width = <16>; ++ dr_mode = "host"; ++ }; ++ ++... +-- +2.32.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0009-usb-isp1763-add-peripheral-mode.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0009-usb-isp1763-add-peripheral-mode.patch new file mode 100644 index 0000000..7b06c91 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0009-usb-isp1763-add-peripheral-mode.patch @@ -0,0 +1,303 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From d369c9187c1897ce5339716354ce47b2c2f67352 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 13 May 2021 09:47:17 +0100 +Subject: [PATCH 08/23] usb: isp1763: add peripheral mode + +Besides the already host mode support add peripheral mode support for +the isp1763 IP from the isp1760 family. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210513084717.2487366-10-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-core.c | 25 +++++++++++------ + drivers/usb/isp1760/isp1760-regs.h | 42 ++++++++++++++++++++++++++++ + drivers/usb/isp1760/isp1760-udc.c | 45 ++++++++++++++++++++++-------- + drivers/usb/isp1760/isp1760-udc.h | 1 + + 4 files changed, 94 insertions(+), 19 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-core.c b/drivers/usb/isp1760/isp1760-core.c +index 1d847f13abab..ff07e2890692 100644 +--- a/drivers/usb/isp1760/isp1760-core.c ++++ b/drivers/usb/isp1760/isp1760-core.c +@@ -83,7 +83,8 @@ static int isp1760_init_core(struct isp1760_device *isp) + * + * TODO: Really support OTG. For now we configure port 1 in device mode + */ +- if ((isp->devflags & ISP1760_FLAG_ISP1761) && ++ if (((isp->devflags & ISP1760_FLAG_ISP1761) || ++ (isp->devflags & ISP1760_FLAG_ISP1763)) && + (isp->devflags & ISP1760_FLAG_PERIPHERAL_EN)) { + isp1760_field_set(hcd->fields, HW_DM_PULLDOWN); + isp1760_field_set(hcd->fields, HW_DP_PULLDOWN); +@@ -470,13 +471,15 @@ static const struct regmap_config isp1763_dc_regmap_conf = { + int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + struct device *dev, unsigned int devflags) + { +- bool udc_disabled = !(devflags & ISP1760_FLAG_ISP1761); + const struct regmap_config *hc_regmap; + const struct reg_field *hc_reg_fields; ++ const struct regmap_config *dc_regmap; ++ const struct reg_field *dc_reg_fields; + struct isp1760_device *isp; + struct isp1760_hcd *hcd; + struct isp1760_udc *udc; + struct regmap_field *f; ++ bool udc_enabled; + int ret; + int i; + +@@ -484,8 +487,11 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + * If neither the HCD not the UDC is enabled return an error, as no + * device would be registered. + */ ++ udc_enabled = ((devflags & ISP1760_FLAG_ISP1763) || ++ (devflags & ISP1760_FLAG_ISP1761)); ++ + if ((!IS_ENABLED(CONFIG_USB_ISP1760_HCD) || usb_disabled()) && +- (!IS_ENABLED(CONFIG_USB_ISP1761_UDC) || udc_disabled)) ++ (!IS_ENABLED(CONFIG_USB_ISP1761_UDC) || !udc_enabled)) + return -ENODEV; + + isp = devm_kzalloc(dev, sizeof(*isp), GFP_KERNEL); +@@ -498,6 +504,7 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + udc = &isp->udc; + + hcd->is_isp1763 = !!(devflags & ISP1760_FLAG_ISP1763); ++ udc->is_isp1763 = !!(devflags & ISP1760_FLAG_ISP1763); + + if (!hcd->is_isp1763 && (devflags & ISP1760_FLAG_BUS_WIDTH_8)) { + dev_err(dev, "isp1760/61 do not support data width 8\n"); +@@ -507,9 +514,13 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + if (hcd->is_isp1763) { + hc_regmap = &isp1763_hc_regmap_conf; + hc_reg_fields = &isp1763_hc_reg_fields[0]; ++ dc_regmap = &isp1763_dc_regmap_conf; ++ dc_reg_fields = &isp1763_dc_reg_fields[0]; + } else { + hc_regmap = &isp1760_hc_regmap_conf; + hc_reg_fields = &isp1760_hc_reg_fields[0]; ++ dc_regmap = &isp1761_dc_regmap_conf; ++ dc_reg_fields = &isp1761_dc_reg_fields[0]; + } + + isp->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); +@@ -532,14 +543,12 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + hcd->fields[i] = f; + } + +- udc->regs = devm_regmap_init_mmio(dev, hcd->base, +- &isp1761_dc_regmap_conf); ++ udc->regs = devm_regmap_init_mmio(dev, hcd->base, dc_regmap); + if (IS_ERR(udc->regs)) + return PTR_ERR(udc->regs); + + for (i = 0; i < DC_FIELD_MAX; i++) { +- f = devm_regmap_field_alloc(dev, udc->regs, +- isp1761_dc_reg_fields[i]); ++ f = devm_regmap_field_alloc(dev, udc->regs, dc_reg_fields[i]); + if (IS_ERR(f)) + return PTR_ERR(f); + +@@ -562,7 +571,7 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + return ret; + } + +- if (IS_ENABLED(CONFIG_USB_ISP1761_UDC) && !udc_disabled) { ++ if (IS_ENABLED(CONFIG_USB_ISP1761_UDC) && udc_enabled) { + ret = isp1760_udc_register(isp, irq, irqflags); + if (ret < 0) { + isp1760_hcd_unregister(hcd); +diff --git a/drivers/usb/isp1760/isp1760-regs.h b/drivers/usb/isp1760/isp1760-regs.h +index 4f632cbbbd1f..94ea60c20b2a 100644 +--- a/drivers/usb/isp1760/isp1760-regs.h ++++ b/drivers/usb/isp1760/isp1760-regs.h +@@ -243,8 +243,50 @@ enum isp176x_device_controller_fields { + DC_EPENABLE, DC_ENDPTYP, + /* DC_FRAMENUM */ + DC_FRAMENUM, DC_UFRAMENUM, ++ /* DC_CHIP_ID */ ++ DC_CHIP_ID_HIGH, DC_CHIP_ID_LOW, ++ /* DC_SCRATCH */ ++ DC_SCRATCH, + /* Last element */ + DC_FIELD_MAX, + }; + ++/* ISP1763 */ ++/* Initialization Registers */ ++#define ISP1763_DC_ADDRESS 0x00 ++#define ISP1763_DC_MODE 0x0c ++#define ISP1763_DC_INTCONF 0x10 ++#define ISP1763_DC_INTENABLE 0x14 ++ ++/* Data Flow Registers */ ++#define ISP1763_DC_EPMAXPKTSZ 0x04 ++#define ISP1763_DC_EPTYPE 0x08 ++ ++#define ISP1763_DC_BUFLEN 0x1c ++#define ISP1763_DC_BUFSTAT 0x1e ++#define ISP1763_DC_DATAPORT 0x20 ++ ++#define ISP1763_DC_CTRLFUNC 0x28 ++#define ISP1763_DC_EPINDEX 0x2c ++ ++/* DMA Registers */ ++#define ISP1763_DC_DMACMD 0x30 ++#define ISP1763_DC_DMATXCOUNT 0x34 ++#define ISP1763_DC_DMACONF 0x38 ++#define ISP1763_DC_DMAHW 0x3c ++#define ISP1763_DC_DMAINTREASON 0x50 ++#define ISP1763_DC_DMAINTEN 0x54 ++#define ISP1763_DC_DMAEP 0x58 ++#define ISP1763_DC_DMABURSTCOUNT 0x64 ++ ++/* General Registers */ ++#define ISP1763_DC_INTERRUPT 0x18 ++#define ISP1763_DC_CHIPID_LOW 0x70 ++#define ISP1763_DC_CHIPID_HIGH 0x72 ++#define ISP1763_DC_FRAMENUM 0x74 ++#define ISP1763_DC_SCRATCH 0x78 ++#define ISP1763_DC_UNLOCKDEV 0x7c ++#define ISP1763_DC_INTPULSEWIDTH 0x80 ++#define ISP1763_DC_TESTMODE 0x84 ++ + #endif +diff --git a/drivers/usb/isp1760/isp1760-udc.c b/drivers/usb/isp1760/isp1760-udc.c +index 30efc9d32506..3e05e3605435 100644 +--- a/drivers/usb/isp1760/isp1760-udc.c ++++ b/drivers/usb/isp1760/isp1760-udc.c +@@ -1151,6 +1151,10 @@ static void isp1760_udc_disconnect(struct isp1760_udc *udc) + + static void isp1760_udc_init_hw(struct isp1760_udc *udc) + { ++ u32 intconf = udc->is_isp1763 ? ISP1763_DC_INTCONF : ISP176x_DC_INTCONF; ++ u32 intena = udc->is_isp1763 ? ISP1763_DC_INTENABLE : ++ ISP176x_DC_INTENABLE; ++ + /* + * The device controller currently shares its interrupt with the host + * controller, the DC_IRQ polarity and signaling mode are ignored. Set +@@ -1160,11 +1164,11 @@ static void isp1760_udc_init_hw(struct isp1760_udc *udc) + * ACK tokens only (and NYET for the out pipe). The default + * configuration also generates an interrupt on the first NACK token. + */ +- isp1760_reg_write(udc->regs, ISP176x_DC_INTCONF, ++ isp1760_reg_write(udc->regs, intconf, + ISP176x_DC_CDBGMOD_ACK | ISP176x_DC_DDBGMODIN_ACK | + ISP176x_DC_DDBGMODOUT_ACK); + +- isp1760_reg_write(udc->regs, ISP176x_DC_INTENABLE, DC_IEPRXTX(7) | ++ isp1760_reg_write(udc->regs, intena, DC_IEPRXTX(7) | + DC_IEPRXTX(6) | DC_IEPRXTX(5) | DC_IEPRXTX(4) | + DC_IEPRXTX(3) | DC_IEPRXTX(2) | DC_IEPRXTX(1) | + DC_IEPRXTX(0) | ISP176x_DC_IEP0SETUP | +@@ -1304,13 +1308,14 @@ static int isp1760_udc_start(struct usb_gadget *gadget, + static int isp1760_udc_stop(struct usb_gadget *gadget) + { + struct isp1760_udc *udc = gadget_to_udc(gadget); ++ u32 mode_reg = udc->is_isp1763 ? ISP1763_DC_MODE : ISP176x_DC_MODE; + unsigned long flags; + + dev_dbg(udc->isp->dev, "%s\n", __func__); + + del_timer_sync(&udc->vbus_timer); + +- isp1760_reg_write(udc->regs, ISP176x_DC_MODE, 0); ++ isp1760_reg_write(udc->regs, mode_reg, 0); + + spin_lock_irqsave(&udc->lock, flags); + udc->driver = NULL; +@@ -1332,15 +1337,30 @@ static const struct usb_gadget_ops isp1760_udc_ops = { + * Interrupt Handling + */ + ++static u32 isp1760_udc_irq_get_status(struct isp1760_udc *udc) ++{ ++ u32 status; ++ ++ if (udc->is_isp1763) { ++ status = isp1760_reg_read(udc->regs, ISP1763_DC_INTERRUPT) ++ & isp1760_reg_read(udc->regs, ISP1763_DC_INTENABLE); ++ isp1760_reg_write(udc->regs, ISP1763_DC_INTERRUPT, status); ++ } else { ++ status = isp1760_reg_read(udc->regs, ISP176x_DC_INTERRUPT) ++ & isp1760_reg_read(udc->regs, ISP176x_DC_INTENABLE); ++ isp1760_reg_write(udc->regs, ISP176x_DC_INTERRUPT, status); ++ } ++ ++ return status; ++} ++ + static irqreturn_t isp1760_udc_irq(int irq, void *dev) + { + struct isp1760_udc *udc = dev; + unsigned int i; + u32 status; + +- status = isp1760_reg_read(udc->regs, ISP176x_DC_INTERRUPT) +- & isp1760_reg_read(udc->regs, ISP176x_DC_INTENABLE); +- isp1760_reg_write(udc->regs, ISP176x_DC_INTERRUPT, status); ++ status = isp1760_udc_irq_get_status(udc); + + if (status & DC_IEVBUS) { + dev_dbg(udc->isp->dev, "%s(VBUS)\n", __func__); +@@ -1475,6 +1495,7 @@ static void isp1760_udc_init_eps(struct isp1760_udc *udc) + + static int isp1760_udc_init(struct isp1760_udc *udc) + { ++ u32 mode_reg = udc->is_isp1763 ? ISP1763_DC_MODE : ISP176x_DC_MODE; + u16 scratch; + u32 chipid; + +@@ -1484,9 +1505,10 @@ static int isp1760_udc_init(struct isp1760_udc *udc) + * register, and reading the scratch register value back. The chip ID + * and scratch register contents must match the expected values. + */ +- isp1760_reg_write(udc->regs, ISP176x_DC_SCRATCH, 0xbabe); +- chipid = isp1760_reg_read(udc->regs, ISP176x_DC_CHIPID); +- scratch = isp1760_reg_read(udc->regs, ISP176x_DC_SCRATCH); ++ isp1760_udc_write(udc, DC_SCRATCH, 0xbabe); ++ chipid = isp1760_udc_read(udc, DC_CHIP_ID_HIGH) << 16; ++ chipid |= isp1760_udc_read(udc, DC_CHIP_ID_LOW); ++ scratch = isp1760_udc_read(udc, DC_SCRATCH); + + if (scratch != 0xbabe) { + dev_err(udc->isp->dev, +@@ -1495,7 +1517,8 @@ static int isp1760_udc_init(struct isp1760_udc *udc) + return -ENODEV; + } + +- if (chipid != 0x00011582 && chipid != 0x00158210) { ++ if (chipid != 0x00011582 && chipid != 0x00158210 && ++ chipid != 0x00176320) { + dev_err(udc->isp->dev, "udc: invalid chip ID 0x%08x\n", chipid); + return -ENODEV; + } +@@ -1503,7 +1526,7 @@ static int isp1760_udc_init(struct isp1760_udc *udc) + /* Reset the device controller. */ + isp1760_udc_set(udc, DC_SFRESET); + usleep_range(10000, 11000); +- isp1760_reg_write(udc->regs, ISP176x_DC_MODE, 0); ++ isp1760_reg_write(udc->regs, mode_reg, 0); + usleep_range(10000, 11000); + + return 0; +diff --git a/drivers/usb/isp1760/isp1760-udc.h b/drivers/usb/isp1760/isp1760-udc.h +index f2ab5929cc9f..22044e86bc0e 100644 +--- a/drivers/usb/isp1760/isp1760-udc.h ++++ b/drivers/usb/isp1760/isp1760-udc.h +@@ -84,6 +84,7 @@ struct isp1760_udc { + u16 ep0_length; + + bool connected; ++ bool is_isp1763; + + unsigned int devstatus; + }; +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0022-usb-isp1760-isp1760-udc-Provide-missing-description-.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0022-usb-isp1760-isp1760-udc-Provide-missing-description-.patch new file mode 100644 index 0000000..7e85595 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0022-usb-isp1760-isp1760-udc-Provide-missing-description-.patch @@ -0,0 +1,41 @@ +Upstream-Status: Accepted [merged with kernel 5.15] +Signed-off-by: Arpita S.K + +From 8268acfe1cc967dbe9fbb05b5f07a19675a81cff Mon Sep 17 00:00:00 2001 +From: Lee Jones +Date: Wed, 26 May 2021 14:00:19 +0100 +Subject: [PATCH 09/23] usb: isp1760: isp1760-udc: Provide missing description + for 'udc' param + +Fixes the following W=1 kernel build warning(s): + + drivers/usb/isp1760/isp1760-udc.c:150: warning: Function parameter or member 'udc' not described in 'isp1760_udc_select_ep' + +Cc: Greg Kroah-Hartman +Cc: Rui Miguel Silva +Cc: Laurent Pinchart +Cc: linux-usb@vger.kernel.org +Reviewed-by: Rui Miguel Silva +Signed-off-by: Lee Jones +Link: https://lore.kernel.org/r/20210526130037.856068-7-lee.jones@linaro.org +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Rui Miguel Silva +--- + drivers/usb/isp1760/isp1760-udc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/usb/isp1760/isp1760-udc.c b/drivers/usb/isp1760/isp1760-udc.c +index 3e05e3605435..a78da59d6417 100644 +--- a/drivers/usb/isp1760/isp1760-udc.c ++++ b/drivers/usb/isp1760/isp1760-udc.c +@@ -137,6 +137,7 @@ static void __isp1760_udc_select_ep(struct isp1760_udc *udc, + /** + * isp1760_udc_select_ep - Select an endpoint for register access + * @ep: The endpoint ++ * @udc: Reference to the device controller + * + * The ISP1761 endpoint registers are banked. This function selects the target + * endpoint for banked register access. The selection remains valid until the +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0023-usb-isp1760-Fix-meaningless-check-in-isp1763_run.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0023-usb-isp1760-Fix-meaningless-check-in-isp1763_run.patch new file mode 100644 index 0000000..a194d7b --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0023-usb-isp1760-Fix-meaningless-check-in-isp1763_run.patch @@ -0,0 +1,38 @@ +Upstream-Status: Accepted [merged with kernel 5.15] +Signed-off-by: Arpita S.K + +From 5f4dee73a4bc25a7781a5406b49439bc640981c2 Mon Sep 17 00:00:00 2001 +From: Tong Tiangen +Date: Fri, 11 Jun 2021 09:40:55 +0800 +Subject: [PATCH 10/23] usb: isp1760: Fix meaningless check in isp1763_run() + +Remove attribution to retval before check, which make it completely +meaningless, and does't check what it was supposed: the return +value of the timed function to set up configuration flag. + +Fixes: 60d789f3bfbb ("usb: isp1760: add support for isp1763") +Tested-by: Rui Miguel Silva +Reviewed-by: Rui Miguel Silva +Signed-off-by: Tong Tiangen +Link: https://lore.kernel.org/r/20210611014055.68551-1-tongtiangen@huawei.com +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Rui Miguel Silva +--- + drivers/usb/isp1760/isp1760-hcd.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index 016a54ea76f4..27168b4a4ef2 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -1648,7 +1648,6 @@ static int isp1763_run(struct usb_hcd *hcd) + down_write(&ehci_cf_port_reset_rwsem); + retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); + up_write(&ehci_cf_port_reset_rwsem); +- retval = 0; + if (retval) + return retval; + +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0024-usb-isp1760-remove-debug-message-as-error.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0024-usb-isp1760-remove-debug-message-as-error.patch new file mode 100644 index 0000000..10ccfd7 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0024-usb-isp1760-remove-debug-message-as-error.patch @@ -0,0 +1,32 @@ +Upstream-Status: Accepted [merged with kernel 5.15] +Signed-off-by: Arpita S.K + +From 7de14c88272c05d86fce83a5cead36832ce3a424 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Tue, 27 Jul 2021 11:05:14 +0100 +Subject: [PATCH 11/23] usb: isp1760: remove debug message as error + +Remove debug message leftover from the boot error buffer. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210727100516.4190681-2-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-hcd.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index 27168b4a4ef2..a745c4c2b773 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -733,7 +733,6 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) + + /* Change bus pattern */ + scratch = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); +- dev_err(hcd->self.controller, "Scratch test 0x%08x\n", scratch); + scratch = isp1760_hcd_read(hcd, HC_SCRATCH); + if (scratch != pattern) { + dev_err(hcd->self.controller, "Scratch test failed. 0x%08x\n", scratch); +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0025-usb-isp1760-do-not-sleep-in-field-register-poll.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0025-usb-isp1760-do-not-sleep-in-field-register-poll.patch new file mode 100644 index 0000000..ab6627e --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0025-usb-isp1760-do-not-sleep-in-field-register-poll.patch @@ -0,0 +1,58 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From 41f673183862a183d4ea0522c045fabfbd1b28c8 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Tue, 27 Jul 2021 11:05:15 +0100 +Subject: [PATCH 12/23] usb: isp1760: do not sleep in field register poll + +When polling for a setup or clear of a register field we were sleeping +in atomic context but using a very tight sleep interval. + +Since the use cases for this poll mechanism are only in setup and +stop paths, and in practice this poll is not used most of the times +but needs to be there to comply to hardware setup times, remove the +sleep time and make the poll loop tighter. + +Reported-by: Dan Carpenter +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210727100516.4190681-3-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-hcd.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index a745c4c2b773..a018394d54f8 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -250,7 +250,7 @@ static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field, + isp1760_hcd_set(hcd, field); + + return regmap_field_read_poll_timeout(priv->fields[field], val, +- val, 10, timeout_us); ++ val, 0, timeout_us); + } + + static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field, +@@ -262,7 +262,7 @@ static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field, + isp1760_hcd_set(hcd, field); + + return regmap_field_read_poll_timeout(priv->fields[field], val, +- !val, 10, timeout_us); ++ !val, 0, timeout_us); + } + + static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field, +@@ -274,7 +274,7 @@ static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field, + isp1760_hcd_clear(hcd, field); + + return regmap_field_read_poll_timeout(priv->fields[field], val, +- !val, 10, timeout_us); ++ !val, 0, timeout_us); + } + + static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field) +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0026-usb-isp1760-rework-cache-initialization-error-handli.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0026-usb-isp1760-rework-cache-initialization-error-handli.patch new file mode 100644 index 0000000..d03d647 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0026-usb-isp1760-rework-cache-initialization-error-handli.patch @@ -0,0 +1,55 @@ +Upstream-Status: Accepted [merged with kernel 5.15] +Signed-off-by: Arpita S.K + +From cbbdb3fe0d974d655c87c3e6ba2990d5496b9f82 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Tue, 27 Jul 2021 11:05:16 +0100 +Subject: [PATCH 13/23] usb: isp1760: rework cache initialization error + handling + +If we fail to create qtd cache we were not destroying the +urb_listitem, rework the error handling logic to cope with that. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210727100516.4190681-4-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-hcd.c | 16 +++++++++++----- + 1 file changed, 11 insertions(+), 5 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index a018394d54f8..825be736be33 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -2527,17 +2527,23 @@ int __init isp1760_init_kmem_once(void) + SLAB_MEM_SPREAD, NULL); + + if (!qtd_cachep) +- return -ENOMEM; ++ goto destroy_urb_listitem; + + qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), + 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); + +- if (!qh_cachep) { +- kmem_cache_destroy(qtd_cachep); +- return -ENOMEM; +- } ++ if (!qh_cachep) ++ goto destroy_qtd; + + return 0; ++ ++destroy_qtd: ++ kmem_cache_destroy(qtd_cachep); ++ ++destroy_urb_listitem: ++ kmem_cache_destroy(urb_listitem_cachep); ++ ++ return -ENOMEM; + } + + void isp1760_deinit_kmem_cache(void) +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0027-usb-isp1760-ignore-return-value-for-bus-change-patte.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0027-usb-isp1760-ignore-return-value-for-bus-change-patte.patch new file mode 100644 index 0000000..354291a --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0027-usb-isp1760-ignore-return-value-for-bus-change-patte.patch @@ -0,0 +1,55 @@ +Upstream-Status: Accepted [merged with kernel 5.15] +Signed-off-by: Arpita S.K + +From 8472896f39cfab2d8fec9ca746070aaf02609169 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 19 Aug 2021 19:09:25 +0100 +Subject: [PATCH 14/23] usb: isp1760: ignore return value for bus change + pattern + +We do not care about the return value of that read between the +scratch register write and read, we really just want to make sure that +the pattern in the bus get changed to make sure we are testing +correctly the scratch pattern. + +Clang-analyzer complains about the never read scratch variable: +>> drivers/usb/isp1760/isp1760-hcd.c:735:2: warning: Value stored to 'scratch' is never read [clang-analyzer-deadcode.DeadStores] + scratch = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); + +Just ignore the return value of that CHIP_ID_HIGH read, add more +information to the comment above why we are doing this. And as at it, +just do a small format change in the error message bellow. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210819180929.1327349-2-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-hcd.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index 825be736be33..2a21fe5aa7a8 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -731,11 +731,15 @@ static int isp1760_hc_setup(struct usb_hcd *hcd) + + isp1760_hcd_write(hcd, HC_SCRATCH, pattern); + +- /* Change bus pattern */ +- scratch = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); ++ /* ++ * we do not care about the read value here we just want to ++ * change bus pattern. ++ */ ++ isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); + scratch = isp1760_hcd_read(hcd, HC_SCRATCH); + if (scratch != pattern) { +- dev_err(hcd->self.controller, "Scratch test failed. 0x%08x\n", scratch); ++ dev_err(hcd->self.controller, "Scratch test failed. 0x%08x\n", ++ scratch); + return -ENODEV; + } + +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0028-usb-isp1760-check-maxpacketsize-before-using-it.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0028-usb-isp1760-check-maxpacketsize-before-using-it.patch new file mode 100644 index 0000000..67c3585 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0028-usb-isp1760-check-maxpacketsize-before-using-it.patch @@ -0,0 +1,40 @@ +Upstream-Status: Accepted [merged with kernel 5.15] +Signed-off-by: Arpita S.K + +From 8e58b7710d6634ed46ae26fedb8459f84f08fd51 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 19 Aug 2021 19:09:26 +0100 +Subject: [PATCH 15/23] usb: isp1760: check maxpacketsize before using it + +When checking if we need one more packet on a bulk pipe we may, even +though not probable at all, get there with a zero maxpacketsize. +In that case for sure no packet, no even a one more, will be +allocated. + +This will clean the clang-analyzer warning: +drivers/usb/isp1760/isp1760-hcd.c:1856:38: warning: Division by zero [clang-analyzer-core.DivideZero] + && !(urb->transfer_buffer_length % + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210819180929.1327349-3-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-hcd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index 2a21fe5aa7a8..5c947a1eae49 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -1854,7 +1854,7 @@ static void packetize_urb(struct usb_hcd *hcd, + packet_type = OUT_PID; + else + packet_type = IN_PID; +- } else if (usb_pipebulk(urb->pipe) ++ } else if (usb_pipebulk(urb->pipe) && maxpacketsize + && (urb->transfer_flags & URB_ZERO_PACKET) + && !(urb->transfer_buffer_length % + maxpacketsize)) { +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0029-usb-isp1760-do-not-reset-retval.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0029-usb-isp1760-do-not-reset-retval.patch new file mode 100644 index 0000000..ccf3248 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0029-usb-isp1760-do-not-reset-retval.patch @@ -0,0 +1,36 @@ +Upstream-Status: Accepted [merged with kernel 5.15] +Signed-off-by: Arpita S.K + +From 5e4cd1b6556302fe6a457e525c256cbef3563543 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 19 Aug 2021 19:09:27 +0100 +Subject: [PATCH 16/23] usb: isp1760: do not reset retval + +We do not really need to reset retval before get used bellow. +This will avoid the clang-analyzer warning: + +drivers/usb/isp1760/isp1760-hcd.c:1919:2: warning: Value stored to 'retval' is never read [clang-analyzer-deadcode.DeadStores] + retval = 0; + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210819180929.1327349-4-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-hcd.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index 5c947a1eae49..aed2714ce0cf 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -1919,7 +1919,6 @@ static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, + if (list_empty(&new_qtds)) + return -ENOMEM; + +- retval = 0; + spin_lock_irqsave(&priv->lock, spinflags); + + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0030-usb-isp1760-do-not-shift-in-uninitialized-slot.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0030-usb-isp1760-do-not-shift-in-uninitialized-slot.patch new file mode 100644 index 0000000..1de6c69 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0030-usb-isp1760-do-not-shift-in-uninitialized-slot.patch @@ -0,0 +1,61 @@ +Upstream-Status: Accepted [merged with kernel 5.15] +Signed-off-by: Arpita S.K + +From 7d1d3882fd9da1ee42fe3ad3a5ffd41fb8204380 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 19 Aug 2021 19:09:28 +0100 +Subject: [PATCH 17/23] usb: isp1760: do not shift in uninitialized slot + +Even though it is not expected, and would trigger a WARN_ON, killing a +transfer in a uninitialized slot this sequence is warned by clang +analyzer, twice: + +drivers/usb/isp1760/isp1760-hcd.c:1976:18: warning: The result of the left shift is undefined because the right operand is negative [clang-analyzer-core.UndefinedBinaryOperatorResult] + skip_map |= (1 << qh->slot); +drivers/usb/isp1760/isp1760-hcd.c:1983:18: warning: The result of the left shift is undefined because the right operand is negative [clang-analyzer-core.UndefinedBinaryOperatorResult] + skip_map |= (1 << qh->slot); + +Only set skip map if slot is active. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210819180929.1327349-5-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-hcd.c | 18 +++++++++++------- + 1 file changed, 11 insertions(+), 7 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index aed2714ce0cf..bf8ab3fe2e5a 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -1974,16 +1974,20 @@ static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, + /* We need to forcefully reclaim the slot since some transfers never + return, e.g. interrupt transfers and NAKed bulk transfers. */ + if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { +- skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); +- skip_map |= (1 << qh->slot); +- isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); +- ndelay(100); ++ if (qh->slot != -1) { ++ skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); ++ skip_map |= (1 << qh->slot); ++ isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); ++ ndelay(100); ++ } + priv->atl_slots[qh->slot].qh = NULL; + priv->atl_slots[qh->slot].qtd = NULL; + } else { +- skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); +- skip_map |= (1 << qh->slot); +- isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); ++ if (qh->slot != -1) { ++ skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); ++ skip_map |= (1 << qh->slot); ++ isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); ++ } + priv->int_slots[qh->slot].qh = NULL; + priv->int_slots[qh->slot].qtd = NULL; + } +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0031-usb-isp1760-clean-never-read-udc_enabled-warning.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0031-usb-isp1760-clean-never-read-udc_enabled-warning.patch new file mode 100644 index 0000000..7d908de --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0031-usb-isp1760-clean-never-read-udc_enabled-warning.patch @@ -0,0 +1,52 @@ +Upstream-Status: Accepted [merged with kernel 5.15] +Signed-off-by: Arpita S.K + +From de940244e8987a76d73fb2b0057ecd494cbfeefd Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 19 Aug 2021 19:09:29 +0100 +Subject: [PATCH 18/23] usb: isp1760: clean never read udc_enabled warning + +When CONFIG_USB_ISP1761_UDC is not enabled the udc_enabled variable is +never used since it is short circuited before in the logic operations. + +This would trigger the following warning by clang analyzer: + +drivers/usb/isp1760/isp1760-core.c:490:2: warning: Value stored to 'udc_enabled' is never read [clang-analyzer-deadcode.DeadStores] + udc_enabled = ((devflags & ISP1760_FLAG_ISP1763) || + ^ +drivers/usb/isp1760/isp1760-core.c:490:2: note: Value stored to 'udc_enabled' is never read + +Just swap the other of the operands in the logic operations. + +Signed-off-by: Rui Miguel Silva +Link: https://lore.kernel.org/r/20210819180929.1327349-6-rui.silva@linaro.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/isp1760/isp1760-core.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-core.c b/drivers/usb/isp1760/isp1760-core.c +index ff07e2890692..cb70f9d63cdd 100644 +--- a/drivers/usb/isp1760/isp1760-core.c ++++ b/drivers/usb/isp1760/isp1760-core.c +@@ -491,7 +491,7 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + (devflags & ISP1760_FLAG_ISP1761)); + + if ((!IS_ENABLED(CONFIG_USB_ISP1760_HCD) || usb_disabled()) && +- (!IS_ENABLED(CONFIG_USB_ISP1761_UDC) || !udc_enabled)) ++ (!udc_enabled || !IS_ENABLED(CONFIG_USB_ISP1761_UDC))) + return -ENODEV; + + isp = devm_kzalloc(dev, sizeof(*isp), GFP_KERNEL); +@@ -571,7 +571,7 @@ int isp1760_register(struct resource *mem, int irq, unsigned long irqflags, + return ret; + } + +- if (IS_ENABLED(CONFIG_USB_ISP1761_UDC) && udc_enabled) { ++ if (udc_enabled && IS_ENABLED(CONFIG_USB_ISP1761_UDC)) { + ret = isp1760_udc_register(isp, irq, irqflags); + if (ret < 0) { + isp1760_hcd_unregister(hcd); +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0032-usb-isp1760-fix-memory-pool-initialization.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0032-usb-isp1760-fix-memory-pool-initialization.patch new file mode 100644 index 0000000..6277d8a --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0032-usb-isp1760-fix-memory-pool-initialization.patch @@ -0,0 +1,36 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From d36713c344e0c963178e417911d2cd867597d2f0 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Fri, 27 Aug 2021 01:27:40 +0100 +Subject: [PATCH 19/23] usb: isp1760: fix memory pool initialization + +The loops to setup the memory pool were skipping some +blocks, that was not visible on the ISP1763 because it has +fewer blocks than the ISP1761. But won testing on that IP +from the family that would be an issue. + +Signed-off-by: Rui Miguel Silva +--- + drivers/usb/isp1760/isp1760-hcd.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index bf8ab3fe2e5a..b3a55c5d2155 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -588,8 +588,8 @@ static void init_memory(struct isp1760_hcd *priv) + + payload_addr = PAYLOAD_OFFSET; + +- for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++) { +- for (j = 0; j < mem->blocks[i]; j++, curr++) { ++ for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++, curr += j) { ++ for (j = 0; j < mem->blocks[i]; j++) { + priv->memory_pool[curr + j].start = payload_addr; + priv->memory_pool[curr + j].size = mem->blocks_size[i]; + priv->memory_pool[curr + j].free = 1; +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0033-usb-isp1760-fix-qtd-fill-length.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0033-usb-isp1760-fix-qtd-fill-length.patch new file mode 100644 index 0000000..ee913bc --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0033-usb-isp1760-fix-qtd-fill-length.patch @@ -0,0 +1,38 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From fc22c0fb49d7858b3c7b8bd2a8e041263280e230 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Wed, 25 Aug 2021 00:10:02 +0100 +Subject: [PATCH 20/23] usb: isp1760: fix qtd fill length + +When trying to send bulks bigger than the biggest block size +we need to split them over several qtd. Fix this limiting the +maximum qtd size to largest block size. + +Signed-off-by: Rui Miguel Silva +--- + drivers/usb/isp1760/isp1760-hcd.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index b3a55c5d2155..fba21122bb00 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -1829,9 +1829,11 @@ static void packetize_urb(struct usb_hcd *hcd, + goto cleanup; + + if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1]) +- len = mem->blocks_size[ISP176x_BLOCK_NUM - 1]; ++ this_qtd_len = mem->blocks_size[ISP176x_BLOCK_NUM - 1]; ++ else ++ this_qtd_len = len; + +- this_qtd_len = qtd_fill(qtd, buf, len); ++ this_qtd_len = qtd_fill(qtd, buf, this_qtd_len); + list_add_tail(&qtd->qtd_list, head); + + len -= this_qtd_len; +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0034-usb-isp1760-write-to-status-and-address-register.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0034-usb-isp1760-write-to-status-and-address-register.patch new file mode 100644 index 0000000..7b8d845 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0034-usb-isp1760-write-to-status-and-address-register.patch @@ -0,0 +1,90 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From a5dca0d8c66fb40ef372b596cbcfad45112fa050 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Tue, 24 Aug 2021 09:37:27 +0100 +Subject: [PATCH 21/23] usb: isp1760: write to status and address register + +We were already writing directly the port status register to +trigger changes in isp1763. The same is needed in other IP +from the family, including also to setup the read address +before reading from device. + +Signed-off-by: Rui Miguel Silva +--- + drivers/usb/isp1760/isp1760-hcd.c | 23 +++++++++++------------ + 1 file changed, 11 insertions(+), 12 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +index fba21122bb00..79d571f1429b 100644 +--- a/drivers/usb/isp1760/isp1760-hcd.c ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -182,7 +182,7 @@ struct urb_listitem { + struct urb *urb; + }; + +-static const u32 isp1763_hc_portsc1_fields[] = { ++static const u32 isp176x_hc_portsc1_fields[] = { + [PORT_OWNER] = BIT(13), + [PORT_POWER] = BIT(12), + [PORT_LSTATUS] = BIT(10), +@@ -205,27 +205,28 @@ static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field) + } + + /* +- * We need, in isp1763, to write directly the values to the portsc1 ++ * We need, in isp176x, to write directly the values to the portsc1 + * register so it will make the other values to trigger. + */ + static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field, + u32 val) + { +- u32 bit = isp1763_hc_portsc1_fields[field]; +- u32 port_status = readl(priv->base + ISP1763_HC_PORTSC1); ++ u32 bit = isp176x_hc_portsc1_fields[field]; ++ u16 portsc1_reg = priv->is_isp1763 ? ISP1763_HC_PORTSC1 : ++ ISP176x_HC_PORTSC1; ++ u32 port_status = readl(priv->base + portsc1_reg); + + if (val) +- writel(port_status | bit, priv->base + ISP1763_HC_PORTSC1); ++ writel(port_status | bit, priv->base + portsc1_reg); + else +- writel(port_status & ~bit, priv->base + ISP1763_HC_PORTSC1); ++ writel(port_status & ~bit, priv->base + portsc1_reg); + } + + static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val) + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); + +- if (unlikely(priv->is_isp1763 && +- (field >= PORT_OWNER && field <= PORT_CONNECT))) ++ if (unlikely((field >= PORT_OWNER && field <= PORT_CONNECT))) + return isp1760_hcd_portsc1_set_clear(priv, field, val); + + isp1760_field_write(priv->fields, field, val); +@@ -367,8 +368,7 @@ static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst, + { + struct isp1760_hcd *priv = hcd_to_priv(hcd); + +- isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); +- isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); ++ isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset); + ndelay(100); + + bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes); +@@ -496,8 +496,7 @@ static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, + u16 src_offset = ptd_offset + slot * sizeof(*ptd); + struct isp1760_hcd *priv = hcd_to_priv(hcd); + +- isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); +- isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); ++ isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset); + ndelay(90); + + bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd, +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0035-usb-isp1760-use-the-right-irq-status-bit.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0035-usb-isp1760-use-the-right-irq-status-bit.patch new file mode 100644 index 0000000..8faad8f --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0035-usb-isp1760-use-the-right-irq-status-bit.patch @@ -0,0 +1,72 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From 8f238acb1dada56dc6898a6ce2551feed0e6e8c2 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Wed, 25 Aug 2021 00:36:55 +0100 +Subject: [PATCH 22/23] usb: isp1760: use the right irq status bit + +Instead of using the fields enum values to check interrupts +trigged, use the correct bit values. + +Signed-off-by: Rui Miguel Silva +--- + drivers/usb/isp1760/isp1760-udc.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-udc.c b/drivers/usb/isp1760/isp1760-udc.c +index a78da59d6417..5cafd23345ca 100644 +--- a/drivers/usb/isp1760/isp1760-udc.c ++++ b/drivers/usb/isp1760/isp1760-udc.c +@@ -1363,7 +1363,7 @@ static irqreturn_t isp1760_udc_irq(int irq, void *dev) + + status = isp1760_udc_irq_get_status(udc); + +- if (status & DC_IEVBUS) { ++ if (status & ISP176x_DC_IEVBUS) { + dev_dbg(udc->isp->dev, "%s(VBUS)\n", __func__); + /* The VBUS interrupt is only triggered when VBUS appears. */ + spin_lock(&udc->lock); +@@ -1371,7 +1371,7 @@ static irqreturn_t isp1760_udc_irq(int irq, void *dev) + spin_unlock(&udc->lock); + } + +- if (status & DC_IEBRST) { ++ if (status & ISP176x_DC_IEBRST) { + dev_dbg(udc->isp->dev, "%s(BRST)\n", __func__); + + isp1760_udc_reset(udc); +@@ -1391,18 +1391,18 @@ static irqreturn_t isp1760_udc_irq(int irq, void *dev) + } + } + +- if (status & DC_IEP0SETUP) { ++ if (status & ISP176x_DC_IEP0SETUP) { + dev_dbg(udc->isp->dev, "%s(EP0SETUP)\n", __func__); + + isp1760_ep0_setup(udc); + } + +- if (status & DC_IERESM) { ++ if (status & ISP176x_DC_IERESM) { + dev_dbg(udc->isp->dev, "%s(RESM)\n", __func__); + isp1760_udc_resume(udc); + } + +- if (status & DC_IESUSP) { ++ if (status & ISP176x_DC_IESUSP) { + dev_dbg(udc->isp->dev, "%s(SUSP)\n", __func__); + + spin_lock(&udc->lock); +@@ -1413,7 +1413,7 @@ static irqreturn_t isp1760_udc_irq(int irq, void *dev) + spin_unlock(&udc->lock); + } + +- if (status & DC_IEHS_STA) { ++ if (status & ISP176x_DC_IEHS_STA) { + dev_dbg(udc->isp->dev, "%s(HS_STA)\n", __func__); + udc->gadget.speed = USB_SPEED_HIGH; + } +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0036-usb-isp1760-otg-control-register-access.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0036-usb-isp1760-otg-control-register-access.patch new file mode 100644 index 0000000..e7ddc89 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0036-usb-isp1760-otg-control-register-access.patch @@ -0,0 +1,134 @@ +Upstream-Status: Accepted [merged with kernel 5.14.9] +Signed-off-by: Arpita S.K + +From 6ccc598ff04d7f7babcbf194b5a0913119abb702 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Fri, 27 Aug 2021 08:22:26 +0100 +Subject: [PATCH 23/23] usb: isp1760: otg control register access + +The set/clear of the otg control values is done writing to +two different 16bit registers, however we setup the regmap +width for isp1760/61 to 32bit value bits. + +So, just access the clear register address (0x376)as the high +part of the otg control register set (0x374), and write the +values in one go to make sure they get clear/set. + +Signed-off-by: Rui Miguel Silva +--- + drivers/usb/isp1760/isp1760-core.c | 50 ++++++++++++++++-------------- + drivers/usb/isp1760/isp1760-regs.h | 16 ++++++++++ + 2 files changed, 42 insertions(+), 24 deletions(-) + +diff --git a/drivers/usb/isp1760/isp1760-core.c b/drivers/usb/isp1760/isp1760-core.c +index cb70f9d63cdd..d1d9a7d5da17 100644 +--- a/drivers/usb/isp1760/isp1760-core.c ++++ b/drivers/usb/isp1760/isp1760-core.c +@@ -30,6 +30,7 @@ static int isp1760_init_core(struct isp1760_device *isp) + { + struct isp1760_hcd *hcd = &isp->hcd; + struct isp1760_udc *udc = &isp->udc; ++ u32 otg_ctrl; + + /* Low-level chip reset */ + if (isp->rst_gpio) { +@@ -83,16 +84,17 @@ static int isp1760_init_core(struct isp1760_device *isp) + * + * TODO: Really support OTG. For now we configure port 1 in device mode + */ +- if (((isp->devflags & ISP1760_FLAG_ISP1761) || +- (isp->devflags & ISP1760_FLAG_ISP1763)) && +- (isp->devflags & ISP1760_FLAG_PERIPHERAL_EN)) { +- isp1760_field_set(hcd->fields, HW_DM_PULLDOWN); +- isp1760_field_set(hcd->fields, HW_DP_PULLDOWN); +- isp1760_field_set(hcd->fields, HW_OTG_DISABLE); +- } else { +- isp1760_field_set(hcd->fields, HW_SW_SEL_HC_DC); +- isp1760_field_set(hcd->fields, HW_VBUS_DRV); +- isp1760_field_set(hcd->fields, HW_SEL_CP_EXT); ++ if (isp->devflags & ISP1760_FLAG_ISP1761) { ++ if (isp->devflags & ISP1760_FLAG_PERIPHERAL_EN) { ++ otg_ctrl = (ISP176x_HW_DM_PULLDOWN_CLEAR | ++ ISP176x_HW_DP_PULLDOWN_CLEAR | ++ ISP176x_HW_OTG_DISABLE); ++ } else { ++ otg_ctrl = (ISP176x_HW_SW_SEL_HC_DC_CLEAR | ++ ISP176x_HW_VBUS_DRV | ++ ISP176x_HW_SEL_CP_EXT); ++ } ++ isp1760_reg_write(hcd->regs, ISP176x_HC_OTG_CTRL, otg_ctrl); + } + + dev_info(isp->dev, "%s bus width: %u, oc: %s\n", +@@ -235,20 +237,20 @@ static const struct reg_field isp1760_hc_reg_fields[] = { + [HC_ISO_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_ISO_IRQ_MASK_AND, 0, 31), + [HC_INT_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_INT_IRQ_MASK_AND, 0, 31), + [HC_ATL_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_ATL_IRQ_MASK_AND, 0, 31), +- [HW_OTG_DISABLE] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 10, 10), +- [HW_SW_SEL_HC_DC] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 7, 7), +- [HW_VBUS_DRV] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 4, 4), +- [HW_SEL_CP_EXT] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 3, 3), +- [HW_DM_PULLDOWN] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 2, 2), +- [HW_DP_PULLDOWN] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 1, 1), +- [HW_DP_PULLUP] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 0, 0), +- [HW_OTG_DISABLE_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 10, 10), +- [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 7, 7), +- [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 4, 4), +- [HW_SEL_CP_EXT_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 3, 3), +- [HW_DM_PULLDOWN_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 2, 2), +- [HW_DP_PULLDOWN_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 1, 1), +- [HW_DP_PULLUP_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 0, 0), ++ [HW_OTG_DISABLE_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL, 26, 26), ++ [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL, 23, 23), ++ [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL, 20, 20), ++ [HW_SEL_CP_EXT_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL, 19, 19), ++ [HW_DM_PULLDOWN_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL, 18, 18), ++ [HW_DP_PULLDOWN_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL, 17, 17), ++ [HW_DP_PULLUP_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL, 16, 16), ++ [HW_OTG_DISABLE] = REG_FIELD(ISP176x_HC_OTG_CTRL, 10, 10), ++ [HW_SW_SEL_HC_DC] = REG_FIELD(ISP176x_HC_OTG_CTRL, 7, 7), ++ [HW_VBUS_DRV] = REG_FIELD(ISP176x_HC_OTG_CTRL, 4, 4), ++ [HW_SEL_CP_EXT] = REG_FIELD(ISP176x_HC_OTG_CTRL, 3, 3), ++ [HW_DM_PULLDOWN] = REG_FIELD(ISP176x_HC_OTG_CTRL, 2, 2), ++ [HW_DP_PULLDOWN] = REG_FIELD(ISP176x_HC_OTG_CTRL, 1, 1), ++ [HW_DP_PULLUP] = REG_FIELD(ISP176x_HC_OTG_CTRL, 0, 0), + }; + + static const struct reg_field isp1763_hc_reg_fields[] = { +diff --git a/drivers/usb/isp1760/isp1760-regs.h b/drivers/usb/isp1760/isp1760-regs.h +index 94ea60c20b2a..3a6751197e97 100644 +--- a/drivers/usb/isp1760/isp1760-regs.h ++++ b/drivers/usb/isp1760/isp1760-regs.h +@@ -61,6 +61,7 @@ + #define ISP176x_HC_INT_IRQ_MASK_AND 0x328 + #define ISP176x_HC_ATL_IRQ_MASK_AND 0x32c + ++#define ISP176x_HC_OTG_CTRL 0x374 + #define ISP176x_HC_OTG_CTRL_SET 0x374 + #define ISP176x_HC_OTG_CTRL_CLEAR 0x376 + +@@ -179,6 +180,21 @@ enum isp176x_host_controller_fields { + #define ISP176x_DC_IESUSP BIT(3) + #define ISP176x_DC_IEBRST BIT(0) + ++#define ISP176x_HW_OTG_DISABLE_CLEAR BIT(26) ++#define ISP176x_HW_SW_SEL_HC_DC_CLEAR BIT(23) ++#define ISP176x_HW_VBUS_DRV_CLEAR BIT(20) ++#define ISP176x_HW_SEL_CP_EXT_CLEAR BIT(19) ++#define ISP176x_HW_DM_PULLDOWN_CLEAR BIT(18) ++#define ISP176x_HW_DP_PULLDOWN_CLEAR BIT(17) ++#define ISP176x_HW_DP_PULLUP_CLEAR BIT(16) ++#define ISP176x_HW_OTG_DISABLE BIT(10) ++#define ISP176x_HW_SW_SEL_HC_DC BIT(7) ++#define ISP176x_HW_VBUS_DRV BIT(4) ++#define ISP176x_HW_SEL_CP_EXT BIT(3) ++#define ISP176x_HW_DM_PULLDOWN BIT(2) ++#define ISP176x_HW_DP_PULLDOWN BIT(1) ++#define ISP176x_HW_DP_PULLUP BIT(0) ++ + #define ISP176x_DC_ENDPTYP_ISOC 0x01 + #define ISP176x_DC_ENDPTYP_BULK 0x02 + #define ISP176x_DC_ENDPTYP_INTERRUPT 0x03 +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/corstone1000_kernel_debug.cfg b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/corstone1000_kernel_debug.cfg new file mode 100644 index 0000000..aad9e93 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/corstone1000_kernel_debug.cfg @@ -0,0 +1,3 @@ +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO_DWARF4=y diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig new file mode 100644 index 0000000..cc7dc3e --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig @@ -0,0 +1,88 @@ +CONFIG_LOCALVERSION="-yocto-standard" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_LOG_BUF_SHIFT=13 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=13 +CONFIG_RELAY=y +CONFIG_BOOT_CONFIG=y +CONFIG_ARCH_VEXPRESS=y +CONFIG_CMDLINE="console=ttyAMA0 loglevel=9" +# CONFIG_SUSPEND is not set +# CONFIG_STACKPROTECTOR is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_SCHED=y +CONFIG_DEVTMPFS=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_UAS=y +CONFIG_USB_ISP1760=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PL031=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_CONFIGFS_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_LIBCRC32C=y +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_DEBUG_FS=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_STACKTRACE=y diff --git a/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc b/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc index 57a2f5b..a32c393 100644 --- a/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc +++ b/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc @@ -81,6 +81,74 @@ KERNEL_FEATURES:append:corstone700-mps3 = " \ '', \ d)}" +# +# Corstone1000 KMACHINE +# +FILESEXTRAPATHS:prepend:corstone1000 := "${ARMBSPFILESPATHS}" +COMPATIBLE_MACHINE:corstone1000 = "${MACHINE}" +KCONFIG_MODE:corstone1000 = "--alldefconfig" +KMACHINE:corstone1000 = "corstone1000" +LINUX_KERNEL_TYPE:corstone1000 = "standard" +#disabling the rootfs cpio file compression so it is not compressed twice when bundled with the kernel +KERNEL_EXTRA_ARGS:corstone1000 += "CONFIG_INITRAMFS_COMPRESSION_NONE=y" +SRC_URI:append:corstone1000 = " \ + file://0001-usb-isp1760-fix-strict-typechecking.patch \ + file://0002-usb-isp1760-move-to-regmap-for-register-access.patch \ + file://0003-usb-isp1760-use-relaxed-primitives.patch \ + file://0004-usb-isp1760-remove-platform-data-struct-and-code.patch \ + file://0005-usb-isp1760-hcd-refactor-mempool-config-and-setup.patch \ + file://0006-usb-isp1760-use-dr_mode-binding.patch \ + file://0007-usb-isp1760-add-support-for-isp1763.patch \ + file://0008-dt-bindings-usb-nxp-isp1760-add-bindings.patch \ + file://0009-usb-isp1763-add-peripheral-mode.patch \ + file://0022-usb-isp1760-isp1760-udc-Provide-missing-description-.patch \ + file://0023-usb-isp1760-Fix-meaningless-check-in-isp1763_run.patch \ + file://0024-usb-isp1760-remove-debug-message-as-error.patch \ + file://0025-usb-isp1760-do-not-sleep-in-field-register-poll.patch \ + file://0026-usb-isp1760-rework-cache-initialization-error-handli.patch \ + file://0027-usb-isp1760-ignore-return-value-for-bus-change-patte.patch \ + file://0028-usb-isp1760-check-maxpacketsize-before-using-it.patch \ + file://0029-usb-isp1760-do-not-reset-retval.patch \ + file://0030-usb-isp1760-do-not-shift-in-uninitialized-slot.patch \ + file://0031-usb-isp1760-clean-never-read-udc_enabled-warning.patch \ + file://0032-usb-isp1760-fix-memory-pool-initialization.patch \ + file://0033-usb-isp1760-fix-qtd-fill-length.patch \ + file://0034-usb-isp1760-write-to-status-and-address-register.patch \ + file://0035-usb-isp1760-use-the-right-irq-status-bit.patch \ + file://0036-usb-isp1760-otg-control-register-access.patch \ + file://defconfig \ + " + +SRC_URI:append:corstone1000 = " ${@bb.utils.contains('MACHINE_FEATURES', \ + 'corstone1000_kernel_debug', \ + 'file://corstone1000_kernel_debug.cfg', \ + '', \ + d)}" + +# Default kernel features not needed for corstone1000 +# otherwise the extra kernel modules will increase the rootfs size +# corstone1000 has limited flash memory constraints +KERNEL_EXTRA_FEATURES:corstone1000 = "" +KERNEL_FEATURES:corstone1000 = "" +# No need to include the kernel image in the rootfs +# So, let's delete the package doing that and uninstalling the initial +# kernel binary. +# The kernel binary needed is the initramfs bundle + +FILES:kernel-image-image:corstone1000="" + +# Uninstalling the initial kernel binary + +do_install:append:corstone1000() { + if [ -e "${D}/${KERNEL_IMAGEDEST}/$imageType-${KERNEL_VERSION}" ]; then + rm ${D}/${KERNEL_IMAGEDEST}/$imageType-${KERNEL_VERSION} + fi + + if [ -e "${D}/${KERNEL_IMAGEDEST}/$imageType" ]; then + rm ${D}/${KERNEL_IMAGEDEST}/$imageType + fi +} + # # FVP BASE KMACHINE # From patchwork Tue Nov 23 15:59:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2124DC433FE for ; Tue, 23 Nov 2021 15:59:57 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.13295.1637683196155812685 for ; Tue, 23 Nov 2021 07:59:56 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D1C4D1FB; Tue, 23 Nov 2021 07:59:55 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EC8473F5A1; Tue, 23 Nov 2021 07:59:53 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Drew Reed , Abdellatif El Khlifi , Satish Kumar , Jon Mason Subject: [PATCH][honister 08/19] arm-bsp/trusted-firmware-m: introducing corstone1000 FVP machine Date: Tue, 23 Nov 2021 15:59:15 +0000 Message-Id: <20211123155926.31743-9-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 15:59:57 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2437 From: Vishnu Banavath Enables trusted-firmware-m on the corstone1000-fvp machine. Change-Id: Id38d565e1f2b2d0a80cbd58740e64f56ddbc4cee Signed-off-by: Drew Reed Signed-off-by: Abdellatif El Khlifi Signed-off-by: Arpita S.K Signed-off-by: Satish Kumar Signed-off-by: Jon Mason --- .../conf/machine/include/corstone1000.inc | 5 ++++ .../trusted-firmware-m-corstone1000.inc | 30 +++++++++++++++++++ .../trusted-firmware-m_%.bbappend | 6 ++++ 3 files changed, 41 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m_%.bbappend diff --git a/meta-arm-bsp/conf/machine/include/corstone1000.inc b/meta-arm-bsp/conf/machine/include/corstone1000.inc index 3d06143..b38e35a 100644 --- a/meta-arm-bsp/conf/machine/include/corstone1000.inc +++ b/meta-arm-bsp/conf/machine/include/corstone1000.inc @@ -2,6 +2,11 @@ require conf/machine/include/arm/armv8a/tune-cortexa35.inc MACHINEOVERRIDES =. "corstone1000:" +# TF-M +PREFERRED_VERSION_trusted-firmware-m ?= "1.4%" +TFM_PLATFORM = "arm/corstone1000" +EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-m" + # Linux kernel PREFERRED_PROVIDER_virtual/kernel:forcevariable = "linux-yocto" PREFERRED_VERSION_linux-yocto = "5.10%" diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc new file mode 100644 index 0000000..1967365 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc @@ -0,0 +1,30 @@ +# Corstone1000 machines specific TFM support + +COMPATIBLE_MACHINE = "(corstone1000)" + +TFM_DEBUG = "1" + +PACKAGECONFIG[test-secure] = "-DTEST_S=OFF,-DTEST_S=OFF" +PACKAGECONFIG[test-nonsecure] = "-DTEST_NS=OFF,-DTEST_NS=OFF" + +INSANE_SKIP:${PN} = "arch" + +## Default is the FVP ## +TFM_PLATFORM_IS_FVP ?= "TRUE" +EXTRA_OECMAKE += "-DPLATFORM_IS_FVP=${TFM_PLATFORM_IS_FVP}" + +SRCREV_tfm = "ccd82e35f539c0d7261b2935d6d30c550cfc6736" + +SRCREV_FORMAT = "tfm_mcuboot_tfm-tests_mbedtls" + +do_install() { + if [ ! -d "${B}/install/outputs/ARM/CORSTONE1000" ] + then + bbfatal "'${B}/install/outputs/ARM/CORSTONE1000' output folder not found!" + fi + + install -D -p -m 0644 ${B}/install/outputs/ARM/CORSTONE1000/tfm_s_signed.bin ${D}/firmware/tfm_s_signed.bin + install -D -p -m 0644 ${B}/install/outputs/ARM/CORSTONE1000/bl2_signed.bin ${D}/firmware/bl2_signed.bin + install -D -p -m 0644 ${B}/install/outputs/ARM/CORSTONE1000/bl1.bin ${D}/firmware/bl1.bin + +} diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m_%.bbappend b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m_%.bbappend new file mode 100644 index 0000000..da70bc7 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m_%.bbappend @@ -0,0 +1,6 @@ +# Machine specific configurations + +MACHINE_TFM_REQUIRE ?= "" +MACHINE_TFM_REQUIRE:corstone1000 = "trusted-firmware-m-corstone1000.inc" + +require ${MACHINE_TFM_REQUIRE} From patchwork Tue Nov 23 15:59:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 395A3C433FE for ; Tue, 23 Nov 2021 16:00:00 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.13255.1637683198601641667 for ; Tue, 23 Nov 2021 07:59:58 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3ACC51FB; Tue, 23 Nov 2021 07:59:58 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 385B33F5A1; Tue, 23 Nov 2021 07:59:55 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Rui Miguel Silva , Abdellatif El Khlifi , Jon Mason Subject: [PATCH][honister 09/19] arm-bsp/u-boot: introducing corstone1000 FVP machine Date: Tue, 23 Nov 2021 15:59:16 +0000 Message-Id: <20211123155926.31743-10-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:00 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2438 From: Rui Miguel Silva Add support for corstone1000-fvp machine which have a cortex-a35 aarch64, this will boot till u-boot prompt. Remove kernel devicetree configuration and add the devicetree here and enable it in the diphda defconfig. Adds the build options required to support an RTC emulator which in turn is required to support the UEFI functions GetTime() and SetTime(). Change-Id: I0d66ece1193494bd2f59a9800d802dff1c4a0db6 Signed-off-by: Arpita S.K Signed-off-by: Rui Miguel Silva Signed-off-by: Abdellatif El Khlifi Signed-off-by: Vishnu Banavath Signed-off-by: Jon Mason --- .../conf/machine/include/corstone1000.inc | 12 + .../0001-arm-add-corstone1000-platform.patch | 330 ++ ...e1000-enable-devicetree-in-defconfig.patch | 59 + ...3-usb-common-move-urb-code-to-common.patch | 508 +++ .../0004-usb-add-isp1760-family-driver.patch | 3797 +++++++++++++++++ ...one1000-enable-isp1763-and-usb-stack.patch | 92 + ...-corstone1000-enable-support-for-FVP.patch | 240 ++ ...-sharing-PSCI-DTS-node-between-FVP-a.patch | 34 + ...rm-corstone1000-Emulated-RTC-Support.patch | 32 + ...-corstone1000-execute-uboot-from-DDR.patch | 31 + .../recipes-bsp/u-boot/u-boot_%.bbappend | 21 + 11 files changed, 5156 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0001-arm-add-corstone1000-platform.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0002-arm-corstone1000-enable-devicetree-in-defconfig.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0003-usb-common-move-urb-code-to-common.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0004-usb-add-isp1760-family-driver.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0005-corstone1000-enable-isp1763-and-usb-stack.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0006-corstone1000-enable-support-for-FVP.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0007-arm-corstone1000-sharing-PSCI-DTS-node-between-FVP-a.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0008-arm-corstone1000-Emulated-RTC-Support.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0009-arm-corstone1000-execute-uboot-from-DDR.patch diff --git a/meta-arm-bsp/conf/machine/include/corstone1000.inc b/meta-arm-bsp/conf/machine/include/corstone1000.inc index b38e35a..2c2293f 100644 --- a/meta-arm-bsp/conf/machine/include/corstone1000.inc +++ b/meta-arm-bsp/conf/machine/include/corstone1000.inc @@ -7,6 +7,18 @@ PREFERRED_VERSION_trusted-firmware-m ?= "1.4%" TFM_PLATFORM = "arm/corstone1000" EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-m" +# u-boot +PREFERRED_VERSION_u-boot ?= "2021.07" +EXTRA_IMAGEDEPENDS += "u-boot" + +UBOOT_CONFIG ??= "EFI" +UBOOT_CONFIG[EFI] = "corstone1000_defconfig" +UBOOT_ENTRYPOINT = "0x80000000" +UBOOT_LOADADDRESS = "0x80000000" +UBOOT_BOOTARGS = "earlycon=pl011,0x1a510000 console=ttyAMA0 loglevel=9" +UBOOT_ARCH = "arm" +UBOOT_EXTLINUX = "0" + # Linux kernel PREFERRED_PROVIDER_virtual/kernel:forcevariable = "linux-yocto" PREFERRED_VERSION_linux-yocto = "5.10%" diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0001-arm-add-corstone1000-platform.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0001-arm-add-corstone1000-platform.patch new file mode 100644 index 0000000..1fe0fb8 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0001-arm-add-corstone1000-platform.patch @@ -0,0 +1,330 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From 3feb071c77bb6297165c7b671b5c92d6ba306238 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Fri, 4 Jun 2021 10:58:24 +0100 +Subject: [PATCH 01/16] arm: add corstone1000 platform + +Add support for new corstone1000 platform. + +Signed-off-by: Rui Miguel Silva +Signed-off-by: Rui Miguel Silva +--- + arch/arm/Kconfig | 9 ++++ + board/armltd/corstone1000/Kconfig | 12 +++++ + board/armltd/corstone1000/MAINTAINERS | 6 +++ + board/armltd/corstone1000/Makefile | 7 +++ + board/armltd/corstone1000/corstone1000.c | 92 +++++++++++++++++++++++++++++++++ + configs/corstone1000_defconfig | 39 ++++++++++++++ + include/configs/corstone1000.h | 80 ++++++++++++++++++++++++++++ + 7 files changed, 245 insertions(+) + create mode 100644 board/armltd/corstone1000/Kconfig + create mode 100644 board/armltd/corstone1000/MAINTAINERS + create mode 100644 board/armltd/corstone1000/Makefile + create mode 100644 board/armltd/corstone1000/corstone1000.c + create mode 100644 configs/corstone1000_defconfig + create mode 100644 include/configs/corstone1000.h + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 0448787b8b..25d2a707be 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1173,6 +1173,13 @@ config TARGET_VEXPRESS64_JUNO + select USB + select DM_USB + ++config TARGET_CORSTONE1000 ++ bool "Support Corstone1000 Platform" ++ select ARM64 ++ select PL01X_SERIAL ++ select DM ++ select OF_BOARD ++ + config TARGET_TOTAL_COMPUTE + bool "Support Total Compute Platform" + select ARM64 +@@ -1985,6 +1992,8 @@ source "arch/arm/mach-nexell/Kconfig" + + source "board/armltd/total_compute/Kconfig" + ++source "board/armltd/corstone1000/Kconfig" ++ + source "board/bosch/shc/Kconfig" + source "board/bosch/guardian/Kconfig" + source "board/CarMediaLab/flea3/Kconfig" +diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig +new file mode 100644 +index 000000000000..90e6b7af59cb +--- /dev/null ++++ b/board/armltd/corstone1000/Kconfig +@@ -0,0 +1,12 @@ ++if TARGET_CORSTONE1000 ++ ++config SYS_BOARD ++ default "corstone1000" ++ ++config SYS_VENDOR ++ default "armltd" ++ ++config SYS_CONFIG_NAME ++ default "corstone1000" ++ ++endif +diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS +new file mode 100644 +index 000000000000..601cff17b666 +--- /dev/null ++++ b/board/armltd/corstone1000/MAINTAINERS +@@ -0,0 +1,6 @@ ++CORSTONE1000 BOARD ++M: Rui Miguel Silva ++S: Maintained ++F: board/armltd/corstone1000/ ++F: include/configs/corstone1000.h ++F: configs/corstone1000_defconfig +diff --git a/board/armltd/corstone1000/Makefile b/board/armltd/corstone1000/Makefile +new file mode 100644 +index 000000000000..7bad6f57f1ce +--- /dev/null ++++ b/board/armltd/corstone1000/Makefile +@@ -0,0 +1,7 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# (C) Copyright 2021 Arm Limited ++# (C) Copyright 2021 Linaro ++# Rui Miguel Silva ++ ++obj-y := corstone1000.o +diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c +new file mode 100644 +index 000000000000..fe986ceba1c5 +--- /dev/null ++++ b/board/armltd/corstone1000/corstone1000.c +@@ -0,0 +1,92 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2021 ARM Limited ++ * (C) Copyright 2021 Linaro ++ * Rui Miguel Silva ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++static const struct pl01x_serial_plat serial_plat = { ++ .base = V2M_UART0, ++ .type = TYPE_PL011, ++ .clock = CONFIG_PL011_CLOCK, ++}; ++ ++U_BOOT_DRVINFO(corstone1000_serials) = { ++ .name = "serial_pl01x", ++ .plat = &serial_plat, ++}; ++ ++static struct mm_region corstone1000_mem_map[] = { ++ { ++ /* CVM */ ++ .virt = 0x02000000UL, ++ .phys = 0x02000000UL, ++ .size = 0x02000000UL, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | ++ PTE_BLOCK_INNER_SHARE ++ }, { ++ /* QSPI */ ++ .virt = 0x08000000UL, ++ .phys = 0x08000000UL, ++ .size = 0x08000000UL, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | ++ PTE_BLOCK_INNER_SHARE ++ }, { ++ /* Host Peripherals */ ++ .virt = 0x1A000000UL, ++ .phys = 0x1A000000UL, ++ .size = 0x26000000UL, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | ++ PTE_BLOCK_NON_SHARE | ++ PTE_BLOCK_PXN | PTE_BLOCK_UXN ++ }, { ++ /* OCVM */ ++ .virt = 0x80000000UL, ++ .phys = 0x80000000UL, ++ .size = 0x80000000UL, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | ++ PTE_BLOCK_INNER_SHARE ++ }, { ++ /* List terminator */ ++ 0, ++ } ++}; ++ ++struct mm_region *mem_map = corstone1000_mem_map; ++ ++int board_init(void) ++{ ++ return 0; ++} ++ ++int dram_init(void) ++{ ++ gd->ram_size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++int dram_init_banksize(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++#ifdef PHYS_SDRAM_2 ++ gd->bd->bi_dram[1].start = PHYS_SDRAM_2; ++ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; ++#endif ++ ++ ++ return 0; ++} ++ ++void reset_cpu(ulong addr) ++{ ++} +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +new file mode 100644 +index 000000000000..47d4bf3771e0 +--- /dev/null ++++ b/configs/corstone1000_defconfig +@@ -0,0 +1,39 @@ ++CONFIG_ARM=y ++CONFIG_ARM64=y ++CONFIG_TARGET_CORSTONE1000=y ++CONFIG_SYS_TEXT_BASE=0x02100000 ++CONFIG_SYS_MALLOC_F_LEN=0x2000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_IDENT_STRING=" corstone1000 aarch64 " ++CONFIG_BOOTDELAY=3 ++CONFIG_OF_BOARD=y ++CONFIG_USE_BOOTARGS=y ++CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9" ++# CONFIG_DISPLAY_CPUINFO is not set ++# CONFIG_DISPLAY_BOARDINFO is not set ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="corstone1000# " ++# CONFIG_CMD_CONSOLE is not set ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_BOOTM=y ++# CONFIG_CMD_XIMG is not set ++# CONFIG_CMD_EDITENV is not set ++# CONFIG_CMD_ENV_EXISTS is not set ++# CONFIG_CMD_ARMFLASH=y ++# CONFIG_CMD_LOADS is not set ++# CONFIG_CMD_ITEST is not set ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_DHCP=y ++# CONFIG_CMD_NFS is not set ++CONFIG_CMD_MII=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_CACHE=y ++CONFIG_FIT=y ++# CONFIG_CMD_MISC is not set ++CONFIG_CMD_FAT=y ++CONFIG_DM=y ++# CONFIG_MMC is not set ++# CONFIG_MTD_NOR_FLASH=y ++CONFIG_DM_ETH=y ++CONFIG_DM_SERIAL=y ++CONFIG_OF_LIBFDT=y +diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h +new file mode 100644 +index 000000000000..c8e630c5d857 +--- /dev/null ++++ b/include/configs/corstone1000.h +@@ -0,0 +1,80 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * (C) Copyright 2020 ARM Limited ++ * (C) Copyright 2020 Linaro ++ * Rui Miguel Silva ++ * Abdellatif El Khlifi ++ * ++ * Configuration for Corstone1000. Parts were derived from other ARM ++ * configurations. ++ */ ++ ++#ifndef __CORSTONE1000_H ++#define __CORSTONE1000_H ++ ++#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) ++#define CONFIG_SKIP_LOWLEVEL_INIT ++ ++#define CONFIG_SYS_HZ 1000 ++ ++#define V2M_SRAM0 0x02000000 ++#define V2M_QSPI 0x08000000 ++ ++#define V2M_DEBUG 0x10000000 ++#define V2M_BASE_PERIPH 0x1A000000 ++ ++#define V2M_BASE 0x80000000 ++ ++#define V2M_PERIPH_OFFSET(x) (x << 16) ++ ++#define V2M_SYSID (V2M_BASE_PERIPH) ++#define V2M_SYSCTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1)) ++ ++#define V2M_COUNTER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32)) ++#define V2M_COUNTER_READ (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33)) ++ ++#define V2M_TIMER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34)) ++#define V2M_TIMER_BASE0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35)) ++ ++#define V2M_UART0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(81)) ++#define V2M_UART1 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(82)) ++ ++#define CONFIG_PL011_CLOCK 50000000 ++ ++/* Physical Memory Map */ ++#define PHYS_SDRAM_1 (V2M_BASE) ++#define PHYS_SDRAM_2 (V2M_QSPI) ++ ++/* Top 16MB reserved for secure world use (maybe not needed) */ ++#define DRAM_SEC_SIZE 0x01000000 ++#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE ++ ++#define PHYS_SDRAM_2_SIZE 0x02000000 ++ ++/* Size of malloc() pool */ ++#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) ++ ++/* Miscellaneous configurable options */ ++#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) ++ ++#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 ++ ++/* Monitor Command Prompt */ ++#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ ++#define CONFIG_SYS_MAXARGS 64 /* max command args */ ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "fdt_addr=0x08330000\0" \ ++ "fdt_addr_r=0x82000000\0" \ ++ "kernel_addr=0x08430000\0" \ ++ "kernel_addr_r=0x82100000\0" \ ++ "fdt_high=0xffffffff\0" ++ ++#define CONFIG_BOOTCOMMAND \ ++ "echo Copying devicetree to memory ... ;" \ ++ "cp.b $fdt_addr $fdt_addr_r 0x100000;" \ ++ "echo Copying Kernel to memory ... ;" \ ++ "cp.b $kernel_addr $kernel_addr_r 0xa00000;" \ ++ "bootm $kernel_addr_r - $fdt_addr_r; " ++ ++#endif +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0002-arm-corstone1000-enable-devicetree-in-defconfig.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0002-arm-corstone1000-enable-devicetree-in-defconfig.patch new file mode 100644 index 0000000..df8c6ed --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0002-arm-corstone1000-enable-devicetree-in-defconfig.patch @@ -0,0 +1,59 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From 1a034bd9397f96939d58a86e9cf8cd9c206db647 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Tue, 22 Jun 2021 17:00:24 +0100 +Subject: [PATCH 02/16] arm: corstone1000: enable devicetree in defconfig + +Add support and setup the default device tree for corstone1000. + +Signed-off-by: Rui Miguel Silva +Signed-off-by: Rui Miguel Silva +--- + configs/corstone1000_defconfig | 3 ++- + include/configs/corstone1000.h | 10 +++------- + 2 files changed, 5 insertions(+), 8 deletions(-) + +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index bc983e6555..54c746d829 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -6,7 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_IDENT_STRING=" corstone1000 aarch64 " + CONFIG_BOOTDELAY=3 +-CONFIG_OF_BOARD=y ++CONFIG_OF_CONTROL=y ++CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3" + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9" + # CONFIG_DISPLAY_CPUINFO is not set +diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h +index 1fe909463f..389ac45a58 100644 +--- a/include/configs/corstone1000.h ++++ b/include/configs/corstone1000.h +@@ -64,17 +64,13 @@ + #define CONFIG_SYS_MAXARGS 64 /* max command args */ + + #define CONFIG_EXTRA_ENV_SETTINGS \ +- "fdt_addr=0x08330000\0" \ + "fdt_addr_r=0x82000000\0" \ +- "kernel_addr=0x08430000\0" \ ++ "kernel_addr=0x08330000\0" \ + "kernel_addr_r=0x82100000\0" \ + "fdt_high=0xffffffff\0" + + #define CONFIG_BOOTCOMMAND \ +- "echo Copying devicetree to memory ... ;" \ +- "cp.b $fdt_addr $fdt_addr_r 0x100000;" \ + "echo Copying Kernel to memory ... ;" \ +- "cp.b $kernel_addr $kernel_addr_r 0xa00000;" \ +- "bootm $kernel_addr_r - $fdt_addr_r; " +- ++ "cp.b $kernel_addr $kernel_addr_r 0xc00000;" \ ++ "booti $kernel_addr_r - $fdtcontroladdr; " + #endif +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0003-usb-common-move-urb-code-to-common.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0003-usb-common-move-urb-code-to-common.patch new file mode 100644 index 0000000..1a73d52 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0003-usb-common-move-urb-code-to-common.patch @@ -0,0 +1,508 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From 84b3b8f2443d0b4f6ac8ef95c941b27d734afbde Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Mon, 28 Jun 2021 23:20:55 +0100 +Subject: [PATCH 03/16] usb: common: move urb code to common + +Move urb code from musb only use to a more common scope, so other +drivers in the future can use the handling of urb in usb. + +Signed-off-by: Rui Miguel Silva +--- + drivers/usb/common/Makefile | 2 + + drivers/usb/common/usb_urb.c | 160 ++++++++++++++++++ + drivers/usb/host/r8a66597-hcd.c | 30 +--- + drivers/usb/musb-new/musb_core.c | 2 +- + drivers/usb/musb-new/musb_host.c | 2 +- + drivers/usb/musb-new/musb_host.h | 2 +- + drivers/usb/musb-new/musb_uboot.c | 38 +---- + drivers/usb/musb-new/musb_uboot.h | 2 +- + .../linux/usb/usb_urb_compat.h | 52 ++++-- + include/usb_defs.h | 32 ++++ + 10 files changed, 240 insertions(+), 82 deletions(-) + create mode 100644 drivers/usb/common/usb_urb.c + rename drivers/usb/musb-new/usb-compat.h => include/linux/usb/usb_urb_compat.h (57%) + +diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile +index 3bedbf213f..dc05cb0a50 100644 +--- a/drivers/usb/common/Makefile ++++ b/drivers/usb/common/Makefile +@@ -4,5 +4,7 @@ + # + + obj-$(CONFIG_$(SPL_)DM_USB) += common.o ++obj-$(CONFIG_USB_MUSB_HCD) += usb_urb.o ++obj-$(CONFIG_USB_MUSB_UDC) += usb_urb.o + obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o fsl-errata.o + obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o fsl-errata.o +diff --git a/drivers/usb/common/usb_urb.c b/drivers/usb/common/usb_urb.c +new file mode 100644 +index 0000000000..be3b6b9f32 +--- /dev/null ++++ b/drivers/usb/common/usb_urb.c +@@ -0,0 +1,160 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Common code for usb urb handling, based on the musb-new code ++ * ++ * Copyright 2021 Linaro, Rui Miguel Silva ++ * ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#if CONFIG_IS_ENABLED(DM_USB) ++struct usb_device *usb_dev_get_parent(struct usb_device *udev) ++{ ++ struct udevice *parent = udev->dev->parent; ++ ++ /* ++ * When called from usb-uclass.c: usb_scan_device() udev->dev points ++ * to the parent udevice, not the actual udevice belonging to the ++ * udev as the device is not instantiated yet. ++ * ++ * If dev is an usb-bus, then we are called from usb_scan_device() for ++ * an usb-device plugged directly into the root port, return NULL. ++ */ ++ if (device_get_uclass_id(udev->dev) == UCLASS_USB) ++ return NULL; ++ ++ /* ++ * If these 2 are not the same we are being called from ++ * usb_scan_device() and udev itself is the parent. ++ */ ++ if (dev_get_parent_priv(udev->dev) != udev) ++ return udev; ++ ++ /* We are being called normally, use the parent pointer */ ++ if (device_get_uclass_id(parent) == UCLASS_USB_HUB) ++ return dev_get_parent_priv(parent); ++ ++ return NULL; ++} ++#else ++struct usb_device *usb_dev_get_parent(struct usb_device *udev) ++{ ++ return udev->parent; ++} ++#endif ++ ++static void usb_urb_complete(struct urb *urb) ++{ ++ urb->dev->status &= ~USB_ST_NOT_PROC; ++ urb->dev->act_len = urb->actual_length; ++ ++ if (urb->status == -EINPROGRESS) ++ urb->status = 0; ++} ++ ++void usb_urb_fill(struct urb *urb, struct usb_host_endpoint *hep, ++ struct usb_device *dev, int endpoint_type, ++ unsigned long pipe, void *buffer, int len, ++ struct devrequest *setup, int interval) ++{ ++ int epnum = usb_pipeendpoint(pipe); ++ int is_in = usb_pipein(pipe); ++ u16 maxpacketsize = is_in ? dev->epmaxpacketin[epnum] : ++ dev->epmaxpacketout[epnum]; ++ ++ memset(urb, 0, sizeof(struct urb)); ++ memset(hep, 0, sizeof(struct usb_host_endpoint)); ++ INIT_LIST_HEAD(&hep->urb_list); ++ INIT_LIST_HEAD(&urb->urb_list); ++ urb->ep = hep; ++ urb->complete = usb_urb_complete; ++ urb->status = -EINPROGRESS; ++ urb->dev = dev; ++ urb->pipe = pipe; ++ urb->transfer_buffer = buffer; ++ urb->transfer_dma = (unsigned long)buffer; ++ urb->transfer_buffer_length = len; ++ urb->setup_packet = (unsigned char *)setup; ++ ++ urb->ep->desc.wMaxPacketSize = __cpu_to_le16(maxpacketsize); ++ urb->ep->desc.bmAttributes = endpoint_type; ++ urb->ep->desc.bEndpointAddress = ((is_in ? USB_DIR_IN : USB_DIR_OUT) | ++ epnum); ++ urb->ep->desc.bInterval = interval; ++} ++ ++int usb_urb_submit(struct usb_hcd *hcd, struct urb *urb) ++{ ++ const struct usb_urb_ops *ops = hcd->urb_ops; ++ unsigned long timeout; ++ int ret; ++ ++ if (!ops) ++ return -EINVAL; ++ ++ ret = ops->urb_enqueue(hcd, urb, 0); ++ if (ret < 0) { ++ printf("Failed to enqueue URB to controller\n"); ++ return ret; ++ } ++ ++ timeout = get_timer(0) + USB_TIMEOUT_MS(urb->pipe); ++ do { ++ if (ctrlc()) ++ return -EIO; ++ ops->isr(0, hcd); ++ } while (urb->status == -EINPROGRESS && get_timer(0) < timeout); ++ ++ if (urb->status == -EINPROGRESS) ++ ops->urb_dequeue(hcd, urb, -ETIME); ++ ++ return urb->status; ++} ++ ++int usb_urb_submit_control(struct usb_hcd *hcd, struct urb *urb, ++ struct usb_host_endpoint *hep, ++ struct usb_device *dev, unsigned long pipe, ++ void *buffer, int len, struct devrequest *setup, ++ int interval, enum usb_device_speed speed) ++{ ++ const struct usb_urb_ops *ops = hcd->urb_ops; ++ ++ usb_urb_fill(urb, hep, dev, USB_ENDPOINT_XFER_CONTROL, pipe, buffer, ++ len, setup, 0); ++ ++ /* Fix speed for non hub-attached devices */ ++ if (!usb_dev_get_parent(dev)) { ++ dev->speed = speed; ++ if (ops->hub_control) ++ return ops->hub_control(hcd, dev, pipe, buffer, len, ++ setup); ++ } ++ ++ return usb_urb_submit(hcd, urb); ++} ++ ++int usb_urb_submit_bulk(struct usb_hcd *hcd, struct urb *urb, ++ struct usb_host_endpoint *hep, struct usb_device *dev, ++ unsigned long pipe, void *buffer, int len) ++{ ++ usb_urb_fill(urb, hep, dev, USB_ENDPOINT_XFER_BULK, pipe, buffer, len, ++ NULL, 0); ++ ++ return usb_urb_submit(hcd, urb); ++} ++ ++int usb_urb_submit_irq(struct usb_hcd *hcd, struct urb *urb, ++ struct usb_host_endpoint *hep, struct usb_device *dev, ++ unsigned long pipe, void *buffer, int len, int interval) ++{ ++ usb_urb_fill(urb, hep, dev, USB_ENDPOINT_XFER_INT, pipe, buffer, len, ++ NULL, interval); ++ ++ return usb_urb_submit(hcd, urb); ++} +diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c +index f1fc93f3d4..3ccbc16da3 100644 +--- a/drivers/usb/host/r8a66597-hcd.c ++++ b/drivers/usb/host/r8a66597-hcd.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + + #include "r8a66597.h" +@@ -24,35 +25,6 @@ + #define R8A66597_DPRINT(...) + #endif + +-static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev) +-{ +- struct udevice *parent = udev->dev->parent; +- +- /* +- * When called from usb-uclass.c: usb_scan_device() udev->dev points +- * to the parent udevice, not the actual udevice belonging to the +- * udev as the device is not instantiated yet. +- * +- * If dev is an usb-bus, then we are called from usb_scan_device() for +- * an usb-device plugged directly into the root port, return NULL. +- */ +- if (device_get_uclass_id(udev->dev) == UCLASS_USB) +- return NULL; +- +- /* +- * If these 2 are not the same we are being called from +- * usb_scan_device() and udev itself is the parent. +- */ +- if (dev_get_parent_priv(udev->dev) != udev) +- return udev; +- +- /* We are being called normally, use the parent pointer */ +- if (device_get_uclass_id(parent) == UCLASS_USB_HUB) +- return dev_get_parent_priv(parent); +- +- return NULL; +-} +- + static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport) + { + struct usb_device *parent = usb_dev_get_parent(dev); +diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c +index 22811a5efb..d1d4ee2da3 100644 +--- a/drivers/usb/musb-new/musb_core.c ++++ b/drivers/usb/musb-new/musb_core.c +@@ -89,9 +89,9 @@ + #include + #include + #include ++#include + #include + #include "linux-compat.h" +-#include "usb-compat.h" + #endif + + #include "musb_core.h" +diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c +index acb2d40f3b..e5905d90d6 100644 +--- a/drivers/usb/musb-new/musb_host.c ++++ b/drivers/usb/musb-new/musb_host.c +@@ -26,8 +26,8 @@ + #include + #include + #include ++#include + #include "linux-compat.h" +-#include "usb-compat.h" + #endif + + #include "musb_core.h" +diff --git a/drivers/usb/musb-new/musb_host.h b/drivers/usb/musb-new/musb_host.h +index afc8fa35a7..5a604bdb0c 100644 +--- a/drivers/usb/musb-new/musb_host.h ++++ b/drivers/usb/musb-new/musb_host.h +@@ -10,7 +10,7 @@ + #ifndef _MUSB_HOST_H + #define _MUSB_HOST_H + #ifdef __UBOOT__ +-#include "usb-compat.h" ++#include + #endif + + static inline struct usb_hcd *musb_to_hcd(struct musb *musb) +diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c +index 8ac2f0a78a..85794356b0 100644 +--- a/drivers/usb/musb-new/musb_uboot.c ++++ b/drivers/usb/musb-new/musb_uboot.c +@@ -8,10 +8,10 @@ + #include + #include + #include ++#include + + #include + #include "linux-compat.h" +-#include "usb-compat.h" + #include "musb_core.h" + #include "musb_host.h" + #include "musb_gadget.h" +@@ -453,39 +453,3 @@ struct musb *musb_register(struct musb_hdrc_platform_data *plat, void *bdata, + + return *musbp; + } +- +-#if CONFIG_IS_ENABLED(DM_USB) +-struct usb_device *usb_dev_get_parent(struct usb_device *udev) +-{ +- struct udevice *parent = udev->dev->parent; +- +- /* +- * When called from usb-uclass.c: usb_scan_device() udev->dev points +- * to the parent udevice, not the actual udevice belonging to the +- * udev as the device is not instantiated yet. +- * +- * If dev is an usb-bus, then we are called from usb_scan_device() for +- * an usb-device plugged directly into the root port, return NULL. +- */ +- if (device_get_uclass_id(udev->dev) == UCLASS_USB) +- return NULL; +- +- /* +- * If these 2 are not the same we are being called from +- * usb_scan_device() and udev itself is the parent. +- */ +- if (dev_get_parent_priv(udev->dev) != udev) +- return udev; +- +- /* We are being called normally, use the parent pointer */ +- if (device_get_uclass_id(parent) == UCLASS_USB_HUB) +- return dev_get_parent_priv(parent); +- +- return NULL; +-} +-#else +-struct usb_device *usb_dev_get_parent(struct usb_device *udev) +-{ +- return udev->parent; +-} +-#endif +diff --git a/drivers/usb/musb-new/musb_uboot.h b/drivers/usb/musb-new/musb_uboot.h +index 18282efccc..6b162f03b1 100644 +--- a/drivers/usb/musb-new/musb_uboot.h ++++ b/drivers/usb/musb-new/musb_uboot.h +@@ -8,8 +8,8 @@ + #define __MUSB_UBOOT_H__ + + #include ++#include + #include "linux-compat.h" +-#include "usb-compat.h" + #include "musb_core.h" + + struct musb_host_data { +diff --git a/drivers/usb/musb-new/usb-compat.h b/include/linux/usb/usb_urb_compat.h +similarity index 57% +rename from drivers/usb/musb-new/usb-compat.h +rename to include/linux/usb/usb_urb_compat.h +index 1c66c4fe36..438e70b56a 100644 +--- a/drivers/usb/musb-new/usb-compat.h ++++ b/include/linux/usb/usb_urb_compat.h +@@ -1,16 +1,31 @@ +-#ifndef __USB_COMPAT_H__ +-#define __USB_COMPAT_H__ ++#ifndef __USB_URB_COMPAT_H__ ++#define __USB_URB_COMPAT_H__ + +-#include "usb.h" ++#include ++#include + + struct udevice; ++struct urb; ++struct usb_hcd; ++ ++ ++struct usb_urb_ops { ++ int (*urb_enqueue)(struct usb_hcd *hcd, struct urb *urb, ++ gfp_t mem_flags); ++ int (*urb_dequeue)(struct usb_hcd *hcd, struct urb *urb, int status); ++ int (*hub_control)(struct usb_hcd *hcd, struct usb_device *dev, ++ unsigned long pipe, void *buffer, int len, ++ struct devrequest *setup); ++ irqreturn_t (*isr)(int irq, void *priv); ++}; + + struct usb_hcd { + void *hcd_priv; ++ const struct usb_urb_ops *urb_ops; + }; + + struct usb_host_endpoint { +- struct usb_endpoint_descriptor desc; ++ struct usb_endpoint_descriptor desc; + struct list_head urb_list; + void *hcpriv; + }; +@@ -23,8 +38,6 @@ struct usb_host_endpoint { + #define URB_SHORT_NOT_OK 0x0001 /* report short reads as errors */ + #define URB_ZERO_PACKET 0x0040 /* Finish bulk OUT with short packet */ + +-struct urb; +- + typedef void (*usb_complete_t)(struct urb *); + + struct urb { +@@ -68,12 +81,27 @@ static inline int usb_hcd_unmap_urb_for_dma(struct usb_hcd *hcd, + return 0; + } + +-/** +- * usb_dev_get_parent() - Get the parent of a USB device +- * +- * @udev: USB struct containing information about the device +- * @return associated device for which udev == dev_get_parent_priv(dev) +- */ + struct usb_device *usb_dev_get_parent(struct usb_device *udev); + ++int usb_urb_submit_control(struct usb_hcd *hcd, struct urb *urb, ++ struct usb_host_endpoint *hep, ++ struct usb_device *dev, unsigned long pipe, ++ void *buffer, int len, struct devrequest *setup, ++ int interval, enum usb_device_speed speed); ++ ++int usb_urb_submit_bulk(struct usb_hcd *hcd, struct urb *urb, ++ struct usb_host_endpoint *hep, struct usb_device *dev, ++ unsigned long pipe, void *buffer, int len); ++ ++int usb_urb_submit_irq(struct usb_hcd *hcd, struct urb *urb, ++ struct usb_host_endpoint *hep, struct usb_device *dev, ++ unsigned long pipe, void *buffer, int len, int interval); ++ ++void usb_urb_fill(struct urb *urb, struct usb_host_endpoint *hep, ++ struct usb_device *dev, int endpoint_type, ++ unsigned long pipe, void *buffer, int len, ++ struct devrequest *setup, int interval); ++ ++int usb_urb_submit(struct usb_hcd *hcd, struct urb *urb); ++ + #endif /* __USB_COMPAT_H__ */ +diff --git a/include/usb_defs.h b/include/usb_defs.h +index 6dd2c997f9..ec00161710 100644 +--- a/include/usb_defs.h ++++ b/include/usb_defs.h +@@ -81,6 +81,32 @@ + #define EndpointOutRequest \ + ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + ++/* class requests from the USB 2.0 hub spec, table 11-15 */ ++#define HUB_CLASS_REQ(dir, type, request) ((((dir) | (type)) << 8) | (request)) ++/* GetBusState and SetHubDescriptor are optional, omitted */ ++#define ClearHubFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_HUB, \ ++ USB_REQ_CLEAR_FEATURE) ++#define ClearPortFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, \ ++ USB_REQ_CLEAR_FEATURE) ++#define GetHubDescriptor HUB_CLASS_REQ(USB_DIR_IN, USB_RT_HUB, \ ++ USB_REQ_GET_DESCRIPTOR) ++#define GetHubStatus HUB_CLASS_REQ(USB_DIR_IN, USB_RT_HUB, \ ++ USB_REQ_GET_STATUS) ++#define GetPortStatus HUB_CLASS_REQ(USB_DIR_IN, USB_RT_PORT, \ ++ USB_REQ_GET_STATUS) ++#define SetHubFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_HUB, \ ++ USB_REQ_SET_FEATURE) ++#define SetPortFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, \ ++ USB_REQ_SET_FEATURE) ++#define ClearTTBuffer HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, \ ++ HUB_CLEAR_TT_BUFFER) ++#define ResetTT HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, \ ++ HUB_RESET_TT) ++#define GetTTState HUB_CLASS_REQ(USB_DIR_IN, USB_RT_PORT, \ ++ HUB_GET_TT_STATE) ++#define StopTT HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, \ ++ HUB_STOP_TT) ++ + /* Descriptor types */ + #define USB_DT_DEVICE 0x01 + #define USB_DT_CONFIG 0x02 +@@ -289,10 +315,16 @@ + #define USB_SS_PORT_STAT_C_CONFIG_ERROR 0x0080 + + /* wHubCharacteristics (masks) */ ++#define HUB_CHAR_COMMON_OCPM 0x0000 /* All ports Over-Current reporting */ ++#define HUB_CHAR_INDV_PORT_LPSM 0x0001 /* per-port power control */ ++#define HUB_CHAR_NO_LPSM 0x0002 /* no power switching */ + #define HUB_CHAR_LPSM 0x0003 + #define HUB_CHAR_COMPOUND 0x0004 ++#define HUB_CHAR_INDV_PORT_OCPM 0x0008 /* per-port Over-current reporting */ ++#define HUB_CHAR_NO_OCPM 0x0010 /* No Over-current Protection support */ + #define HUB_CHAR_OCPM 0x0018 + #define HUB_CHAR_TTTT 0x0060 /* TT Think Time mask */ ++#define HUB_CHAR_PORTIND 0x0080 /* per-port indicators (LEDs) */ + + /* + * Hub Status & Hub Change bit masks +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0004-usb-add-isp1760-family-driver.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0004-usb-add-isp1760-family-driver.patch new file mode 100644 index 0000000..9d75164 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0004-usb-add-isp1760-family-driver.patch @@ -0,0 +1,3797 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From a007c43ab35e81bb609e9af28ebe4f73ee196823 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Mon, 28 Jun 2021 23:31:25 +0100 +Subject: [PATCH 04/16] usb: add isp1760 family driver + +ISP1760/61/63 are a family of usb controllers, blah, blah, more info +here. + +Signed-off-by: Rui Miguel Silva +--- + Makefile | 1 + + drivers/usb/Kconfig | 2 + + drivers/usb/common/Makefile | 1 + + drivers/usb/isp1760/Kconfig | 13 + + drivers/usb/isp1760/Makefile | 6 + + drivers/usb/isp1760/isp1760-core.c | 378 ++++ + drivers/usb/isp1760/isp1760-core.h | 96 + + drivers/usb/isp1760/isp1760-hcd.c | 2574 +++++++++++++++++++++++++++ + drivers/usb/isp1760/isp1760-hcd.h | 82 + + drivers/usb/isp1760/isp1760-if.c | 127 ++ + drivers/usb/isp1760/isp1760-regs.h | 292 +++ + drivers/usb/isp1760/isp1760-uboot.c | 64 + + drivers/usb/isp1760/isp1760-uboot.h | 27 + + 13 files changed, 3663 insertions(+) + create mode 100644 drivers/usb/isp1760/Kconfig + create mode 100644 drivers/usb/isp1760/Makefile + create mode 100644 drivers/usb/isp1760/isp1760-core.c + create mode 100644 drivers/usb/isp1760/isp1760-core.h + create mode 100644 drivers/usb/isp1760/isp1760-hcd.c + create mode 100644 drivers/usb/isp1760/isp1760-hcd.h + create mode 100644 drivers/usb/isp1760/isp1760-if.c + create mode 100644 drivers/usb/isp1760/isp1760-regs.h + create mode 100644 drivers/usb/isp1760/isp1760-uboot.c + create mode 100644 drivers/usb/isp1760/isp1760-uboot.h + +diff --git a/Makefile b/Makefile +index 2ab9c53192..570e35d566 100644 +--- a/Makefile ++++ b/Makefile +@@ -828,6 +828,7 @@ libs-y += drivers/usb/host/ + libs-y += drivers/usb/mtu3/ + libs-y += drivers/usb/musb/ + libs-y += drivers/usb/musb-new/ ++libs-y += drivers/usb/isp1760/ + libs-y += drivers/usb/phy/ + libs-y += drivers/usb/ulpi/ + libs-y += cmd/ +diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig +index f6975730bf..6f7b4d4db4 100644 +--- a/drivers/usb/Kconfig ++++ b/drivers/usb/Kconfig +@@ -78,6 +78,8 @@ source "drivers/usb/musb/Kconfig" + + source "drivers/usb/musb-new/Kconfig" + ++source "drivers/usb/isp1760/Kconfig" ++ + source "drivers/usb/emul/Kconfig" + + source "drivers/usb/phy/Kconfig" +diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile +index dc05cb0a50..f08b064d24 100644 +--- a/drivers/usb/common/Makefile ++++ b/drivers/usb/common/Makefile +@@ -4,6 +4,7 @@ + # + + obj-$(CONFIG_$(SPL_)DM_USB) += common.o ++obj-$(CONFIG_USB_ISP1760) += usb_urb.o + obj-$(CONFIG_USB_MUSB_HCD) += usb_urb.o + obj-$(CONFIG_USB_MUSB_UDC) += usb_urb.o + obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o fsl-errata.o +diff --git a/drivers/usb/isp1760/Kconfig b/drivers/usb/isp1760/Kconfig +new file mode 100644 +index 0000000000..e76fb5e4cc +--- /dev/null ++++ b/drivers/usb/isp1760/Kconfig +@@ -0,0 +1,13 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++config USB_ISP1760 ++ tristate "NXP ISP 1760/1761/1763 support" ++ depends on DM_USB ++ select USB_HOST ++ help ++ Say Y or M here if your system as an ISP1760/1761/1763 USB host ++ controller. ++ ++ This USB controller is usually attached to a non-DMA-Master ++ capable bus. ++ +diff --git a/drivers/usb/isp1760/Makefile b/drivers/usb/isp1760/Makefile +new file mode 100644 +index 0000000000..2c809c01b1 +--- /dev/null ++++ b/drivers/usb/isp1760/Makefile +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0 ++isp1760-y := isp1760-core.o isp1760-if.o isp1760-uboot.o isp1760-hcd.o ++ ++#isp1760-hcd.o ++ ++obj-$(CONFIG_USB_ISP1760) += isp1760.o +diff --git a/drivers/usb/isp1760/isp1760-core.c b/drivers/usb/isp1760/isp1760-core.c +new file mode 100644 +index 0000000000..3080595549 +--- /dev/null ++++ b/drivers/usb/isp1760/isp1760-core.c +@@ -0,0 +1,378 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Driver for the NXP ISP1760 chip ++ * ++ * Copyright 2021 Linaro, Rui Miguel Silva ++ * ++ * This is based on linux kernel driver, original developed: ++ * Copyright 2014 Laurent Pinchart ++ * Copyright 2007 Sebastian Siewior ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "isp1760-core.h" ++#include "isp1760-hcd.h" ++#include "isp1760-regs.h" ++ ++#define msleep(a) udelay(a * 1000) ++ ++static int isp1760_init_core(struct isp1760_device *isp) ++{ ++ struct isp1760_hcd *hcd = &isp->hcd; ++ ++ /* ++ * Reset the host controller, including the CPU interface ++ * configuration. ++ */ ++ isp1760_field_set(hcd->fields, SW_RESET_RESET_ALL); ++ msleep(100); ++ ++ /* Setup HW Mode Control: This assumes a level active-low interrupt */ ++ if ((isp->devflags & ISP1760_FLAG_ANALOG_OC) && hcd->is_isp1763) ++ return -EINVAL; ++ ++ if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_16) ++ isp1760_field_clear(hcd->fields, HW_DATA_BUS_WIDTH); ++ if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_8) ++ isp1760_field_set(hcd->fields, HW_DATA_BUS_WIDTH); ++ if (isp->devflags & ISP1760_FLAG_ANALOG_OC) ++ isp1760_field_set(hcd->fields, HW_ANA_DIGI_OC); ++ if (isp->devflags & ISP1760_FLAG_DACK_POL_HIGH) ++ isp1760_field_set(hcd->fields, HW_DACK_POL_HIGH); ++ if (isp->devflags & ISP1760_FLAG_DREQ_POL_HIGH) ++ isp1760_field_set(hcd->fields, HW_DREQ_POL_HIGH); ++ if (isp->devflags & ISP1760_FLAG_INTR_POL_HIGH) ++ isp1760_field_set(hcd->fields, HW_INTR_HIGH_ACT); ++ if (isp->devflags & ISP1760_FLAG_INTR_EDGE_TRIG) ++ isp1760_field_set(hcd->fields, HW_INTR_EDGE_TRIG); ++ ++ /* ++ * The ISP1761 has a dedicated DC IRQ line but supports sharing the HC ++ * IRQ line for both the host and device controllers. Hardcode IRQ ++ * sharing for now and disable the DC interrupts globally to avoid ++ * spurious interrupts during HCD registration. ++ */ ++ if (isp->devflags & ISP1760_FLAG_ISP1761) { ++ isp1760_reg_write(hcd->regs, ISP176x_DC_MODE, 0); ++ isp1760_field_set(hcd->fields, HW_COMN_IRQ); ++ } ++ ++ /* ++ * PORT 1 Control register of the ISP1760 is the OTG control register ++ * on ISP1761. ++ * ++ * TODO: Really support OTG. For now we configure port 1 in device mode ++ */ ++ if (((isp->devflags & ISP1760_FLAG_ISP1761) || ++ (isp->devflags & ISP1760_FLAG_ISP1763)) && ++ (isp->devflags & ISP1760_FLAG_PERIPHERAL_EN)) { ++ isp1760_field_set(hcd->fields, HW_DM_PULLDOWN); ++ isp1760_field_set(hcd->fields, HW_DP_PULLDOWN); ++ isp1760_field_set(hcd->fields, HW_OTG_DISABLE); ++ } else { ++ isp1760_field_set(hcd->fields, HW_SW_SEL_HC_DC); ++ isp1760_field_set(hcd->fields, HW_VBUS_DRV); ++ isp1760_field_set(hcd->fields, HW_SEL_CP_EXT); ++ } ++ ++ printf( "%s bus width: %u, oc: %s\n", ++ hcd->is_isp1763 ? "isp1763" : "isp1760", ++ isp->devflags & ISP1760_FLAG_BUS_WIDTH_8 ? 8 : ++ isp->devflags & ISP1760_FLAG_BUS_WIDTH_16 ? 16 : 32, ++ hcd->is_isp1763 ? "not available" : ++ isp->devflags & ISP1760_FLAG_ANALOG_OC ? "analog" : "digital"); ++ ++ return 0; ++} ++ ++void isp1760_set_pullup(struct isp1760_device *isp, bool enable) ++{ ++ struct isp1760_hcd *hcd = &isp->hcd; ++ ++ if (enable) ++ isp1760_field_set(hcd->fields, HW_DP_PULLUP); ++ else ++ isp1760_field_set(hcd->fields, HW_DP_PULLUP_CLEAR); ++} ++ ++/* ++ * ISP1760/61: ++ * ++ * 60kb divided in: ++ * - 32 blocks @ 256 bytes ++ * - 20 blocks @ 1024 bytes ++ * - 4 blocks @ 8192 bytes ++ */ ++static const struct isp1760_memory_layout isp176x_memory_conf = { ++ .blocks[0] = 32, ++ .blocks_size[0] = 256, ++ .blocks[1] = 20, ++ .blocks_size[1] = 1024, ++ .blocks[2] = 4, ++ .blocks_size[2] = 8192, ++ ++ .slot_num = 32, ++ .payload_blocks = 32 + 20 + 4, ++ .payload_area_size = 0xf000, ++}; ++ ++/* ++ * ISP1763: ++ * ++ * 20kb divided in: ++ * - 8 blocks @ 256 bytes ++ * - 2 blocks @ 1024 bytes ++ * - 4 blocks @ 4096 bytes ++ */ ++static const struct isp1760_memory_layout isp1763_memory_conf = { ++ .blocks[0] = 8, ++ .blocks_size[0] = 256, ++ .blocks[1] = 2, ++ .blocks_size[1] = 1024, ++ .blocks[2] = 4, ++ .blocks_size[2] = 4096, ++ ++ .slot_num = 16, ++ .payload_blocks = 8 + 2 + 4, ++ .payload_area_size = 0x5000, ++}; ++ ++static const struct regmap_config isp1760_hc_regmap_conf = { ++ .width = REGMAP_SIZE_16, ++}; ++ ++static const struct reg_field isp1760_hc_reg_fields[] = { ++ [HCS_PPC] = REG_FIELD(ISP176x_HC_HCSPARAMS, 4, 4), ++ [HCS_N_PORTS] = REG_FIELD(ISP176x_HC_HCSPARAMS, 0, 3), ++ [HCC_ISOC_CACHE] = REG_FIELD(ISP176x_HC_HCCPARAMS, 7, 7), ++ [HCC_ISOC_THRES] = REG_FIELD(ISP176x_HC_HCCPARAMS, 4, 6), ++ [CMD_LRESET] = REG_FIELD(ISP176x_HC_USBCMD, 7, 7), ++ [CMD_RESET] = REG_FIELD(ISP176x_HC_USBCMD, 1, 1), ++ [CMD_RUN] = REG_FIELD(ISP176x_HC_USBCMD, 0, 0), ++ [STS_PCD] = REG_FIELD(ISP176x_HC_USBSTS, 2, 2), ++ [HC_FRINDEX] = REG_FIELD(ISP176x_HC_FRINDEX, 0, 13), ++ [FLAG_CF] = REG_FIELD(ISP176x_HC_CONFIGFLAG, 0, 0), ++ [HC_ISO_PTD_DONEMAP] = REG_FIELD(ISP176x_HC_ISO_PTD_DONEMAP, 0, 31), ++ [HC_ISO_PTD_SKIPMAP] = REG_FIELD(ISP176x_HC_ISO_PTD_SKIPMAP, 0, 31), ++ [HC_ISO_PTD_LASTPTD] = REG_FIELD(ISP176x_HC_ISO_PTD_LASTPTD, 0, 31), ++ [HC_INT_PTD_DONEMAP] = REG_FIELD(ISP176x_HC_INT_PTD_DONEMAP, 0, 31), ++ [HC_INT_PTD_SKIPMAP] = REG_FIELD(ISP176x_HC_INT_PTD_SKIPMAP, 0, 31), ++ [HC_INT_PTD_LASTPTD] = REG_FIELD(ISP176x_HC_INT_PTD_LASTPTD, 0, 31), ++ [HC_ATL_PTD_DONEMAP] = REG_FIELD(ISP176x_HC_ATL_PTD_DONEMAP, 0, 31), ++ [HC_ATL_PTD_SKIPMAP] = REG_FIELD(ISP176x_HC_ATL_PTD_SKIPMAP, 0, 31), ++ [HC_ATL_PTD_LASTPTD] = REG_FIELD(ISP176x_HC_ATL_PTD_LASTPTD, 0, 31), ++ [PORT_OWNER] = REG_FIELD(ISP176x_HC_PORTSC1, 13, 13), ++ [PORT_POWER] = REG_FIELD(ISP176x_HC_PORTSC1, 12, 12), ++ [PORT_LSTATUS] = REG_FIELD(ISP176x_HC_PORTSC1, 10, 11), ++ [PORT_RESET] = REG_FIELD(ISP176x_HC_PORTSC1, 8, 8), ++ [PORT_SUSPEND] = REG_FIELD(ISP176x_HC_PORTSC1, 7, 7), ++ [PORT_RESUME] = REG_FIELD(ISP176x_HC_PORTSC1, 6, 6), ++ [PORT_PE] = REG_FIELD(ISP176x_HC_PORTSC1, 2, 2), ++ [PORT_CSC] = REG_FIELD(ISP176x_HC_PORTSC1, 1, 1), ++ [PORT_CONNECT] = REG_FIELD(ISP176x_HC_PORTSC1, 0, 0), ++ [ALL_ATX_RESET] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 31, 31), ++ [HW_ANA_DIGI_OC] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 15, 15), ++ [HW_COMN_IRQ] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 10, 10), ++ [HW_DATA_BUS_WIDTH] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 8, 8), ++ [HW_DACK_POL_HIGH] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 6, 6), ++ [HW_DREQ_POL_HIGH] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 5, 5), ++ [HW_INTR_HIGH_ACT] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 2, 2), ++ [HW_INTR_EDGE_TRIG] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 1, 1), ++ [HW_GLOBAL_INTR_EN] = REG_FIELD(ISP176x_HC_HW_MODE_CTRL, 0, 0), ++ [HC_CHIP_REV] = REG_FIELD(ISP176x_HC_CHIP_ID, 16, 31), ++ [HC_CHIP_ID_HIGH] = REG_FIELD(ISP176x_HC_CHIP_ID, 8, 15), ++ [HC_CHIP_ID_LOW] = REG_FIELD(ISP176x_HC_CHIP_ID, 0, 7), ++ [HC_SCRATCH] = REG_FIELD(ISP176x_HC_SCRATCH, 0, 31), ++ [SW_RESET_RESET_ALL] = REG_FIELD(ISP176x_HC_RESET, 0, 0), ++ [ISO_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 2, 2), ++ [INT_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 1, 1), ++ [ATL_BUF_FILL] = REG_FIELD(ISP176x_HC_BUFFER_STATUS, 0, 0), ++ [MEM_BANK_SEL] = REG_FIELD(ISP176x_HC_MEMORY, 16, 17), ++ [MEM_START_ADDR] = REG_FIELD(ISP176x_HC_MEMORY, 0, 15), ++ [HC_INTERRUPT] = REG_FIELD(ISP176x_HC_INTERRUPT, 0, 9), ++ [HC_ATL_IRQ_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 8, 8), ++ [HC_INT_IRQ_ENABLE] = REG_FIELD(ISP176x_HC_INTERRUPT_ENABLE, 7, 7), ++ [HC_ISO_IRQ_MASK_OR] = REG_FIELD(ISP176x_HC_ISO_IRQ_MASK_OR, 0, 31), ++ [HC_INT_IRQ_MASK_OR] = REG_FIELD(ISP176x_HC_INT_IRQ_MASK_OR, 0, 31), ++ [HC_ATL_IRQ_MASK_OR] = REG_FIELD(ISP176x_HC_ATL_IRQ_MASK_OR, 0, 31), ++ [HC_ISO_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_ISO_IRQ_MASK_AND, 0, 31), ++ [HC_INT_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_INT_IRQ_MASK_AND, 0, 31), ++ [HC_ATL_IRQ_MASK_AND] = REG_FIELD(ISP176x_HC_ATL_IRQ_MASK_AND, 0, 31), ++ [HW_OTG_DISABLE] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 10, 10), ++ [HW_SW_SEL_HC_DC] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 7, 7), ++ [HW_VBUS_DRV] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 4, 4), ++ [HW_SEL_CP_EXT] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 3, 3), ++ [HW_DM_PULLDOWN] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 2, 2), ++ [HW_DP_PULLDOWN] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 1, 1), ++ [HW_DP_PULLUP] = REG_FIELD(ISP176x_HC_OTG_CTRL_SET, 0, 0), ++ [HW_OTG_DISABLE_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 10, 10), ++ [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 7, 7), ++ [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 4, 4), ++ [HW_SEL_CP_EXT_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 3, 3), ++ [HW_DM_PULLDOWN_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 2, 2), ++ [HW_DP_PULLDOWN_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 1, 1), ++ [HW_DP_PULLUP_CLEAR] = REG_FIELD(ISP176x_HC_OTG_CTRL_CLEAR, 0, 0), ++}; ++ ++static const struct regmap_config isp1763_hc_regmap_conf = { ++ .width = REGMAP_SIZE_16, ++}; ++ ++static const struct reg_field isp1763_hc_reg_fields[] = { ++ [CMD_LRESET] = REG_FIELD(ISP1763_HC_USBCMD, 7, 7), ++ [CMD_RESET] = REG_FIELD(ISP1763_HC_USBCMD, 1, 1), ++ [CMD_RUN] = REG_FIELD(ISP1763_HC_USBCMD, 0, 0), ++ [STS_PCD] = REG_FIELD(ISP1763_HC_USBSTS, 2, 2), ++ [HC_FRINDEX] = REG_FIELD(ISP1763_HC_FRINDEX, 0, 13), ++ [FLAG_CF] = REG_FIELD(ISP1763_HC_CONFIGFLAG, 0, 0), ++ [HC_ISO_PTD_DONEMAP] = REG_FIELD(ISP1763_HC_ISO_PTD_DONEMAP, 0, 15), ++ [HC_ISO_PTD_SKIPMAP] = REG_FIELD(ISP1763_HC_ISO_PTD_SKIPMAP, 0, 15), ++ [HC_ISO_PTD_LASTPTD] = REG_FIELD(ISP1763_HC_ISO_PTD_LASTPTD, 0, 15), ++ [HC_INT_PTD_DONEMAP] = REG_FIELD(ISP1763_HC_INT_PTD_DONEMAP, 0, 15), ++ [HC_INT_PTD_SKIPMAP] = REG_FIELD(ISP1763_HC_INT_PTD_SKIPMAP, 0, 15), ++ [HC_INT_PTD_LASTPTD] = REG_FIELD(ISP1763_HC_INT_PTD_LASTPTD, 0, 15), ++ [HC_ATL_PTD_DONEMAP] = REG_FIELD(ISP1763_HC_ATL_PTD_DONEMAP, 0, 15), ++ [HC_ATL_PTD_SKIPMAP] = REG_FIELD(ISP1763_HC_ATL_PTD_SKIPMAP, 0, 15), ++ [HC_ATL_PTD_LASTPTD] = REG_FIELD(ISP1763_HC_ATL_PTD_LASTPTD, 0, 15), ++ [PORT_OWNER] = REG_FIELD(ISP1763_HC_PORTSC1, 13, 13), ++ [PORT_POWER] = REG_FIELD(ISP1763_HC_PORTSC1, 12, 12), ++ [PORT_LSTATUS] = REG_FIELD(ISP1763_HC_PORTSC1, 10, 11), ++ [PORT_RESET] = REG_FIELD(ISP1763_HC_PORTSC1, 8, 8), ++ [PORT_SUSPEND] = REG_FIELD(ISP1763_HC_PORTSC1, 7, 7), ++ [PORT_RESUME] = REG_FIELD(ISP1763_HC_PORTSC1, 6, 6), ++ [PORT_PE] = REG_FIELD(ISP1763_HC_PORTSC1, 2, 2), ++ [PORT_CSC] = REG_FIELD(ISP1763_HC_PORTSC1, 1, 1), ++ [PORT_CONNECT] = REG_FIELD(ISP1763_HC_PORTSC1, 0, 0), ++ [HW_DATA_BUS_WIDTH] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 4, 4), ++ [HW_DACK_POL_HIGH] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 6, 6), ++ [HW_DREQ_POL_HIGH] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 5, 5), ++ [HW_INTF_LOCK] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 3, 3), ++ [HW_INTR_HIGH_ACT] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 2, 2), ++ [HW_INTR_EDGE_TRIG] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 1, 1), ++ [HW_GLOBAL_INTR_EN] = REG_FIELD(ISP1763_HC_HW_MODE_CTRL, 0, 0), ++ [SW_RESET_RESET_ATX] = REG_FIELD(ISP1763_HC_RESET, 3, 3), ++ [SW_RESET_RESET_ALL] = REG_FIELD(ISP1763_HC_RESET, 0, 0), ++ [HC_CHIP_ID_HIGH] = REG_FIELD(ISP1763_HC_CHIP_ID, 0, 15), ++ [HC_CHIP_ID_LOW] = REG_FIELD(ISP1763_HC_CHIP_REV, 8, 15), ++ [HC_CHIP_REV] = REG_FIELD(ISP1763_HC_CHIP_REV, 0, 7), ++ [HC_SCRATCH] = REG_FIELD(ISP1763_HC_SCRATCH, 0, 15), ++ [ISO_BUF_FILL] = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 2, 2), ++ [INT_BUF_FILL] = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 1, 1), ++ [ATL_BUF_FILL] = REG_FIELD(ISP1763_HC_BUFFER_STATUS, 0, 0), ++ [MEM_START_ADDR] = REG_FIELD(ISP1763_HC_MEMORY, 0, 15), ++ [HC_DATA] = REG_FIELD(ISP1763_HC_DATA, 0, 15), ++ [HC_INTERRUPT] = REG_FIELD(ISP1763_HC_INTERRUPT, 0, 10), ++ [HC_ATL_IRQ_ENABLE] = REG_FIELD(ISP1763_HC_INTERRUPT_ENABLE, 8, 8), ++ [HC_INT_IRQ_ENABLE] = REG_FIELD(ISP1763_HC_INTERRUPT_ENABLE, 7, 7), ++ [HC_ISO_IRQ_MASK_OR] = REG_FIELD(ISP1763_HC_ISO_IRQ_MASK_OR, 0, 15), ++ [HC_INT_IRQ_MASK_OR] = REG_FIELD(ISP1763_HC_INT_IRQ_MASK_OR, 0, 15), ++ [HC_ATL_IRQ_MASK_OR] = REG_FIELD(ISP1763_HC_ATL_IRQ_MASK_OR, 0, 15), ++ [HC_ISO_IRQ_MASK_AND] = REG_FIELD(ISP1763_HC_ISO_IRQ_MASK_AND, 0, 15), ++ [HC_INT_IRQ_MASK_AND] = REG_FIELD(ISP1763_HC_INT_IRQ_MASK_AND, 0, 15), ++ [HC_ATL_IRQ_MASK_AND] = REG_FIELD(ISP1763_HC_ATL_IRQ_MASK_AND, 0, 15), ++ [HW_HC_2_DIS] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 15, 15), ++ [HW_OTG_DISABLE] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 10, 10), ++ [HW_SW_SEL_HC_DC] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 7, 7), ++ [HW_VBUS_DRV] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 4, 4), ++ [HW_SEL_CP_EXT] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 3, 3), ++ [HW_DM_PULLDOWN] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 2, 2), ++ [HW_DP_PULLDOWN] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 1, 1), ++ [HW_DP_PULLUP] = REG_FIELD(ISP1763_HC_OTG_CTRL_SET, 0, 0), ++ [HW_HC_2_DIS_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 15, 15), ++ [HW_OTG_DISABLE_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 10, 10), ++ [HW_SW_SEL_HC_DC_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 7, 7), ++ [HW_VBUS_DRV_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 4, 4), ++ [HW_SEL_CP_EXT_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 3, 3), ++ [HW_DM_PULLDOWN_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 2, 2), ++ [HW_DP_PULLDOWN_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 1, 1), ++ [HW_DP_PULLUP_CLEAR] = REG_FIELD(ISP1763_HC_OTG_CTRL_CLEAR, 0, 0), ++}; ++ ++int isp1760_register(struct isp1760_device *isp, struct resource *mem, int irq, ++ unsigned long irqflags) ++{ ++ const struct regmap_config *hc_regmap; ++ const struct reg_field *hc_reg_fields; ++ struct isp1760_hcd *hcd; ++ struct regmap_field *f; ++ unsigned int devflags; ++ struct udevice *dev; ++ int ret; ++ int i; ++ ++ hcd = &isp->hcd; ++ devflags = isp->devflags; ++ dev = isp->dev; ++ ++ hcd->is_isp1763 = !!(devflags & ISP1760_FLAG_ISP1763); ++ ++ if (!hcd->is_isp1763 && (devflags & ISP1760_FLAG_BUS_WIDTH_8)) { ++ dev_err(dev, "isp1760/61 do not support data width 8\n"); ++ return -EINVAL; ++ } ++ ++ if (hcd->is_isp1763) { ++ hc_regmap = &isp1763_hc_regmap_conf; ++ hc_reg_fields = &isp1763_hc_reg_fields[0]; ++ } else { ++ hc_regmap = &isp1760_hc_regmap_conf; ++ hc_reg_fields = &isp1760_hc_reg_fields[0]; ++ } ++ ++ hcd->base = devm_ioremap(dev, mem->start, resource_size(mem)); ++ if (IS_ERR(hcd->base)) ++ return PTR_ERR(hcd->base); ++ ++ hcd->regs = devm_regmap_init(dev, NULL, NULL, hc_regmap); ++ if (IS_ERR(hcd->regs)) ++ return PTR_ERR(hcd->regs); ++ ++ for (i = 0; i < HC_FIELD_MAX; i++) { ++ f = devm_regmap_field_alloc(dev, hcd->regs, hc_reg_fields[i]); ++ if (IS_ERR(f)) ++ return PTR_ERR(f); ++ ++ hcd->fields[i] = f; ++ } ++ ++ if (hcd->is_isp1763) ++ hcd->memory_layout = &isp1763_memory_conf; ++ else ++ hcd->memory_layout = &isp176x_memory_conf; ++ ++ ret = isp1760_init_core(isp); ++ if (ret < 0) ++ return ret; ++ ++ hcd->dev = dev; ++ ++ ret = isp1760_hcd_register(hcd, mem, irq, irqflags, dev); ++ if (ret < 0) ++ return ret; ++ ++ ret = isp1760_hcd_lowlevel_init(hcd); ++ if (ret < 0) ++ return ret; ++ ++ dev_set_drvdata(dev, isp); ++ ++ return 0; ++} ++ ++void isp1760_unregister(struct isp1760_device *isp) ++{ ++ isp1760_hcd_unregister(&isp->hcd); ++ ++ return; ++} +diff --git a/drivers/usb/isp1760/isp1760-core.h b/drivers/usb/isp1760/isp1760-core.h +new file mode 100644 +index 0000000000..0a60e30b5f +--- /dev/null ++++ b/drivers/usb/isp1760/isp1760-core.h +@@ -0,0 +1,96 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Driver for the NXP ISP1760 chip ++ * ++ * Copyright 2021 Linaro, Rui Miguel Silva ++ * Copyright 2014 Laurent Pinchart ++ * Copyright 2007 Sebastian Siewior ++ * ++ * Contacts: ++ * Sebastian Siewior ++ * Laurent Pinchart ++ * Rui Miguel Silva ++ */ ++ ++#ifndef _ISP1760_CORE_H_ ++#define _ISP1760_CORE_H_ ++ ++#include ++#include ++#include ++ ++#include "isp1760-hcd.h" ++ ++struct device; ++struct gpio_desc; ++ ++/* ++ * Device flags that can vary from board to board. All of these ++ * indicate the most "atypical" case, so that a devflags of 0 is ++ * a sane default configuration. ++ */ ++#define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */ ++#define ISP1760_FLAG_PERIPHERAL_EN 0x00000004 /* Port 1 supports Peripheral mode*/ ++#define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */ ++#define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */ ++#define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */ ++#define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */ ++#define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */ ++#define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */ ++#define ISP1760_FLAG_ISP1763 0x00000200 /* Chip is ISP1763 */ ++#define ISP1760_FLAG_BUS_WIDTH_8 0x00000400 /* 8-bit data bus width */ ++ ++struct isp1760_device { ++ struct udevice *dev; ++ ++ unsigned int devflags; ++ struct gpio_desc *rst_gpio; ++ ++ struct isp1760_hcd hcd; ++}; ++ ++int isp1760_register(struct isp1760_device *isp, struct resource *mem, int irq, ++ unsigned long irqflags); ++void isp1760_unregister(struct isp1760_device *isp); ++ ++void isp1760_set_pullup(struct isp1760_device *isp, bool enable); ++ ++static inline u32 isp1760_field_read(struct regmap_field **fields, u32 field) ++{ ++ unsigned int val; ++ ++ regmap_field_read(fields[field], &val); ++ ++ return val; ++} ++ ++static inline void isp1760_field_write(struct regmap_field **fields, u32 field, ++ u32 val) ++{ ++ regmap_field_write(fields[field], val); ++} ++ ++static inline void isp1760_field_set(struct regmap_field **fields, u32 field) ++{ ++ isp1760_field_write(fields, field, 0xFFFFFFFF); ++} ++ ++static inline void isp1760_field_clear(struct regmap_field **fields, u32 field) ++{ ++ isp1760_field_write(fields, field, 0); ++} ++ ++static inline u32 isp1760_reg_read(struct regmap *regs, u32 reg) ++{ ++ unsigned int val; ++ ++ regmap_read(regs, reg, &val); ++ ++ return val; ++} ++ ++static inline void isp1760_reg_write(struct regmap *regs, u32 reg, u32 val) ++{ ++ regmap_write(regs, reg, val); ++} ++#endif +diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c +new file mode 100644 +index 0000000000..b1d86dd69b +--- /dev/null ++++ b/drivers/usb/isp1760/isp1760-hcd.c +@@ -0,0 +1,2574 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Driver for the NXP ISP1760 chip ++ * ++ * Copyright 2021 Linaro, Rui Miguel Silva ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "isp1760-core.h" ++#include "isp1760-hcd.h" ++#include "isp1760-regs.h" ++#include "isp1760-uboot.h" ++ ++static struct kmem_cache *qtd_cachep; ++static struct kmem_cache *qh_cachep; ++static struct kmem_cache *urb_listitem_cachep; ++ ++typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, ++ struct isp1760_qtd *qtd); ++ ++static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) ++{ ++ return hcd->hcd_priv; ++} ++ ++#define dw_to_le32(x) (cpu_to_le32((__force u32)x)) ++#define le32_to_dw(x) ((__force __dw)(le32_to_cpu(x))) ++ ++/* urb state*/ ++#define DELETE_URB (0x0008) ++#define NO_TRANSFER_ACTIVE (0xffffffff) ++ ++/* Philips Proprietary Transfer Descriptor (PTD) */ ++typedef __u32 __bitwise __dw; ++struct ptd { ++ __dw dw0; ++ __dw dw1; ++ __dw dw2; ++ __dw dw3; ++ __dw dw4; ++ __dw dw5; ++ __dw dw6; ++ __dw dw7; ++}; ++ ++struct ptd_le32 { ++ __le32 dw0; ++ __le32 dw1; ++ __le32 dw2; ++ __le32 dw3; ++ __le32 dw4; ++ __le32 dw5; ++ __le32 dw6; ++ __le32 dw7; ++}; ++ ++#define PTD_OFFSET 0x0400 ++#define ISO_PTD_OFFSET 0x0400 ++#define INT_PTD_OFFSET 0x0800 ++#define ATL_PTD_OFFSET 0x0c00 ++#define PAYLOAD_OFFSET 0x1000 ++ ++#define ISP_BANK_0 0x00 ++#define ISP_BANK_1 0x01 ++#define ISP_BANK_2 0x02 ++#define ISP_BANK_3 0x03 ++ ++#define TO_DW(x) ((__force __dw)x) ++#define TO_U32(x) ((__force u32)x) ++ ++ /* ATL */ ++ /* DW0 */ ++#define DW0_VALID_BIT TO_DW(1) ++#define FROM_DW0_VALID(x) (TO_U32(x) & 0x01) ++#define TO_DW0_LENGTH(x) TO_DW((((u32)x) << 3)) ++#define TO_DW0_MAXPACKET(x) TO_DW((((u32)x) << 18)) ++#define TO_DW0_MULTI(x) TO_DW((((u32)x) << 29)) ++#define TO_DW0_ENDPOINT(x) TO_DW((((u32)x) << 31)) ++/* DW1 */ ++#define TO_DW1_DEVICE_ADDR(x) TO_DW((((u32)x) << 3)) ++#define TO_DW1_PID_TOKEN(x) TO_DW((((u32)x) << 10)) ++#define DW1_TRANS_BULK TO_DW(((u32)2 << 12)) ++#define DW1_TRANS_INT TO_DW(((u32)3 << 12)) ++#define DW1_TRANS_SPLIT TO_DW(((u32)1 << 14)) ++#define DW1_SE_USB_LOSPEED TO_DW(((u32)2 << 16)) ++#define TO_DW1_PORT_NUM(x) TO_DW((((u32)x) << 18)) ++#define TO_DW1_HUB_NUM(x) TO_DW((((u32)x) << 25)) ++/* DW2 */ ++#define TO_DW2_DATA_START_ADDR(x) TO_DW((((u32)x) << 8)) ++#define TO_DW2_RL(x) TO_DW(((x) << 25)) ++#define FROM_DW2_RL(x) ((TO_U32(x) >> 25) & 0xf) ++/* DW3 */ ++#define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x3fff) ++#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x07ff) ++#define TO_DW3_NAKCOUNT(x) TO_DW(((x) << 19)) ++#define FROM_DW3_NAKCOUNT(x) ((TO_U32(x) >> 19) & 0xf) ++#define TO_DW3_CERR(x) TO_DW(((x) << 23)) ++#define FROM_DW3_CERR(x) ((TO_U32(x) >> 23) & 0x3) ++#define TO_DW3_DATA_TOGGLE(x) TO_DW(((x) << 25)) ++#define FROM_DW3_DATA_TOGGLE(x) ((TO_U32(x) >> 25) & 0x1) ++#define TO_DW3_PING(x) TO_DW(((x) << 26)) ++#define FROM_DW3_PING(x) ((TO_U32(x) >> 26) & 0x1) ++#define DW3_ERROR_BIT TO_DW((1 << 28)) ++#define DW3_BABBLE_BIT TO_DW((1 << 29)) ++#define DW3_HALT_BIT TO_DW((1 << 30)) ++#define DW3_ACTIVE_BIT TO_DW((1 << 31)) ++#define FROM_DW3_ACTIVE(x) ((TO_U32(x) >> 31) & 0x01) ++ ++#define INT_UNDERRUN (1 << 2) ++#define INT_BABBLE (1 << 1) ++#define INT_EXACT (1 << 0) ++ ++#define SETUP_PID (2) ++#define IN_PID (1) ++#define OUT_PID (0) ++ ++/* Errata 1 */ ++#define RL_COUNTER (0) ++#define NAK_COUNTER (0) ++#define ERR_COUNTER (3) ++ ++struct isp1760_qtd { ++ u8 packet_type; ++ void *data_buffer; ++ u32 payload_addr; ++ ++ /* the rest is HCD-private */ ++ struct list_head qtd_list; ++ struct urb *urb; ++ size_t length; ++ size_t actual_length; ++ ++ /* QTD_ENQUEUED: waiting for transfer (inactive) */ ++ /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ ++ /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only ++ interrupt handler may touch this qtd! */ ++ /* QTD_XFER_COMPLETE: payload has been transferred successfully */ ++ /* QTD_RETIRE: transfer error/abort qtd */ ++#define QTD_ENQUEUED 0 ++#define QTD_PAYLOAD_ALLOC 1 ++#define QTD_XFER_STARTED 2 ++#define QTD_XFER_COMPLETE 3 ++#define QTD_RETIRE 4 ++ u32 status; ++}; ++ ++/* Queue head, one for each active endpoint */ ++struct isp1760_qh { ++ struct list_head qh_list; ++ struct list_head qtd_list; ++ int epnum; ++ u32 toggle; ++ u32 ping; ++ int slot; ++ int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ ++}; ++ ++struct urb_listitem { ++ struct list_head urb_list; ++ struct urb *urb; ++}; ++ ++static const u32 isp1763_hc_portsc1_fields[] = { ++ [PORT_OWNER] = BIT(13), ++ [PORT_POWER] = BIT(12), ++ [PORT_LSTATUS] = BIT(10), ++ [PORT_RESET] = BIT(8), ++ [PORT_SUSPEND] = BIT(7), ++ [PORT_RESUME] = BIT(6), ++ [PORT_PE] = BIT(2), ++ [PORT_CSC] = BIT(1), ++ [PORT_CONNECT] = BIT(0), ++}; ++ ++static struct descriptor { ++ struct usb_device_descriptor device; ++ struct usb_config_descriptor config; ++ struct usb_interface_descriptor interface; ++ struct usb_endpoint_descriptor endpoint; ++} __packed rh_descriptor = { ++ { ++ /* usb 2.0 root hub device descriptor */ ++ 0x12, /* __u8 bLength; */ ++ USB_DT_DEVICE, /* __u8 bDescriptorType; Device */ ++ 0x0002, /* __le16 bcdUSB; v2.0 */ ++ ++ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ ++ 0x00, /* __u8 bDeviceSubClass; */ ++ 0x00, /* __u8 bDeviceProtocol; [ usb 2.0 no TT ] */ ++ 0x40, /* __u8 bMaxPacketSize0; 64 Bytes */ ++ ++ 0x6b1d, /* __le16 idVendor; Linux Foundation 0x1d6b */ ++ 0x0200, /* __le16 idProduct; device 0x0002 */ ++ 0x0001, /* __le16 bcdDevice */ ++ ++ 0x03, /* __u8 iManufacturer; */ ++ 0x02, /* __u8 iProduct; */ ++ 0x01, /* __u8 iSerialNumber; */ ++ 0x01 /* __u8 bNumConfigurations; */ ++ }, { ++ /* one configuration */ ++ 0x09, /* __u8 bLength; */ ++ USB_DT_CONFIG, /* __u8 bDescriptorType; Configuration */ ++ 0x1900, /* __le16 wTotalLength; */ ++ 0x01, /* __u8 bNumInterfaces; (1) */ ++ 0x01, /* __u8 bConfigurationValue; */ ++ 0x00, /* __u8 iConfiguration; */ ++ 0xc0, /* __u8 bmAttributes; ++ Bit 7: must be set, ++ 6: Self-powered, ++ 5: Remote wakeup, ++ 4..0: resvd */ ++ 0x00, /* __u8 MaxPower; */ ++ }, { ++ /* one interface */ ++ 0x09, /* __u8 if_bLength; */ ++ USB_DT_INTERFACE, /* __u8 if_bDescriptorType; Interface */ ++ 0x00, /* __u8 if_bInterfaceNumber; */ ++ 0x00, /* __u8 if_bAlternateSetting; */ ++ 0x01, /* __u8 if_bNumEndpoints; */ ++ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ ++ 0x00, /* __u8 if_bInterfaceSubClass; */ ++ 0x00, /* __u8 if_bInterfaceProtocol; [usb1.1 or single tt] */ ++ 0x00, /* __u8 if_iInterface; */ ++ }, { ++ /* one endpoint (status change endpoint) */ ++ 0x07, /* __u8 ep_bLength; */ ++ USB_DT_ENDPOINT, /* __u8 ep_bDescriptorType; Endpoint */ ++ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ ++ 0x03, /* __u8 ep_bmAttributes; Interrupt */ ++ /* __le16 ep_wMaxPacketSize; 1 + (MAX_ROOT_PORTS / 8) ++ * see hub.c:hub_configure() for details. */ ++ (USB_MAXCHILDREN + 1 + 7) / 8, 0x00, ++ 0x0c /* __u8 ep_bInterval; (256ms -- usb 2.0 spec) */ ++ }, ++}; ++ ++/* ++ * Access functions for isp176x registers regmap fields ++ */ ++static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ return isp1760_field_read(priv->fields, field); ++} ++ ++/* ++ * We need, in isp1763, to write directly the values to the portsc1 ++ * register so it will make the other values to trigger. ++ */ ++static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field, ++ u32 val) ++{ ++ u32 bit = isp1763_hc_portsc1_fields[field]; ++ u32 port_status = readl(priv->base + ISP1763_HC_PORTSC1); ++ ++ if (val) ++ writel(port_status | bit, priv->base + ISP1763_HC_PORTSC1); ++ else ++ writel(port_status & ~bit, priv->base + ISP1763_HC_PORTSC1); ++} ++ ++static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (unlikely(priv->is_isp1763 && ++ (field >= PORT_OWNER && field <= PORT_CONNECT))) ++ return isp1760_hcd_portsc1_set_clear(priv, field, val); ++ ++ isp1760_field_write(priv->fields, field, val); ++} ++ ++static void isp1760_hcd_set(struct usb_hcd *hcd, u32 field) ++{ ++ isp1760_hcd_write(hcd, field, 0xFFFFFFFF); ++} ++ ++static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field) ++{ ++ isp1760_hcd_write(hcd, field, 0); ++} ++ ++static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field, ++ u32 timeout_us) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ u32 val; ++ ++ isp1760_hcd_set(hcd, field); ++ ++ return regmap_field_read_poll_timeout(priv->fields[field], val, ++ val, 10, timeout_us); ++} ++ ++static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field, ++ u32 timeout_us) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ u32 val; ++ ++ isp1760_hcd_set(hcd, field); ++ ++ return regmap_field_read_poll_timeout(priv->fields[field], val, ++ !val, 10, timeout_us); ++} ++ ++static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field, ++ u32 timeout_us) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ u32 val; ++ ++ isp1760_hcd_clear(hcd, field); ++ ++ return regmap_field_read_poll_timeout(priv->fields[field], val, ++ !val, 10, timeout_us); ++} ++ ++static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field) ++{ ++ return !!isp1760_hcd_read(hcd, field); ++} ++ ++static bool isp1760_hcd_ppc_is_set(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (priv->is_isp1763) ++ return true; ++ ++ return isp1760_hcd_is_set(hcd, HCS_PPC); ++} ++ ++static u32 isp1760_hcd_n_ports(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (priv->is_isp1763) ++ return 1; ++ ++ return isp1760_hcd_read(hcd, HCS_N_PORTS); ++} ++ ++/* ++ * Access functions for isp176x memory (offset >= 0x0400). ++ * ++ * bank_reads8() reads memory locations prefetched by an earlier write to ++ * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- ++ * bank optimizations, you should use the more generic mem_read() below. ++ * ++ * For access to ptd memory, use the specialized ptd_read() and ptd_write() ++ * below. ++ * ++ * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() ++ * doesn't quite work because some people have to enforce 32-bit access ++ */ ++static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, ++ __u32 *dst, u32 bytes) ++{ ++ __u32 __iomem *src; ++ u32 val; ++ __u8 *src_byteptr; ++ __u8 *dst_byteptr; ++ ++ src = src_base + (bank_addr | src_offset); ++ ++ if (src_offset < PAYLOAD_OFFSET) { ++ while (bytes >= 4) { ++ *dst = readl_relaxed(src); ++ bytes -= 4; ++ src++; ++ dst++; ++ } ++ } else { ++ while (bytes >= 4) { ++ *dst = __raw_readl(src); ++ bytes -= 4; ++ src++; ++ dst++; ++ } ++ } ++ ++ if (!bytes) ++ return; ++ ++ /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully ++ * allocated. ++ */ ++ if (src_offset < PAYLOAD_OFFSET) ++ val = readl_relaxed(src); ++ else ++ val = __raw_readl(src); ++ ++ dst_byteptr = (void *) dst; ++ src_byteptr = (void *) &val; ++ while (bytes > 0) { ++ *dst_byteptr = *src_byteptr; ++ dst_byteptr++; ++ src_byteptr++; ++ bytes--; ++ } ++} ++ ++static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst, ++ u32 bytes) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); ++ isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); ++ ndelay(100); ++ ++ bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes); ++} ++ ++/* ++ * ISP1763 does not have the banks direct host controller memory access, ++ * needs to use the HC_DATA register. Add data read/write according to this, ++ * and also adjust 16bit access. ++ */ ++static void isp1763_mem_read(struct usb_hcd *hcd, u16 srcaddr, ++ u16 *dstptr, u32 bytes) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ ++ /* Write the starting device address to the hcd memory register */ ++ isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, srcaddr); ++ ndelay(100); /* Delay between consecutive access */ ++ ++ /* As long there are at least 16-bit to read ... */ ++ while (bytes >= 2) { ++ *dstptr = __raw_readw(priv->base + ISP1763_HC_DATA); ++ bytes -= 2; ++ dstptr++; ++ } ++ ++ /* If there are no more bytes to read, return */ ++ if (bytes <= 0) ++ return; ++ ++ *((u8 *)dstptr) = (u8)(readw(priv->base + ISP1763_HC_DATA) & 0xFF); ++} ++ ++static void mem_read(struct usb_hcd *hcd, u32 src_offset, __u32 *dst, ++ u32 bytes) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (!priv->is_isp1763) ++ return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes); ++ ++ isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes); ++} ++ ++static void isp1760_mem_write(void __iomem *dst_base, u32 dst_offset, ++ __u32 const *src, u32 bytes) ++{ ++ __u32 __iomem *dst; ++ ++ dst = dst_base + dst_offset; ++ ++ if (dst_offset < PAYLOAD_OFFSET) { ++ while (bytes >= 4) { ++ writel_relaxed(*src, dst); ++ bytes -= 4; ++ src++; ++ dst++; ++ } ++ } else { ++ while (bytes >= 4) { ++ __raw_writel(*src, dst); ++ bytes -= 4; ++ src++; ++ dst++; ++ } ++ } ++ ++ if (!bytes) ++ return; ++ /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the ++ * extra bytes should not be read by the HW. ++ */ ++ ++ if (dst_offset < PAYLOAD_OFFSET) ++ writel_relaxed(*src, dst); ++ else ++ __raw_writel(*src, dst); ++} ++ ++static void isp1763_mem_write(struct usb_hcd *hcd, u16 dstaddr, u16 *src, ++ u32 bytes) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ /* Write the starting device address to the hcd memory register */ ++ isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, dstaddr); ++ ndelay(100); /* Delay between consecutive access */ ++ ++ while (bytes >= 2) { ++ /* Get and write the data; then adjust the data ptr and len */ ++ __raw_writew(*src, priv->base + ISP1763_HC_DATA); ++ bytes -= 2; ++ src++; ++ } ++ ++ /* If there are no more bytes to process, return */ ++ if (bytes <= 0) ++ return; ++ ++ /* ++ * The only way to get here is if there is a single byte left, ++ * get it and write it to the data reg; ++ */ ++ writew(*((u8 *)src), priv->base + ISP1763_HC_DATA); ++} ++ ++static void mem_write(struct usb_hcd *hcd, u32 dst_offset, __u32 *src, ++ u32 bytes) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (!priv->is_isp1763) ++ return isp1760_mem_write(priv->base, dst_offset, src, bytes); ++ ++ isp1763_mem_write(hcd, dst_offset, (u16 *)src, bytes); ++} ++ ++/* ++ * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, ++ * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. ++ */ ++static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, ++ struct ptd *ptd) ++{ ++ u16 src_offset = ptd_offset + slot * sizeof(*ptd); ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); ++ isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); ++ ndelay(90); ++ ++ bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd, ++ sizeof(*ptd)); ++} ++ ++static void isp1763_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, ++ struct ptd *ptd) ++{ ++ u16 src_offset = ptd_offset + slot * sizeof(*ptd); ++ struct ptd_le32 le32_ptd; ++ ++ isp1763_mem_read(hcd, src_offset, (u16 *)&le32_ptd, sizeof(le32_ptd)); ++ /* Normalize the data obtained */ ++ ptd->dw0 = le32_to_dw(le32_ptd.dw0); ++ ptd->dw1 = le32_to_dw(le32_ptd.dw1); ++ ptd->dw2 = le32_to_dw(le32_ptd.dw2); ++ ptd->dw3 = le32_to_dw(le32_ptd.dw3); ++ ptd->dw4 = le32_to_dw(le32_ptd.dw4); ++ ptd->dw5 = le32_to_dw(le32_ptd.dw5); ++ ptd->dw6 = le32_to_dw(le32_ptd.dw6); ++ ptd->dw7 = le32_to_dw(le32_ptd.dw7); ++} ++ ++static void ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, ++ struct ptd *ptd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (!priv->is_isp1763) ++ return isp1760_ptd_read(hcd, ptd_offset, slot, ptd); ++ ++ isp1763_ptd_read(hcd, ptd_offset, slot, ptd); ++} ++ ++static void isp1763_ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, ++ struct ptd *cpu_ptd) ++{ ++ u16 dst_offset = ptd_offset + slot * sizeof(*cpu_ptd); ++ struct ptd_le32 ptd; ++ ++ ptd.dw0 = dw_to_le32(cpu_ptd->dw0); ++ ptd.dw1 = dw_to_le32(cpu_ptd->dw1); ++ ptd.dw2 = dw_to_le32(cpu_ptd->dw2); ++ ptd.dw3 = dw_to_le32(cpu_ptd->dw3); ++ ptd.dw4 = dw_to_le32(cpu_ptd->dw4); ++ ptd.dw5 = dw_to_le32(cpu_ptd->dw5); ++ ptd.dw6 = dw_to_le32(cpu_ptd->dw6); ++ ptd.dw7 = dw_to_le32(cpu_ptd->dw7); ++ ++ isp1763_mem_write(hcd, dst_offset, (u16 *)&ptd.dw0, ++ 8 * sizeof(ptd.dw0)); ++} ++ ++static void isp1760_ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, ++ struct ptd *ptd) ++{ ++ u32 dst_offset = ptd_offset + slot * sizeof(*ptd); ++ ++ /* ++ * Make sure dw0 gets written last (after other dw's and after payload) ++ * since it contains the enable bit ++ */ ++ isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0), ++ (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1)); ++ wmb(); ++ isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0, ++ sizeof(ptd->dw0)); ++} ++ ++static void ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, ++ struct ptd *ptd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ if (!priv->is_isp1763) ++ return isp1760_ptd_write(priv->base, ptd_offset, slot, ptd); ++ ++ isp1763_ptd_write(hcd, ptd_offset, slot, ptd); ++} ++ ++/* memory management of the 60kb on the chip from 0x1000 to 0xffff */ ++static void init_memory(struct isp1760_hcd *priv) ++{ ++ const struct isp1760_memory_layout *mem = priv->memory_layout; ++ int i, j, curr; ++ u32 payload_addr; ++ ++ payload_addr = PAYLOAD_OFFSET; ++ ++ for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++) { ++ for (j = 0; j < mem->blocks[i]; j++, curr++) { ++ priv->memory_pool[curr + j].start = payload_addr; ++ priv->memory_pool[curr + j].size = mem->blocks_size[i]; ++ priv->memory_pool[curr + j].free = 1; ++ payload_addr += priv->memory_pool[curr + j].size; ++ } ++ } ++ ++ WARN_ON(payload_addr - priv->memory_pool[0].start > ++ mem->payload_area_size); ++} ++ ++static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; ++ int i; ++ ++ WARN_ON(qtd->payload_addr); ++ ++ if (!qtd->length) ++ return; ++ ++ for (i = 0; i < mem->payload_blocks; i++) { ++ if (priv->memory_pool[i].size >= qtd->length && ++ priv->memory_pool[i].free) { ++ priv->memory_pool[i].free = 0; ++ qtd->payload_addr = priv->memory_pool[i].start; ++ return; ++ } ++ } ++} ++ ++static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; ++ int i; ++ ++ if (!qtd->payload_addr) ++ return; ++ ++ for (i = 0; i < mem->payload_blocks; i++) { ++ if (priv->memory_pool[i].start == qtd->payload_addr) { ++ WARN_ON(priv->memory_pool[i].free); ++ priv->memory_pool[i].free = 1; ++ qtd->payload_addr = 0; ++ return; ++ } ++ } ++ ++ WARN_ON(1); ++ qtd->payload_addr = 0; ++} ++ ++/* reset a non-running (STS_HALT == 1) controller */ ++static int ehci_reset(struct usb_hcd *hcd) ++{ ++ return isp1760_hcd_set_and_wait_swap(hcd, CMD_RESET, 250 * 1000); ++} ++ ++static struct isp1760_qh *qh_alloc(gfp_t flags) ++{ ++ struct isp1760_qh *qh; ++ ++ qh = kmem_cache_alloc(qh_cachep, flags); ++ if (!qh) ++ return NULL; ++ ++ memset(qh, '\0', qh_cachep->sz); ++ INIT_LIST_HEAD(&qh->qh_list); ++ INIT_LIST_HEAD(&qh->qtd_list); ++ qh->slot = -1; ++ ++ return qh; ++} ++ ++static void qh_free(struct isp1760_qh *qh) ++{ ++ WARN_ON(!list_empty(&qh->qtd_list)); ++ WARN_ON(qh->slot > -1); ++ kmem_cache_free(qh_cachep, qh); ++} ++ ++/* one-time init, only for memory state */ ++static int priv_init(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ u32 isoc_cache; ++ u32 isoc_thres; ++ int i; ++ ++ spin_lock_init(&priv->lock); ++ ++ for (i = 0; i < QH_END; i++) ++ INIT_LIST_HEAD(&priv->qh_list[i]); ++ ++ /* ++ * hw default: 1K periodic list heads, one per frame. ++ * periodic_size can shrink by USBCMD update if hcc_params allows. ++ */ ++ priv->periodic_size = DEFAULT_I_TDPS; ++ ++ if (priv->is_isp1763) { ++ priv->i_thresh = 2; ++ return 0; ++ } ++ ++ /* controllers may cache some of the periodic schedule ... */ ++ isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE); ++ isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES); ++ ++ /* full frame cache */ ++ if (isoc_cache) ++ priv->i_thresh = 8; ++ else /* N microframes cached */ ++ priv->i_thresh = 2 + isoc_thres; ++ ++ return 0; ++} ++ ++static int isp1760_hc_setup(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ u32 atx_reset; ++ int result; ++ u32 scratch; ++ u32 pattern; ++ ++ if (priv->is_isp1763) ++ pattern = 0xcafe; ++ else ++ pattern = 0xdeadcafe; ++ ++ isp1760_hcd_write(hcd, HC_SCRATCH, pattern); ++ ++ /* Change bus pattern */ ++ scratch = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); ++ scratch = isp1760_hcd_read(hcd, HC_SCRATCH); ++ if (scratch != pattern) { ++ printf("Scratch test failed. 0x%08x\n", scratch); ++ return -ENODEV; ++ } ++ ++ /* ++ * The RESET_HC bit in the SW_RESET register is supposed to reset the ++ * host controller without touching the CPU interface registers, but at ++ * least on the ISP1761 it seems to behave as the RESET_ALL bit and ++ * reset the whole device. We thus can't use it here, so let's reset ++ * the host controller through the EHCI USB Command register. The device ++ * has been reset in core code anyway, so this shouldn't matter. ++ */ ++ isp1760_hcd_clear(hcd, ISO_BUF_FILL); ++ isp1760_hcd_clear(hcd, INT_BUF_FILL); ++ isp1760_hcd_clear(hcd, ATL_BUF_FILL); ++ ++ isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); ++ ++ result = ehci_reset(hcd); ++ if (result) ++ return result; ++ ++ /* Step 11 passed */ ++ ++ /* ATL reset */ ++ if (priv->is_isp1763) ++ atx_reset = SW_RESET_RESET_ATX; ++ else ++ atx_reset = ALL_ATX_RESET; ++ ++ isp1760_hcd_set(hcd, atx_reset); ++ mdelay(10); ++ isp1760_hcd_clear(hcd, atx_reset); ++ ++ if (priv->is_isp1763) { ++ isp1760_hcd_set(hcd, HW_OTG_DISABLE); ++ isp1760_hcd_set(hcd, HW_SW_SEL_HC_DC_CLEAR); ++ isp1760_hcd_set(hcd, HW_HC_2_DIS_CLEAR); ++ isp1760_hcd_set(hcd, HW_DM_PULLDOWN); ++ isp1760_hcd_set(hcd, HW_DP_PULLDOWN); ++ mdelay(10); ++ ++ isp1760_hcd_set(hcd, HW_INTF_LOCK); ++ } ++ ++ isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); ++ isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); ++ ++ return priv_init(hcd); ++} ++ ++static u32 base_to_chip(u32 base) ++{ ++ return ((base - 0x400) >> 3); ++} ++ ++static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) ++{ ++ struct urb *urb; ++ ++ if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) ++ return 1; ++ ++ urb = qtd->urb; ++ qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); ++ ++ return (qtd->urb != urb); ++} ++ ++/* magic numbers that can affect system performance */ ++#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ ++#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ ++#define EHCI_TUNE_RL_TT 0 ++#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ ++#define EHCI_TUNE_MULT_TT 1 ++#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ ++ ++static void create_ptd_atl(struct isp1760_qh *qh, struct isp1760_qtd *qtd, ++ struct ptd *ptd) ++{ ++ u32 maxpacket; ++ u32 multi; ++ u32 rl = RL_COUNTER; ++ u32 nak = NAK_COUNTER; ++ u8 portnr; ++ u8 hubaddr; ++ ++ memset(ptd, 0, sizeof(*ptd)); ++ ++ /* according to 3.6.2, max packet len can not be > 0x400 */ ++ maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe); ++ multi = 1 + ((maxpacket >> 11) & 0x3); ++ maxpacket &= 0x7ff; ++ ++ /* DW0 */ ++ ptd->dw0 = DW0_VALID_BIT; ++ ptd->dw0 |= TO_DW0_LENGTH(qtd->length); ++ ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); ++ ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); ++ ++ /* DW1 */ ++ ptd->dw1 = TO_DW((usb_pipeendpoint(qtd->urb->pipe) >> 1)); ++ ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); ++ ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); ++ ++ if (usb_pipebulk(qtd->urb->pipe)) ++ ptd->dw1 |= DW1_TRANS_BULK; ++ else if (usb_pipeint(qtd->urb->pipe)) ++ ptd->dw1 |= DW1_TRANS_INT; ++ ++ if (qtd->urb->dev->speed != USB_SPEED_HIGH) { ++ /* split transaction */ ++ ++ ptd->dw1 |= DW1_TRANS_SPLIT; ++ if (qtd->urb->dev->speed == USB_SPEED_LOW) ++ ptd->dw1 |= DW1_SE_USB_LOSPEED; ++ ++ if (!qtd->urb->dev->dev->parent_priv_) { ++ portnr = qtd->urb->dev->portnr; ++ hubaddr = qtd->urb->dev->devnum; ++ } else { ++ usb_find_usb2_hub_address_port(qtd->urb->dev, &hubaddr, ++ &portnr); ++ } ++ ++ ptd->dw1 |= TO_DW1_PORT_NUM(portnr); ++ ptd->dw1 |= TO_DW1_HUB_NUM(hubaddr); ++ ++ /* SE bit for Split INT transfers */ ++ if (usb_pipeint(qtd->urb->pipe) && ++ (qtd->urb->dev->speed == USB_SPEED_LOW)) ++ ptd->dw1 |= DW1_SE_USB_LOSPEED; ++ ++ rl = 0; ++ nak = 0; ++ } else { ++ ptd->dw0 |= TO_DW0_MULTI(multi); ++ if (usb_pipecontrol(qtd->urb->pipe) || ++ usb_pipebulk(qtd->urb->pipe)) ++ ptd->dw3 |= TO_DW3_PING(qh->ping); ++ } ++ /* DW2 */ ++ ptd->dw2 = 0; ++ ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); ++ ptd->dw2 |= TO_DW2_RL(rl); ++ ++ /* DW3 */ ++ ptd->dw3 |= TO_DW3_NAKCOUNT(nak); ++ ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); ++ ++ if (usb_pipecontrol(qtd->urb->pipe)) { ++ if (qtd->data_buffer == qtd->urb->setup_packet) { ++ ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); ++ } else if (last_qtd_of_urb(qtd, qh)) { ++ ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); ++ } ++ } ++ ++ ptd->dw3 |= DW3_ACTIVE_BIT; ++ /* Cerr */ ++ ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); ++} ++ ++static void transform_add_int(struct isp1760_qh *qh, struct isp1760_qtd *qtd, ++ struct ptd *ptd) ++{ ++ struct usb_host_endpoint *hep = qtd->urb->ep; ++ struct usb_endpoint_descriptor *epd = &hep->desc; ++ u32 usof; ++ u32 period; ++ ++ /* ++ * Most of this is guessing. ISP1761 datasheet is quite unclear, and ++ * the algorithm from the original Philips driver code, which was ++ * pretty much used in this driver before as well, is quite horrendous ++ * and, i believe, incorrect. The code below follows the datasheet and ++ * USB2.0 spec as far as I can tell, and plug/unplug seems to be much ++ * more reliable this way (fingers crossed...). ++ */ ++ ++ if (qtd->urb->dev->speed == USB_SPEED_HIGH) { ++ /* urb->interval is in units of microframes (1/8 ms) */ ++ period = epd->bInterval >> 3; ++ ++ if (epd->bInterval > 4) ++ usof = 0x01; /* One bit set => ++ interval 1 ms * uFrame-match */ ++ else if (epd->bInterval > 2) ++ usof = 0x22; /* Two bits set => interval 1/2 ms */ ++ else if (epd->bInterval > 1) ++ usof = 0x55; /* Four bits set => interval 1/4 ms */ ++ else ++ usof = 0xff; /* All bits set => interval 1/8 ms */ ++ } else { ++ /* urb->interval is in units of frames (1 ms) */ ++ period = epd->bInterval; ++ usof = 0x0f; /* Execute Start Split on any of the ++ four first uFrames */ ++ ++ /* ++ * First 8 bits in dw5 is uSCS and "specifies which uSOF the ++ * complete split needs to be sent. Valid only for IN." Also, ++ * "All bits can be set to one for every transfer." (p 82, ++ * ISP1761 data sheet.) 0x1c is from Philips driver. Where did ++ * that number come from? 0xff seems to work fine... ++ */ ++ /* ptd->dw5 = 0x1c; */ ++ ptd->dw5 = TO_DW(0xff); /* Execute Complete Split on any uFrame */ ++ } ++ ++ period = period >> 1;/* Ensure equal or shorter period than requested */ ++ period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ ++ ++ ptd->dw2 |= TO_DW(period); ++ ptd->dw4 = TO_DW(usof); ++} ++ ++static void create_ptd_int(struct isp1760_qh *qh, struct isp1760_qtd *qtd, ++ struct ptd *ptd) ++{ ++ create_ptd_atl(qh, qtd, ptd); ++ transform_add_int(qh, qtd, ptd); ++} ++ ++static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) ++{ ++ if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { ++ void *ptr; ++ for (ptr = urb->transfer_buffer; ++ ptr < urb->transfer_buffer + urb->transfer_buffer_length; ++ ptr += PAGE_SIZE) ++ flush_dcache_range((unsigned long)ptr, ++ (unsigned long)ptr + PAGE_SIZE); ++ } ++ ++ /* complete() can reenter this HCD */ ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++ usb_hcd_giveback_urb(hcd, urb, urb->status); ++} ++ ++static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, ++ u8 packet_type) ++{ ++ struct isp1760_qtd *qtd; ++ ++ qtd = kmem_cache_alloc(qtd_cachep, flags); ++ if (!qtd) ++ return NULL; ++ ++ memset(qtd, '\0', sizeof(*qtd)); ++ INIT_LIST_HEAD(&qtd->qtd_list); ++ qtd->urb = urb; ++ qtd->packet_type = packet_type; ++ qtd->status = QTD_ENQUEUED; ++ qtd->actual_length = 0; ++ ++ return qtd; ++} ++ ++static void qtd_free(struct isp1760_qtd *qtd) ++{ ++ WARN_ON(qtd->payload_addr); ++ kmem_cache_free(qtd_cachep, qtd); ++} ++ ++static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, ++ struct isp1760_slotinfo *slots, ++ struct isp1760_qtd *qtd, struct isp1760_qh *qh, ++ struct ptd *ptd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; ++ int skip_map; ++ ++ WARN_ON((slot < 0) || (slot > mem->slot_num - 1)); ++ WARN_ON(qtd->length && !qtd->payload_addr); ++ WARN_ON(slots[slot].qtd); ++ WARN_ON(slots[slot].qh); ++ WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); ++ ++ if (priv->is_isp1763) ++ ndelay(100); ++ ++ /* Make sure done map has not triggered from some unlinked transfer */ ++ if (ptd_offset == ATL_PTD_OFFSET) { ++ skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); ++ isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, ++ skip_map | (1 << slot)); ++ priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); ++ priv->atl_done_map &= ~(1 << slot); ++ } else { ++ skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); ++ isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, ++ skip_map | (1 << slot)); ++ priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); ++ priv->int_done_map &= ~(1 << slot); ++ } ++ ++ skip_map &= ~(1 << slot); ++ qh->slot = slot; ++ qtd->status = QTD_XFER_STARTED; ++ slots[slot].qtd = qtd; ++ slots[slot].qh = qh; ++ ++ ptd_write(hcd, ptd_offset, slot, ptd); ++ ++ if (ptd_offset == ATL_PTD_OFFSET) ++ isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); ++ else ++ isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); ++} ++ ++static int is_short_bulk(struct isp1760_qtd *qtd) ++{ ++ return (usb_pipebulk(qtd->urb->pipe) && ++ (qtd->actual_length < qtd->length)); ++} ++ ++static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, ++ struct list_head *urb_list) ++{ ++ struct isp1760_qtd *qtd, *qtd_next; ++ struct urb_listitem *urb_listitem; ++ int last_qtd; ++ ++ list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { ++ if (qtd->status < QTD_XFER_COMPLETE) ++ break; ++ ++ last_qtd = last_qtd_of_urb(qtd, qh); ++ ++ if ((!last_qtd) && (qtd->status == QTD_RETIRE)) ++ qtd_next->status = QTD_RETIRE; ++ ++ if (qtd->status == QTD_XFER_COMPLETE) { ++ if (qtd->actual_length) { ++ switch (qtd->packet_type) { ++ case IN_PID: ++ mem_read(hcd, qtd->payload_addr, ++ qtd->data_buffer, ++ qtd->actual_length); ++ fallthrough; ++ case OUT_PID: ++ qtd->urb->actual_length += ++ qtd->actual_length; ++ fallthrough; ++ case SETUP_PID: ++ break; ++ } ++ } ++ ++ if (is_short_bulk(qtd)) { ++ if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) ++ qtd->urb->status = -EREMOTEIO; ++ if (!last_qtd) ++ qtd_next->status = QTD_RETIRE; ++ } ++ } ++ ++ if (qtd->payload_addr) ++ free_mem(hcd, qtd); ++ ++ if (last_qtd) { ++ if ((qtd->status == QTD_RETIRE) && ++ (qtd->urb->status == -EINPROGRESS)) ++ qtd->urb->status = -EPIPE; ++ /* Defer calling of urb_done() since it releases lock */ ++ urb_listitem = kmem_cache_alloc(urb_listitem_cachep, ++ GFP_ATOMIC); ++ if (unlikely(!urb_listitem)) ++ break; /* Try again on next call */ ++ urb_listitem->urb = qtd->urb; ++ list_add_tail(&urb_listitem->urb_list, urb_list); ++ } ++ ++ list_del(&qtd->qtd_list); ++ qtd_free(qtd); ++ } ++} ++ ++#define ENQUEUE_DEPTH 2 ++static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; ++ int slot_num = mem->slot_num; ++ int ptd_offset; ++ struct isp1760_slotinfo *slots; ++ int curr_slot, free_slot; ++ int n; ++ struct ptd ptd; ++ struct isp1760_qtd *qtd; ++ ++ if (unlikely(list_empty(&qh->qtd_list))) ++ return; ++ ++ /* Make sure this endpoint's TT buffer is clean before queueing ptds */ ++ if (qh->tt_buffer_dirty) ++ return; ++ ++ if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, ++ qtd_list)->urb->pipe)) { ++ ptd_offset = INT_PTD_OFFSET; ++ slots = priv->int_slots; ++ } else { ++ ptd_offset = ATL_PTD_OFFSET; ++ slots = priv->atl_slots; ++ } ++ ++ free_slot = -1; ++ for (curr_slot = 0; curr_slot < slot_num; curr_slot++) { ++ if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) ++ free_slot = curr_slot; ++ if (slots[curr_slot].qh == qh) ++ break; ++ } ++ ++ n = 0; ++ list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { ++ if (qtd->status == QTD_ENQUEUED) { ++ WARN_ON(qtd->payload_addr); ++ alloc_mem(hcd, qtd); ++ if ((qtd->length) && (!qtd->payload_addr)) ++ break; ++ ++ if (qtd->length && (qtd->packet_type == SETUP_PID || ++ qtd->packet_type == OUT_PID)) { ++ mem_write(hcd, qtd->payload_addr, ++ qtd->data_buffer, qtd->length); ++ } ++ ++ qtd->status = QTD_PAYLOAD_ALLOC; ++ } ++ ++ if (qtd->status == QTD_PAYLOAD_ALLOC) { ++/* ++ if ((curr_slot > 31) && (free_slot == -1)) ++ printf("%s: No slot " ++ "available for transfer\n", __func__); ++*/ ++ /* Start xfer for this endpoint if not already done */ ++ if ((curr_slot > slot_num - 1) && (free_slot > -1)) { ++ if (usb_pipeint(qtd->urb->pipe)) ++ create_ptd_int(qh, qtd, &ptd); ++ else ++ create_ptd_atl(qh, qtd, &ptd); ++ ++ start_bus_transfer(hcd, ptd_offset, free_slot, ++ slots, qtd, qh, &ptd); ++ curr_slot = free_slot; ++ } ++ ++ n++; ++ if (n >= ENQUEUE_DEPTH) ++ break; ++ } ++ } ++} ++ ++static void schedule_ptds(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv; ++ struct isp1760_qh *qh, *qh_next; ++ struct list_head *ep_queue; ++ LIST_HEAD(urb_list); ++ struct urb_listitem *urb_listitem, *urb_listitem_next; ++ int i; ++ ++ if (!hcd) { ++ WARN_ON(1); ++ return; ++ } ++ ++ priv = hcd_to_priv(hcd); ++ ++ /* ++ * check finished/retired xfers, transfer payloads, call urb_done() ++ */ ++ for (i = 0; i < QH_END; i++) { ++ ep_queue = &priv->qh_list[i]; ++ list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) ++ collect_qtds(hcd, qh, &urb_list); ++ } ++ ++ list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, ++ urb_list) { ++ isp1760_urb_done(hcd, urb_listitem->urb); ++ kmem_cache_free(urb_listitem_cachep, urb_listitem); ++ } ++ ++ /* ++ * Schedule packets for transfer. ++ * ++ * According to USB2.0 specification: ++ * ++ * 1st prio: interrupt xfers, up to 80 % of bandwidth ++ * 2nd prio: control xfers ++ * 3rd prio: bulk xfers ++ * ++ * ... but let's use a simpler scheme here (mostly because ISP1761 doc ++ * is very unclear on how to prioritize traffic): ++ * ++ * 1) Enqueue any queued control transfers, as long as payload chip mem ++ * and PTD ATL slots are available. ++ * 2) Enqueue any queued INT transfers, as long as payload chip mem ++ * and PTD INT slots are available. ++ * 3) Enqueue any queued bulk transfers, as long as payload chip mem ++ * and PTD ATL slots are available. ++ * ++ * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between ++ * conservation of chip mem and performance. ++ * ++ * I'm sure this scheme could be improved upon! ++ */ ++ for (i = 0; i < QH_END; i++) { ++ ep_queue = &priv->qh_list[i]; ++ list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) ++ enqueue_qtds(hcd, qh); ++ } ++} ++ ++#define PTD_STATE_QTD_DONE 1 ++#define PTD_STATE_QTD_RELOAD 2 ++#define PTD_STATE_URB_RETIRE 3 ++ ++static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, ++ struct urb *urb) ++{ ++ u32 dw4; ++ int i; ++ ++ dw4 = TO_U32(ptd->dw4); ++ dw4 >>= 8; ++ ++ /* FIXME: ISP1761 datasheet does not say what to do with these. Do we ++ need to handle these errors? Is it done in hardware? */ ++ if (ptd->dw3 & DW3_HALT_BIT) { ++ ++ urb->status = -EPROTO; /* Default unknown error */ ++ ++ for (i = 0; i < 8; i++) { ++ switch (dw4 & 0x7) { ++ case INT_UNDERRUN: ++ printf("underrun during uFrame %d\n", i); ++ urb->status = -ECOMM; /* Could not write data */ ++ break; ++ case INT_EXACT: ++ printf("transaction error uFrame %d\n", i); ++ urb->status = -EPROTO; /* timeout, bad CRC, PID ++ error etc. */ ++ break; ++ case INT_BABBLE: ++ printf("babble error during uFrame %d\n", i); ++ urb->status = -EOVERFLOW; ++ break; ++ } ++ dw4 >>= 3; ++ } ++ ++ return PTD_STATE_URB_RETIRE; ++ } ++ ++ return PTD_STATE_QTD_DONE; ++} ++ ++static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, ++ struct urb *urb) ++{ ++ WARN_ON(!ptd); ++ if (ptd->dw3 & DW3_HALT_BIT) { ++ if (ptd->dw3 & DW3_BABBLE_BIT) ++ urb->status = -EOVERFLOW; ++ else if (FROM_DW3_CERR(ptd->dw3)) ++ urb->status = -EPIPE; /* Stall */ ++ else ++ urb->status = -EPROTO; /* Unknown */ ++ ++ /* usefull debug ++ printf("%s: ptd error:\n" ++ " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" ++ " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", ++ __func__, ++ ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, ++ ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); ++ */ ++ ++ return PTD_STATE_URB_RETIRE; ++ } ++ ++ /* Transfer Error, *but* active and no HALT -> reload */ ++ if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) ++ return PTD_STATE_QTD_RELOAD; ++ ++ /* ++ * NAKs are handled in HW by the chip. Usually if the ++ * device is not able to send data fast enough. ++ * This happens mostly on slower hardware. ++ */ ++ if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) ++ return PTD_STATE_QTD_RELOAD; ++ ++ return PTD_STATE_QTD_DONE; ++} ++ ++static void handle_done_ptds(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ struct isp1760_slotinfo *slots; ++ struct isp1760_qtd *qtd; ++ struct isp1760_qh *qh; ++ struct ptd ptd; ++ u32 ptd_offset; ++ int modified; ++ int skip_map; ++ int state; ++ int slot; ++ ++ skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); ++ priv->int_done_map &= ~skip_map; ++ skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); ++ priv->atl_done_map &= ~skip_map; ++ ++ modified = priv->int_done_map || priv->atl_done_map; ++ ++ while (priv->int_done_map || priv->atl_done_map) { ++ if (priv->int_done_map) { ++ /* INT ptd */ ++ slot = __ffs(priv->int_done_map); ++ priv->int_done_map &= ~(1 << slot); ++ slots = priv->int_slots; ++ /* This should not trigger, and could be removed if ++ noone have any problems with it triggering: */ ++ if (!slots[slot].qh) { ++ WARN_ON(1); ++ continue; ++ } ++ ptd_offset = INT_PTD_OFFSET; ++ ptd_read(hcd, INT_PTD_OFFSET, slot, &ptd); ++ state = check_int_transfer(hcd, &ptd, ++ slots[slot].qtd->urb); ++ } else { ++ /* ATL ptd */ ++ slot = __ffs(priv->atl_done_map); ++ priv->atl_done_map &= ~(1 << slot); ++ slots = priv->atl_slots; ++ /* This should not trigger, and could be removed if ++ noone have any problems with it triggering: */ ++ if (!slots[slot].qh) { ++ WARN_ON(1); ++ continue; ++ } ++ ptd_offset = ATL_PTD_OFFSET; ++ ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd); ++ state = check_atl_transfer(hcd, &ptd, ++ slots[slot].qtd->urb); ++ } ++ ++ qtd = slots[slot].qtd; ++ slots[slot].qtd = NULL; ++ qh = slots[slot].qh; ++ slots[slot].qh = NULL; ++ qh->slot = -1; ++ ++ WARN_ON(qtd->status != QTD_XFER_STARTED); ++ ++ switch (state) { ++ case PTD_STATE_QTD_DONE: ++ if ((usb_pipeint(qtd->urb->pipe)) && ++ (qtd->urb->dev->speed != USB_SPEED_HIGH)) ++ qtd->actual_length = ++ FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); ++ else ++ qtd->actual_length = ++ FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); ++ ++ qtd->status = QTD_XFER_COMPLETE; ++ ++ if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || ++ is_short_bulk(qtd)) ++ qtd = NULL; ++ else ++ qtd = list_entry(qtd->qtd_list.next, ++ typeof(*qtd), qtd_list); ++ ++ qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); ++ qh->ping = FROM_DW3_PING(ptd.dw3); ++ ++ break; ++ ++ case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ ++ qtd->status = QTD_PAYLOAD_ALLOC; ++ ptd.dw0 |= DW0_VALID_BIT; ++ /* RL counter = ERR counter */ ++ ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); ++ ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); ++ ptd.dw3 &= ~TO_DW3_CERR(3); ++ ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); ++ ++ qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); ++ qh->ping = FROM_DW3_PING(ptd.dw3); ++ break; ++ ++ case PTD_STATE_URB_RETIRE: ++ qtd->status = QTD_RETIRE; ++ qtd = NULL; ++ qh->toggle = 0; ++ qh->ping = 0; ++ break; ++ ++ default: ++ WARN_ON(1); ++ continue; ++ } ++ ++ if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { ++ if (slots == priv->int_slots) { ++ if (state == PTD_STATE_QTD_RELOAD) ++ dev_err(priv->dev, ++ "%s: PTD_STATE_QTD_RELOAD on " ++ "interrupt packet\n", __func__); ++ if (state != PTD_STATE_QTD_RELOAD) ++ create_ptd_int(qh, qtd, &ptd); ++ } else { ++ if (state != PTD_STATE_QTD_RELOAD) ++ create_ptd_atl(qh, qtd, &ptd); ++ } ++ ++ start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, ++ qh, &ptd); ++ } ++ } ++ ++ if (modified) ++ schedule_ptds(hcd); ++} ++ ++static irqreturn_t isp1760_irq(int irq, void *__hci) ++{ ++ struct usb_hcd *hcd = __hci; ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ irqreturn_t irqret = IRQ_NONE; ++ u32 int_reg; ++ u32 imask; ++ ++ imask = isp1760_hcd_read(hcd, HC_INTERRUPT); ++ if (unlikely(!imask)) ++ return irqret; ++ ++ int_reg = priv->is_isp1763 ? ISP1763_HC_INTERRUPT : ++ ISP176x_HC_INTERRUPT; ++ isp1760_reg_write(priv->regs, int_reg, imask); ++ ++ priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); ++ priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); ++ ++ handle_done_ptds(hcd); ++ ++ irqret = IRQ_HANDLED; ++ ++ return irqret; ++} ++ ++static int isp1763_run(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ int retval; ++ u32 chipid_h; ++ u32 chipid_l; ++ u32 chip_rev; ++ u32 ptd_atl_int; ++ u32 ptd_iso; ++ ++ chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); ++ chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); ++ chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); ++ printf("USB ISP %02x%02x HW rev. %d started\n", chipid_h, ++ chipid_l, chip_rev); ++ ++ isp1760_hcd_clear(hcd, ISO_BUF_FILL); ++ isp1760_hcd_clear(hcd, INT_BUF_FILL); ++ isp1760_hcd_clear(hcd, ATL_BUF_FILL); ++ ++ isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); ++ ndelay(100); ++ isp1760_hcd_clear(hcd, HC_ATL_PTD_DONEMAP); ++ isp1760_hcd_clear(hcd, HC_INT_PTD_DONEMAP); ++ isp1760_hcd_clear(hcd, HC_ISO_PTD_DONEMAP); ++ ++ isp1760_hcd_set(hcd, HW_OTG_DISABLE); ++ isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(7)); ++ isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(15)); ++ mdelay(10); ++ ++ isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); ++ isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); ++ ++ isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); ++ ++ isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); ++ isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); ++ isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); ++ ++ isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); ++ isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); ++ isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); ++ ++ ptd_atl_int = 0x8000; ++ ptd_iso = 0x0001; ++ ++ isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); ++ isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); ++ isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); ++ ++ isp1760_hcd_set(hcd, ATL_BUF_FILL); ++ isp1760_hcd_set(hcd, INT_BUF_FILL); ++ ++ isp1760_hcd_clear(hcd, CMD_LRESET); ++ isp1760_hcd_clear(hcd, CMD_RESET); ++ ++ retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); ++ if (retval) ++ return retval; ++ ++ down_write(&ehci_cf_port_reset_rwsem); ++ retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); ++ up_write(&ehci_cf_port_reset_rwsem); ++ retval = 0; ++ if (retval) ++ return retval; ++ ++ return 0; ++} ++ ++static int isp1760_run(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ int retval; ++ u32 chipid_h; ++ u32 chipid_l; ++ u32 chip_rev; ++ u32 ptd_atl_int; ++ u32 ptd_iso; ++ ++ /* ++ * ISP1763 have some differences in the setup and order to enable ++ * the ports, disable otg, setup buffers, and ATL, INT, ISO status. ++ * So, just handle it a separate sequence. ++ */ ++ if (priv->is_isp1763) ++ return isp1763_run(hcd); ++ ++ /* Set PTD interrupt AND & OR maps */ ++ isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); ++ isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); ++ isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); ++ ++ isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); ++ isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); ++ isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); ++ ++ /* step 23 passed */ ++ ++ isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); ++ ++ isp1760_hcd_clear(hcd, CMD_LRESET); ++ isp1760_hcd_clear(hcd, CMD_RESET); ++ ++ retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); ++ if (retval) ++ return retval; ++ ++ /* ++ * XXX ++ * Spec says to write FLAG_CF as last config action, priv code grabs ++ * the semaphore while doing so. ++ */ ++ down_write(&ehci_cf_port_reset_rwsem); ++ ++ retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); ++ up_write(&ehci_cf_port_reset_rwsem); ++ if (retval) ++ return retval; ++ ++ chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); ++ chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); ++ chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); ++ dev_info(priv->dev, "USB ISP %02x%02x HW rev. %d started\n", ++ chipid_h, chipid_l, chip_rev); ++ ++ /* PTD Register Init Part 2, Step 28 */ ++ ++ /* Setup registers controlling PTD checking */ ++ ptd_atl_int = 0x80000000; ++ ptd_iso = 0x00000001; ++ ++ isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); ++ isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); ++ isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); ++ ++ isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); ++ isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); ++ ++ isp1760_hcd_set(hcd, ATL_BUF_FILL); ++ isp1760_hcd_set(hcd, INT_BUF_FILL); ++ ++ /* GRR this is run-once init(), being done every time the HC starts. ++ * So long as they're part of class devices, we can't do it init() ++ * since the class device isn't created that early. ++ */ ++ return 0; ++} ++ ++static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) ++{ ++ qtd->data_buffer = databuffer; ++ ++ qtd->length = len; ++ ++ return qtd->length; ++} ++ ++static void qtd_list_free(struct list_head *qtd_list) ++{ ++ struct isp1760_qtd *qtd, *qtd_next; ++ ++ list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { ++ list_del(&qtd->qtd_list); ++ qtd_free(qtd); ++ } ++} ++ ++/* ++ * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. ++ * Also calculate the PID type (SETUP/IN/OUT) for each packet. ++ */ ++#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) ++static void packetize_urb(struct usb_hcd *hcd, ++ struct urb *urb, struct list_head *head, gfp_t flags) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ const struct isp1760_memory_layout *mem = priv->memory_layout; ++ struct isp1760_qtd *qtd; ++ void *buf; ++ int len, maxpacketsize; ++ u8 packet_type; ++ ++ /* ++ * URBs map to sequences of QTDs: one logical transaction ++ */ ++ ++ if (!urb->transfer_buffer && urb->transfer_buffer_length) { ++ /* XXX This looks like usb storage / SCSI bug */ ++ dev_err(priv->dev, "buf is null, dma is %08lx len is %d\n", ++ (long unsigned)urb->transfer_dma, ++ urb->transfer_buffer_length); ++ WARN_ON(1); ++ } ++ ++ if (usb_pipein(urb->pipe)) ++ packet_type = IN_PID; ++ else ++ packet_type = OUT_PID; ++ ++ if (usb_pipecontrol(urb->pipe)) { ++ qtd = qtd_alloc(flags, urb, SETUP_PID); ++ if (!qtd) ++ goto cleanup; ++ qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); ++ list_add_tail(&qtd->qtd_list, head); ++ ++ /* for zero length DATA stages, STATUS is always IN */ ++ if (urb->transfer_buffer_length == 0) ++ packet_type = IN_PID; ++ } ++ ++ maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe)); ++ ++ /* ++ * buffer gets wrapped in one or more qtds; ++ * last one may be "short" (including zero len) ++ * and may serve as a control status ack ++ */ ++ buf = urb->transfer_buffer; ++ len = urb->transfer_buffer_length; ++ ++ for (;;) { ++ int this_qtd_len; ++ ++ qtd = qtd_alloc(flags, urb, packet_type); ++ if (!qtd) ++ goto cleanup; ++ ++ if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1]) ++ len = mem->blocks_size[ISP176x_BLOCK_NUM - 1]; ++ ++ this_qtd_len = qtd_fill(qtd, buf, len); ++ list_add_tail(&qtd->qtd_list, head); ++ ++ len -= this_qtd_len; ++ buf += this_qtd_len; ++ ++ if (len <= 0) ++ break; ++ } ++ ++ /* ++ * control requests may need a terminating data "status" ack; ++ * bulk ones may need a terminating short packet (zero length). ++ */ ++ if (urb->transfer_buffer_length != 0) { ++ int one_more = 0; ++ ++ if (usb_pipecontrol(urb->pipe)) { ++ one_more = 1; ++ if (packet_type == IN_PID) ++ packet_type = OUT_PID; ++ else ++ packet_type = IN_PID; ++ } else if (usb_pipebulk(urb->pipe) ++ && (urb->transfer_flags & URB_ZERO_PACKET) ++ && !(urb->transfer_buffer_length % ++ maxpacketsize)) { ++ one_more = 1; ++ } ++ if (one_more) { ++ qtd = qtd_alloc(flags, urb, packet_type); ++ if (!qtd) ++ goto cleanup; ++ ++ /* never any data in such packets */ ++ qtd_fill(qtd, NULL, 0); ++ list_add_tail(&qtd->qtd_list, head); ++ } ++ } ++ ++ return; ++ ++cleanup: ++ qtd_list_free(head); ++} ++ ++static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, ++ gfp_t mem_flags) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ struct isp1760_qh *qh = NULL; ++ struct list_head *ep_queue; ++ LIST_HEAD(new_qtds); ++ int qh_in_queue; ++ int retval; ++ int epnum; ++ ++ switch (usb_pipetype(urb->pipe)) { ++ case PIPE_CONTROL: ++ ep_queue = &priv->qh_list[QH_CONTROL]; ++ break; ++ case PIPE_BULK: ++ ep_queue = &priv->qh_list[QH_BULK]; ++ break; ++ case PIPE_INTERRUPT: ++ ep_queue = &priv->qh_list[QH_INTERRUPT]; ++ break; ++ case PIPE_ISOCHRONOUS: ++ printf("isochronous USB packets not yet supported\n"); ++ return -EPIPE; ++ default: ++ printf("unknown pipe type\n"); ++ return -EPIPE; ++ } ++ ++ if (usb_pipein(urb->pipe)) ++ urb->actual_length = 0; ++ ++ packetize_urb(hcd, urb, &new_qtds, mem_flags); ++ if (list_empty(&new_qtds)) ++ return -ENOMEM; ++ ++ retval = usb_hcd_link_urb_to_ep(hcd, urb); ++ if (retval) { ++ qtd_list_free(&new_qtds); ++ goto out; ++ } ++ ++ epnum = usb_pipeendpoint(urb->pipe); ++ ++ qh_in_queue = 0; ++ list_for_each_entry(qh, ep_queue, qh_list) { ++ if (qh->epnum == epnum) { ++ qh_in_queue = 1; ++ break; ++ } ++ } ++ ++ if (!qh_in_queue) { ++ qh = qh_alloc(GFP_ATOMIC); ++ if (!qh) { ++ retval = -ENOMEM; ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++ qtd_list_free(&new_qtds); ++ goto out; ++ } ++ ++ qh->epnum = epnum; ++ list_add_tail(&qh->qh_list, ep_queue); ++ urb->ep->hcpriv = qh; ++ } ++ ++ list_splice_tail(&new_qtds, &qh->qtd_list); ++ schedule_ptds(hcd); ++ ++out: ++ return retval; ++} ++ ++static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, ++ struct isp1760_qh *qh) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ int skip_map; ++ ++ WARN_ON(qh->slot == -1); ++ ++ /* We need to forcefully reclaim the slot since some transfers never ++ return, e.g. interrupt transfers and NAKed bulk transfers. */ ++ if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { ++ skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); ++ skip_map |= (1 << qh->slot); ++ isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); ++ ndelay(100); ++ priv->atl_slots[qh->slot].qh = NULL; ++ priv->atl_slots[qh->slot].qtd = NULL; ++ } else { ++ skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); ++ skip_map |= (1 << qh->slot); ++ isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); ++ priv->int_slots[qh->slot].qh = NULL; ++ priv->int_slots[qh->slot].qtd = NULL; ++ } ++ ++ qh->slot = -1; ++} ++ ++/* ++ * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing ++ * any active transfer belonging to the urb in the process. ++ */ ++static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, ++ struct isp1760_qtd *qtd) ++{ ++ struct urb *urb; ++ int urb_was_running; ++ ++ urb = qtd->urb; ++ urb_was_running = 0; ++ list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { ++ if (qtd->urb != urb) ++ break; ++ ++ if (qtd->status >= QTD_XFER_STARTED) ++ urb_was_running = 1; ++ if (last_qtd_of_urb(qtd, qh) && ++ (qtd->status >= QTD_XFER_COMPLETE)) ++ urb_was_running = 0; ++ ++ if (qtd->status == QTD_XFER_STARTED) ++ kill_transfer(hcd, urb, qh); ++ qtd->status = QTD_RETIRE; ++ } ++} ++ ++int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) ++{ ++ struct isp1760_qtd *qtd; ++ struct isp1760_qh *qh; ++ int retval = 0; ++ ++ retval = usb_hcd_check_unlink_urb(hcd, urb, status); ++ if (retval) ++ goto out; ++ ++ qh = urb->ep->hcpriv; ++ if (!qh) { ++ retval = -EINVAL; ++ goto out; ++ } ++ ++ list_for_each_entry(qtd, &qh->qtd_list, qtd_list) ++ if (qtd->urb == urb) { ++ dequeue_urb_from_qtd(hcd, qh, qtd); ++ list_move(&qtd->qtd_list, &qh->qtd_list); ++ break; ++ } ++ ++ urb->status = status; ++ schedule_ptds(hcd); ++ ++out: ++ return retval; ++} ++ ++static void isp1760_hub_descriptor(struct isp1760_hcd *priv, ++ struct usb_hub_descriptor *desc) ++{ ++ int ports; ++ u16 temp; ++ ++ ports = isp1760_hcd_n_ports(priv->hcd); ++ ++ desc->bDescriptorType = USB_DT_HUB; ++ /* priv 1.0, 2.3.9 says 20ms max */ ++ desc->bPwrOn2PwrGood = 10; ++ desc->bHubContrCurrent = 0; ++ ++ desc->bNbrPorts = ports; ++ temp = 1 + (ports / 8); ++ desc->bLength = 7 + 2 * temp; ++ ++ /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ ++ memset(&desc->u.hs.DeviceRemovable[0], 0, temp); ++ memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); ++ ++ /* per-port overcurrent reporting */ ++ temp = HUB_CHAR_INDV_PORT_OCPM; ++ if (isp1760_hcd_ppc_is_set(priv->hcd)) ++ /* per-port power control */ ++ temp |= HUB_CHAR_INDV_PORT_LPSM; ++ else ++ /* no power switching */ ++ temp |= HUB_CHAR_NO_LPSM; ++ desc->wHubCharacteristics = cpu_to_le16(temp); ++} ++ ++#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) ++ ++static void check_reset_complete(struct usb_hcd *hcd, int index) ++{ ++ if (!(isp1760_hcd_is_set(hcd, PORT_CONNECT))) ++ return; ++ ++ /* if reset finished and it's still not enabled -- handoff */ ++ if (!isp1760_hcd_is_set(hcd, PORT_PE)) { ++ printf("port %d full speed --> companion\n", index + 1); ++ ++ isp1760_hcd_set(hcd, PORT_OWNER); ++ ++ isp1760_hcd_clear(hcd, PORT_CSC); ++ } else { ++ printf("port %d high speed\n", index + 1); ++ } ++ ++ return; ++} ++ ++static int isp1760_hub_control(struct usb_hcd *hcd, struct usb_device *dev, ++ unsigned long pipe, void *buffer, int length, ++ struct devrequest *setup) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ u16 typeReq, wValue, wIndex; ++ unsigned long flags; ++ char *buf = buffer; ++ void *src = NULL; ++ int src_len = 0; ++ int retval = 0; ++ u32 status; ++ int ports; ++ ++ if (!setup) ++ return -EINVAL; ++ ++ ports = isp1760_hcd_n_ports(hcd); ++ ++ typeReq = setup->request | (setup->requesttype << 8); ++ wValue = le16_to_cpu(setup->value); ++ wIndex = le16_to_cpu(setup->index); ++ ++ /* ++ * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. ++ * HCS_INDICATOR may say we can change LEDs to off/amber/green. ++ * (track current state ourselves) ... blink for diagnostics, ++ * power, "this is the one", etc. EHCI spec supports this. ++ */ ++ ++ switch (typeReq) { ++ case DeviceOutRequest | USB_REQ_SET_ADDRESS: ++ break; ++ case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: ++ /* Nothing to do */ ++ break; ++ case DeviceRequest | USB_REQ_GET_DESCRIPTOR: ++ switch (wValue & 0xff00) { ++ case USB_DT_DEVICE << 8: ++ src = &rh_descriptor.device; ++ src_len = 0x12; ++ break; ++ case USB_DT_CONFIG << 8: ++ src = &rh_descriptor.config; ++ src_len = 0x09; ++ break; ++ case USB_DT_STRING << 8: ++ switch (wValue & 0xff) { ++ case 0: /* Language */ ++ src = "\4\3\19\4"; ++ src_len = 4; ++ break; ++ case 1: /* Vendor String */ ++ src = "\16\3U\0-\0B\0o\0o\0t\0"; ++ src_len = 14; ++ break; ++ case 2: /* Product Name */ ++ src = "\52\3I\0S\0P\0-\0 " ++ "\0H\0o\0s\0t\0 " ++ "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; ++ src_len = 42; ++ break; ++ default: ++ goto error; ++ } ++ break; ++ } ++ break; ++ case ClearHubFeature: ++ switch (wValue) { ++ case C_HUB_LOCAL_POWER: ++ case C_HUB_OVER_CURRENT: ++ /* no hub-wide feature/status flags */ ++ break; ++ default: ++ goto error; ++ } ++ break; ++ case ClearPortFeature: ++ if (!wIndex || wIndex > ports) ++ goto error; ++ wIndex--; ++ ++ /* ++ * Even if OWNER is set, so the port is owned by the ++ * companion controller, hub_wq needs to be able to clear ++ * the port-change status bits (especially ++ * USB_PORT_STAT_C_CONNECTION). ++ */ ++ ++ switch (wValue) { ++ case USB_PORT_FEAT_ENABLE: ++ isp1760_hcd_clear(hcd, PORT_PE); ++ break; ++ case USB_PORT_FEAT_C_ENABLE: ++ /* XXX error? */ ++ break; ++ case USB_PORT_FEAT_SUSPEND: ++ if (isp1760_hcd_is_set(hcd, PORT_RESET)) ++ goto error; ++ ++ if (isp1760_hcd_is_set(hcd, PORT_SUSPEND)) { ++ if (!isp1760_hcd_is_set(hcd, PORT_PE)) ++ goto error; ++ /* resume signaling for 20 msec */ ++ isp1760_hcd_clear(hcd, PORT_CSC); ++ isp1760_hcd_set(hcd, PORT_RESUME); ++ ++ priv->reset_done = get_timer(0) + 40; ++ } ++ break; ++ case USB_PORT_FEAT_C_SUSPEND: ++ /* we auto-clear this feature */ ++ break; ++ case USB_PORT_FEAT_POWER: ++ if (isp1760_hcd_ppc_is_set(hcd)) ++ isp1760_hcd_clear(hcd, PORT_POWER); ++ break; ++ case USB_PORT_FEAT_C_CONNECTION: ++ isp1760_hcd_set(hcd, PORT_CSC); ++ break; ++ case USB_PORT_FEAT_C_OVER_CURRENT: ++ /* XXX error ?*/ ++ break; ++ case USB_PORT_FEAT_C_RESET: ++ /* GetPortStatus clears reset */ ++ break; ++ default: ++ goto error; ++ } ++ isp1760_hcd_read(hcd, CMD_RUN); ++ break; ++ case GetHubDescriptor: ++ isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) buf); ++ break; ++ case GetHubStatus: ++ /* no hub-wide feature/status flags */ ++ memset(buf, 0, 4); ++ break; ++ case GetPortStatus: ++ if (!wIndex || wIndex > ports) ++ goto error; ++ wIndex--; ++ status = 0; ++ ++ /* wPortChange bits */ ++ if (isp1760_hcd_is_set(hcd, PORT_CSC)) ++ status |= USB_PORT_STAT_C_CONNECTION << 16; ++ ++ /* whoever resumes must GetPortStatus to complete it!! */ ++ if (isp1760_hcd_is_set(hcd, PORT_RESUME)) { ++ status |= USB_PORT_STAT_C_SUSPEND << 16; ++ ++ if (!priv->reset_done) { ++ priv->reset_done = get_timer(0) + 20; ++ } else if (get_timer(0) > priv->reset_done) { ++ /* stop resume signaling */ ++ isp1760_hcd_clear(hcd, PORT_CSC); ++ ++ retval = isp1760_hcd_clear_and_wait(hcd, ++ PORT_RESUME, 2000); ++ if (retval != 0) { ++ printf("port %d resume error %d\n", ++ wIndex + 1, retval); ++ goto error; ++ } ++ } ++ } ++ ++ /* whoever resets must GetPortStatus to complete it!! */ ++ if (isp1760_hcd_is_set(hcd, PORT_RESET) && ++ get_timer(0) > priv->reset_done) { ++ status |= USB_PORT_STAT_C_RESET << 16; ++ priv->reset_done = 0; ++ ++ /* force reset to complete */ ++ /* REVISIT: some hardware needs 550+ usec to clear ++ * this bit; seems too long to spin routinely... ++ */ ++ retval = isp1760_hcd_clear_and_wait(hcd, PORT_RESET, ++ 750); ++ if (retval != 0) { ++ printf("port %d reset error %d\n", wIndex + 1, ++ retval); ++ goto error; ++ } ++ ++ /* see what we found out */ ++ check_reset_complete(hcd, wIndex); ++ } ++ /* ++ * Even if OWNER is set, there's no harm letting hub_wq ++ * see the wPortStatus values (they should all be 0 except ++ * for PORT_POWER anyway). ++ */ ++ ++ if (isp1760_hcd_is_set(hcd, PORT_OWNER)) ++ printf("PORT_OWNER is set\n"); ++ ++ if (isp1760_hcd_is_set(hcd, PORT_CONNECT)) { ++ status |= USB_PORT_STAT_CONNECTION; ++ ++ /* status may be from integrated TT */ ++ status |= USB_PORT_STAT_HIGH_SPEED; ++ } ++ if (isp1760_hcd_is_set(hcd, PORT_PE)) ++ status |= USB_PORT_STAT_ENABLE; ++ if (isp1760_hcd_is_set(hcd, PORT_SUSPEND) && ++ isp1760_hcd_is_set(hcd, PORT_RESUME)) ++ status |= USB_PORT_STAT_SUSPEND; ++ if (isp1760_hcd_is_set(hcd, PORT_RESET)) ++ status |= USB_PORT_STAT_RESET; ++ if (isp1760_hcd_is_set(hcd, PORT_POWER)) ++ status |= USB_PORT_STAT_POWER; ++ ++ put_unaligned(cpu_to_le32(status), (__le32 *) buf); ++ break; ++ case SetHubFeature: ++ switch (wValue) { ++ case C_HUB_LOCAL_POWER: ++ case C_HUB_OVER_CURRENT: ++ /* no hub-wide feature/status flags */ ++ break; ++ default: ++ goto error; ++ } ++ break; ++ case SetPortFeature: ++ wIndex &= 0xff; ++ if (!wIndex || wIndex > ports) ++ goto error; ++ wIndex--; ++ ++ if (isp1760_hcd_is_set(hcd, PORT_OWNER)) ++ break; ++ ++ switch (wValue) { ++ case USB_PORT_FEAT_ENABLE: ++ isp1760_hcd_set(hcd, PORT_PE); ++ break; ++ ++ case USB_PORT_FEAT_SUSPEND: ++ if (!isp1760_hcd_is_set(hcd, PORT_PE) || ++ isp1760_hcd_is_set(hcd, PORT_RESET)) ++ goto error; ++ ++ isp1760_hcd_set(hcd, PORT_SUSPEND); ++ break; ++ case USB_PORT_FEAT_POWER: ++ if (isp1760_hcd_ppc_is_set(hcd)) ++ isp1760_hcd_set(hcd, PORT_POWER); ++ break; ++ case USB_PORT_FEAT_RESET: ++ if (isp1760_hcd_is_set(hcd, PORT_RESUME)) ++ goto error; ++ /* line status bits may report this as low speed, ++ * which can be fine if this root hub has a ++ * transaction translator built in. ++ */ ++ if ((isp1760_hcd_is_set(hcd, PORT_CONNECT) && ++ !isp1760_hcd_is_set(hcd, PORT_PE)) && ++ (isp1760_hcd_read(hcd, PORT_LSTATUS) == 1)) { ++ isp1760_hcd_set(hcd, PORT_OWNER); ++ } else { ++ isp1760_hcd_set(hcd, PORT_RESET); ++ isp1760_hcd_clear(hcd, PORT_PE); ++ ++ priv->reset_done = get_timer(0) + 50; ++ } ++ break; ++ default: ++ goto error; ++ } ++ break; ++ ++ default: ++ printf("root: unknown request: 0x%0x\n", typeReq); ++ goto error; ++ } ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ if (src_len) { ++ length = min(src_len, length); ++ ++ if (src != NULL && length > 0) ++ memcpy(buffer, src, length); ++ else ++ printf("zero copy USB descriptor\n"); ++ } ++ ++ dev->act_len = length; ++ dev->status = 0; ++ ++ return 0; ++ ++error: ++ /* "stall" on error */ ++ dev->act_len = 0; ++ dev->status = USB_ST_STALLED; ++ return -EPIPE; ++} ++ ++#ifndef __UBOOT__ ++static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) ++{ ++ u32 status = 0; ++ int retval = 1; ++ ++ /* init status to no-changes */ ++ buf[0] = 0; ++ ++ if (isp1760_hcd_is_set(hcd, PORT_OWNER) && ++ isp1760_hcd_is_set(hcd, PORT_CSC)) { ++ isp1760_hcd_clear(hcd, PORT_CSC); ++ goto done; ++ } ++ ++done: ++ return status ? retval : 0; ++} ++ ++static void isp1760_endpoint_disable(struct usb_hcd *hcd, ++ struct usb_host_endpoint *ep) ++{ ++ struct isp1760_qh *qh, *qh_iter; ++ unsigned long spinflags; ++ int i; ++ ++ qh = ep->hcpriv; ++ if (!qh) ++ return; ++ ++ WARN_ON(!list_empty(&qh->qtd_list)); ++ ++ for (i = 0; i < QH_END; i++) ++ list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list) ++ if (qh_iter == qh) { ++ list_del(&qh_iter->qh_list); ++ i = QH_END; ++ break; ++ } ++ qh_free(qh); ++ ep->hcpriv = NULL; ++ ++ schedule_ptds(hcd); ++} ++ ++static int isp1760_get_frame(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ u32 fr; ++ ++ fr = isp1760_hcd_read(hcd, HC_FRINDEX); ++ return (fr >> 3) % priv->periodic_size; ++} ++ ++static void isp1760_stop(struct usb_hcd *hcd) ++{ ++ struct isp1760_hcd *priv = hcd_to_priv(hcd); ++ ++ msleep(20); ++ ++ spin_lock_irq(&priv->lock); ++ ehci_reset(hcd); ++ /* Disable IRQ */ ++ isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN); ++ spin_unlock_irq(&priv->lock); ++ ++ isp1760_hcd_clear(hcd, FLAG_CF); ++} ++ ++static void isp1760_shutdown(struct usb_hcd *hcd) ++{ ++ isp1760_stop(hcd); ++ ++ isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN); ++ ++ isp1760_hcd_clear(hcd, CMD_RUN); ++} ++ ++static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd, ++ struct usb_host_endpoint *ep) ++{ ++ struct isp1760_qh *qh = ep->hcpriv; ++ unsigned long spinflags; ++ ++ if (!qh) ++ return; ++ ++ qh->tt_buffer_dirty = 0; ++ schedule_ptds(hcd); ++} ++ ++ ++static const struct hc_driver isp1760_hc_driver = { ++ .description = "isp1760-hcd", ++ .product_desc = "NXP ISP1760 USB Host Controller", ++ .hcd_priv_size = sizeof(struct isp1760_hcd *), ++ .irq = isp1760_irq, ++ .flags = HCD_MEMORY | HCD_USB2, ++ .reset = isp1760_hc_setup, ++ .start = isp1760_run, ++ .stop = isp1760_stop, ++ .shutdown = isp1760_shutdown, ++ .urb_enqueue = isp1760_urb_enqueue, ++ .urb_dequeue = isp1760_urb_dequeue, ++ .endpoint_disable = isp1760_endpoint_disable, ++ .get_frame_number = isp1760_get_frame, ++ .hub_status_data = isp1760_hub_status_data, ++ .hub_control = isp1760_hub_control, ++ .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete, ++}; ++#endif // __UBOOT__ ++ ++int __init isp1760_init_kmem_once(void) ++{ ++ urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem", ++ sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | ++ SLAB_MEM_SPREAD, NULL); ++ ++ if (!urb_listitem_cachep) ++ return -ENOMEM; ++ ++ qtd_cachep = kmem_cache_create("isp1760_qtd", ++ sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | ++ SLAB_MEM_SPREAD, NULL); ++ ++ if (!qtd_cachep) ++ return -ENOMEM; ++ ++ qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), ++ 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); ++ ++ if (!qh_cachep) { ++ kmem_cache_destroy(qtd_cachep); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++void isp1760_deinit_kmem_cache(void) ++{ ++ kmem_cache_destroy(qtd_cachep); ++ kmem_cache_destroy(qh_cachep); ++ kmem_cache_destroy(urb_listitem_cachep); ++} ++ ++int isp1760_hcd_lowlevel_init(struct isp1760_hcd *priv) ++{ ++ int ret; ++ ++ ret = isp1760_hc_setup(priv->hcd); ++ if (ret < 0) ++ return ret; ++ ++ ret = isp1760_run(priv->hcd); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static const struct usb_urb_ops isp1760_urb_ops = { ++ .urb_enqueue = isp1760_urb_enqueue, ++ .urb_dequeue = isp1760_urb_dequeue, ++ .hub_control = isp1760_hub_control, ++ .isr = isp1760_irq, ++}; ++ ++int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, ++ int irq, unsigned long irqflags, ++ struct udevice *dev) ++{ ++ const struct isp1760_memory_layout *mem_layout = priv->memory_layout; ++ struct isp1760_host_data *host = dev_get_priv(dev); ++ struct usb_hcd *hcd = &host->hcd; ++ int ret; ++ ++ priv->hcd = hcd; ++ ++ hcd->hcd_priv = priv; ++ ++ priv->hcd = hcd; ++ ++ hcd->urb_ops = &isp1760_urb_ops; ++ ++ priv->atl_slots = kcalloc(mem_layout->slot_num, ++ sizeof(struct isp1760_slotinfo), GFP_KERNEL); ++ if (!priv->atl_slots) ++ return -ENOMEM; ++ ++ priv->int_slots = kcalloc(mem_layout->slot_num, ++ sizeof(struct isp1760_slotinfo), GFP_KERNEL); ++ if (!priv->int_slots) { ++ ret = -ENOMEM; ++ goto free_atl_slots; ++ } ++ ++ host->host_speed = USB_SPEED_HIGH; ++ ++ init_memory(priv); ++ ++ return 0; ++ ++free_atl_slots: ++ kfree(priv->atl_slots); ++ ++ return ret; ++} ++ ++void isp1760_hcd_unregister(struct isp1760_hcd *priv) ++{ ++ struct isp1760_qh *qh, *qh_next; ++ int i; ++ ++ for (i = 0; i < QH_END; i++) ++ list_for_each_entry_safe(qh, qh_next, &priv->qh_list[i], ++ qh_list) { ++ qtd_list_free(&qh->qtd_list); ++ list_del(&qh->qh_list); ++ qh_free(qh); ++ } ++ ++ kfree(priv->atl_slots); ++ kfree(priv->int_slots); ++} +diff --git a/drivers/usb/isp1760/isp1760-hcd.h b/drivers/usb/isp1760/isp1760-hcd.h +new file mode 100644 +index 0000000000..00f5ca8c1f +--- /dev/null ++++ b/drivers/usb/isp1760/isp1760-hcd.h +@@ -0,0 +1,82 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef _ISP1760_HCD_H_ ++#define _ISP1760_HCD_H_ ++ ++#include ++ ++#include "isp1760-regs.h" ++ ++struct isp1760_qh; ++struct isp1760_qtd; ++struct resource; ++struct usb_hcd; ++ ++struct isp1760_slotinfo { ++ struct isp1760_qh *qh; ++ struct isp1760_qtd *qtd; ++ unsigned long timestamp; ++}; ++ ++/* chip memory management */ ++#define ISP176x_BLOCK_MAX (32 + 20 + 4) ++#define ISP176x_BLOCK_NUM 3 ++ ++struct isp1760_memory_layout { ++ unsigned int blocks[ISP176x_BLOCK_NUM]; ++ unsigned int blocks_size[ISP176x_BLOCK_NUM]; ++ ++ unsigned int slot_num; ++ unsigned int payload_blocks; ++ unsigned int payload_area_size; ++}; ++ ++struct isp1760_memory_chunk { ++ unsigned int start; ++ unsigned int size; ++ unsigned int free; ++}; ++ ++enum isp1760_queue_head_types { ++ QH_CONTROL, ++ QH_BULK, ++ QH_INTERRUPT, ++ QH_END ++}; ++ ++struct isp1760_hcd { ++ struct usb_hcd *hcd; ++ struct udevice *dev; ++ ++ void __iomem *base; ++ ++ struct regmap *regs; ++ struct regmap_field *fields[HC_FIELD_MAX]; ++ ++ bool is_isp1763; ++ const struct isp1760_memory_layout *memory_layout; ++ ++ spinlock_t lock; ++ struct isp1760_slotinfo *atl_slots; ++ int atl_done_map; ++ struct isp1760_slotinfo *int_slots; ++ int int_done_map; ++ struct isp1760_memory_chunk memory_pool[ISP176x_BLOCK_MAX]; ++ struct list_head qh_list[QH_END]; ++ ++ /* periodic schedule support */ ++#define DEFAULT_I_TDPS 1024 ++ unsigned periodic_size; ++ unsigned i_thresh; ++ unsigned long reset_done; ++ unsigned long next_statechange; ++}; ++ ++int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, ++ int irq, unsigned long irqflags, struct udevice *dev); ++void isp1760_hcd_unregister(struct isp1760_hcd *priv); ++int isp1760_hcd_lowlevel_init(struct isp1760_hcd *priv); ++ ++int isp1760_init_kmem_once(void); ++void isp1760_deinit_kmem_cache(void); ++ ++#endif /* _ISP1760_HCD_H_ */ +diff --git a/drivers/usb/isp1760/isp1760-if.c b/drivers/usb/isp1760/isp1760-if.c +new file mode 100644 +index 0000000000..c610da6b23 +--- /dev/null ++++ b/drivers/usb/isp1760/isp1760-if.c +@@ -0,0 +1,127 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright 2021 Linaro, Rui Miguel Silva ++ * ++ * based on original code from: ++ * (c) 2007 Sebastian Siewior ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "isp1760-core.h" ++#include "isp1760-regs.h" ++#include "isp1760-uboot.h" ++ ++ ++static int isp1760_of_to_plat(struct udevice *dev) ++{ ++ struct isp1760_device *isp = dev_get_plat(dev); ++ unsigned int devflags = 0; ++ u32 bus_width = 0; ++ ofnode dp; ++ ++ ++ if (!dev_has_ofnode(dev)) { ++ /* select isp1763 as the default device */ ++ devflags = ISP1760_FLAG_ISP1763 | ISP1760_FLAG_BUS_WIDTH_16; ++ pr_err("isp1760: no platform data\n"); ++ goto isp_setup; ++ } ++ ++ dp = dev_ofnode(dev); ++ ++ if (ofnode_device_is_compatible(dp, "nxp,usb-isp1761")) ++ devflags |= ISP1760_FLAG_ISP1761; ++ ++ if (ofnode_device_is_compatible(dp, "nxp,usb-isp1763")) ++ devflags |= ISP1760_FLAG_ISP1763; ++ ++ /* ++ * Some systems wire up only 8 of 16 data lines or ++ * 16 of the 32 data lines ++ */ ++ bus_width = ofnode_read_u32_default(dp, "bus-width", 16); ++ if (bus_width == 16) ++ devflags |= ISP1760_FLAG_BUS_WIDTH_16; ++ else if (bus_width == 8) ++ devflags |= ISP1760_FLAG_BUS_WIDTH_8; ++ ++ if (usb_get_dr_mode(dev_ofnode(dev)) == USB_DR_MODE_PERIPHERAL) ++ devflags |= ISP1760_FLAG_PERIPHERAL_EN; ++ ++ if (ofnode_read_bool(dp, "analog-oc")) ++ devflags |= ISP1760_FLAG_ANALOG_OC; ++ ++ if (ofnode_read_bool(dp, "dack-polarity")) ++ devflags |= ISP1760_FLAG_DACK_POL_HIGH; ++ ++ if (ofnode_read_bool(dp, "dreq-polarity")) ++ devflags |= ISP1760_FLAG_DREQ_POL_HIGH; ++ ++isp_setup: ++ isp->devflags = devflags; ++ isp->dev = dev; ++ ++ return 0; ++} ++ ++static int isp1760_plat_probe(struct udevice *dev) ++{ ++ struct isp1760_device *isp = dev_get_plat(dev); ++ struct resource mem_res; ++ struct resource irq_res; ++ int ret; ++ ++ dev_read_resource(dev, 0, &mem_res); ++ dev_read_resource(dev, 1, &irq_res); ++ ++ isp1760_init_kmem_once(); ++ ++ ret = isp1760_register(isp, &mem_res, irq_res.start, irq_res.flags); ++ if (ret < 0) { ++ isp1760_deinit_kmem_cache(); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int isp1760_plat_remove(struct udevice *dev) ++{ ++ struct isp1760_device *isp = dev_get_plat(dev); ++ ++ isp1760_deinit_kmem_cache(); ++ isp1760_unregister(isp); ++ ++ return 0; ++} ++ ++static const struct udevice_id isp1760_ids[] = { ++ { .compatible = "nxp,usb-isp1760", }, ++ { .compatible = "nxp,usb-isp1761", }, ++ { .compatible = "nxp,usb-isp1763", }, ++ { }, ++}; ++ ++U_BOOT_DRIVER(isp1760) = { ++ .name = "isp1760", ++ .id = UCLASS_USB, ++ .of_match = isp1760_ids, ++ .of_to_plat = isp1760_of_to_plat, ++ .ops = &isp1760_usb_ops, ++ .probe = isp1760_plat_probe, ++ .remove = isp1760_plat_remove, ++ .plat_auto = sizeof(struct isp1760_device), ++ .priv_auto = sizeof(struct isp1760_host_data), ++}; +diff --git a/drivers/usb/isp1760/isp1760-regs.h b/drivers/usb/isp1760/isp1760-regs.h +new file mode 100644 +index 0000000000..94ea60c20b +--- /dev/null ++++ b/drivers/usb/isp1760/isp1760-regs.h +@@ -0,0 +1,292 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Driver for the NXP ISP1760 chip ++ * ++ * Copyright 2021 Linaro, Rui Miguel Silva ++ * Copyright 2014 Laurent Pinchart ++ * Copyright 2007 Sebastian Siewior ++ * ++ * Contacts: ++ * Sebastian Siewior ++ * Laurent Pinchart ++ * Rui Miguel Silva ++ */ ++ ++#ifndef _ISP176x_REGS_H_ ++#define _ISP176x_REGS_H_ ++ ++/* ----------------------------------------------------------------------------- ++ * Host Controller ++ */ ++ ++/* ISP1760/31 */ ++/* EHCI capability registers */ ++#define ISP176x_HC_VERSION 0x002 ++#define ISP176x_HC_HCSPARAMS 0x004 ++#define ISP176x_HC_HCCPARAMS 0x008 ++ ++/* EHCI operational registers */ ++#define ISP176x_HC_USBCMD 0x020 ++#define ISP176x_HC_USBSTS 0x024 ++#define ISP176x_HC_FRINDEX 0x02c ++ ++#define ISP176x_HC_CONFIGFLAG 0x060 ++#define ISP176x_HC_PORTSC1 0x064 ++ ++#define ISP176x_HC_ISO_PTD_DONEMAP 0x130 ++#define ISP176x_HC_ISO_PTD_SKIPMAP 0x134 ++#define ISP176x_HC_ISO_PTD_LASTPTD 0x138 ++#define ISP176x_HC_INT_PTD_DONEMAP 0x140 ++#define ISP176x_HC_INT_PTD_SKIPMAP 0x144 ++#define ISP176x_HC_INT_PTD_LASTPTD 0x148 ++#define ISP176x_HC_ATL_PTD_DONEMAP 0x150 ++#define ISP176x_HC_ATL_PTD_SKIPMAP 0x154 ++#define ISP176x_HC_ATL_PTD_LASTPTD 0x158 ++ ++/* Configuration Register */ ++#define ISP176x_HC_HW_MODE_CTRL 0x300 ++#define ISP176x_HC_CHIP_ID 0x304 ++#define ISP176x_HC_SCRATCH 0x308 ++#define ISP176x_HC_RESET 0x30c ++#define ISP176x_HC_BUFFER_STATUS 0x334 ++#define ISP176x_HC_MEMORY 0x33c ++ ++/* Interrupt Register */ ++#define ISP176x_HC_INTERRUPT 0x310 ++#define ISP176x_HC_INTERRUPT_ENABLE 0x314 ++#define ISP176x_HC_ISO_IRQ_MASK_OR 0x318 ++#define ISP176x_HC_INT_IRQ_MASK_OR 0x31c ++#define ISP176x_HC_ATL_IRQ_MASK_OR 0x320 ++#define ISP176x_HC_ISO_IRQ_MASK_AND 0x324 ++#define ISP176x_HC_INT_IRQ_MASK_AND 0x328 ++#define ISP176x_HC_ATL_IRQ_MASK_AND 0x32c ++ ++#define ISP176x_HC_OTG_CTRL_SET 0x374 ++#define ISP176x_HC_OTG_CTRL_CLEAR 0x376 ++ ++enum isp176x_host_controller_fields { ++ /* HC_PORTSC1 */ ++ PORT_OWNER, PORT_POWER, PORT_LSTATUS, PORT_RESET, PORT_SUSPEND, ++ PORT_RESUME, PORT_PE, PORT_CSC, PORT_CONNECT, ++ /* HC_HCSPARAMS */ ++ HCS_PPC, HCS_N_PORTS, ++ /* HC_HCCPARAMS */ ++ HCC_ISOC_CACHE, HCC_ISOC_THRES, ++ /* HC_USBCMD */ ++ CMD_LRESET, CMD_RESET, CMD_RUN, ++ /* HC_USBSTS */ ++ STS_PCD, ++ /* HC_FRINDEX */ ++ HC_FRINDEX, ++ /* HC_CONFIGFLAG */ ++ FLAG_CF, ++ /* ISO/INT/ATL PTD */ ++ HC_ISO_PTD_DONEMAP, HC_ISO_PTD_SKIPMAP, HC_ISO_PTD_LASTPTD, ++ HC_INT_PTD_DONEMAP, HC_INT_PTD_SKIPMAP, HC_INT_PTD_LASTPTD, ++ HC_ATL_PTD_DONEMAP, HC_ATL_PTD_SKIPMAP, HC_ATL_PTD_LASTPTD, ++ /* HC_HW_MODE_CTRL */ ++ ALL_ATX_RESET, HW_ANA_DIGI_OC, HW_DEV_DMA, HW_COMN_IRQ, HW_COMN_DMA, ++ HW_DATA_BUS_WIDTH, HW_DACK_POL_HIGH, HW_DREQ_POL_HIGH, HW_INTR_HIGH_ACT, ++ HW_INTF_LOCK, HW_INTR_EDGE_TRIG, HW_GLOBAL_INTR_EN, ++ /* HC_CHIP_ID */ ++ HC_CHIP_ID_HIGH, HC_CHIP_ID_LOW, HC_CHIP_REV, ++ /* HC_SCRATCH */ ++ HC_SCRATCH, ++ /* HC_RESET */ ++ SW_RESET_RESET_ATX, SW_RESET_RESET_HC, SW_RESET_RESET_ALL, ++ /* HC_BUFFER_STATUS */ ++ ISO_BUF_FILL, INT_BUF_FILL, ATL_BUF_FILL, ++ /* HC_MEMORY */ ++ MEM_BANK_SEL, MEM_START_ADDR, ++ /* HC_DATA */ ++ HC_DATA, ++ /* HC_INTERRUPT */ ++ HC_INTERRUPT, ++ /* HC_INTERRUPT_ENABLE */ ++ HC_INT_IRQ_ENABLE, HC_ATL_IRQ_ENABLE, ++ /* INTERRUPT MASKS */ ++ HC_ISO_IRQ_MASK_OR, HC_INT_IRQ_MASK_OR, HC_ATL_IRQ_MASK_OR, ++ HC_ISO_IRQ_MASK_AND, HC_INT_IRQ_MASK_AND, HC_ATL_IRQ_MASK_AND, ++ /* HW_OTG_CTRL_SET */ ++ HW_OTG_DISABLE, HW_SW_SEL_HC_DC, HW_VBUS_DRV, HW_SEL_CP_EXT, ++ HW_DM_PULLDOWN, HW_DP_PULLDOWN, HW_DP_PULLUP, HW_HC_2_DIS, ++ /* HW_OTG_CTRL_CLR */ ++ HW_OTG_DISABLE_CLEAR, HW_SW_SEL_HC_DC_CLEAR, HW_VBUS_DRV_CLEAR, ++ HW_SEL_CP_EXT_CLEAR, HW_DM_PULLDOWN_CLEAR, HW_DP_PULLDOWN_CLEAR, ++ HW_DP_PULLUP_CLEAR, HW_HC_2_DIS_CLEAR, ++ /* Last element */ ++ HC_FIELD_MAX, ++}; ++ ++/* ISP1763 */ ++/* EHCI operational registers */ ++#define ISP1763_HC_USBCMD 0x8c ++#define ISP1763_HC_USBSTS 0x90 ++#define ISP1763_HC_FRINDEX 0x98 ++ ++#define ISP1763_HC_CONFIGFLAG 0x9c ++#define ISP1763_HC_PORTSC1 0xa0 ++ ++#define ISP1763_HC_ISO_PTD_DONEMAP 0xa4 ++#define ISP1763_HC_ISO_PTD_SKIPMAP 0xa6 ++#define ISP1763_HC_ISO_PTD_LASTPTD 0xa8 ++#define ISP1763_HC_INT_PTD_DONEMAP 0xaa ++#define ISP1763_HC_INT_PTD_SKIPMAP 0xac ++#define ISP1763_HC_INT_PTD_LASTPTD 0xae ++#define ISP1763_HC_ATL_PTD_DONEMAP 0xb0 ++#define ISP1763_HC_ATL_PTD_SKIPMAP 0xb2 ++#define ISP1763_HC_ATL_PTD_LASTPTD 0xb4 ++ ++/* Configuration Register */ ++#define ISP1763_HC_HW_MODE_CTRL 0xb6 ++#define ISP1763_HC_CHIP_REV 0x70 ++#define ISP1763_HC_CHIP_ID 0x72 ++#define ISP1763_HC_SCRATCH 0x78 ++#define ISP1763_HC_RESET 0xb8 ++#define ISP1763_HC_BUFFER_STATUS 0xba ++#define ISP1763_HC_MEMORY 0xc4 ++#define ISP1763_HC_DATA 0xc6 ++ ++/* Interrupt Register */ ++#define ISP1763_HC_INTERRUPT 0xd4 ++#define ISP1763_HC_INTERRUPT_ENABLE 0xd6 ++#define ISP1763_HC_ISO_IRQ_MASK_OR 0xd8 ++#define ISP1763_HC_INT_IRQ_MASK_OR 0xda ++#define ISP1763_HC_ATL_IRQ_MASK_OR 0xdc ++#define ISP1763_HC_ISO_IRQ_MASK_AND 0xde ++#define ISP1763_HC_INT_IRQ_MASK_AND 0xe0 ++#define ISP1763_HC_ATL_IRQ_MASK_AND 0xe2 ++ ++#define ISP1763_HC_OTG_CTRL_SET 0xe4 ++#define ISP1763_HC_OTG_CTRL_CLEAR 0xe6 ++ ++/* ----------------------------------------------------------------------------- ++ * Peripheral Controller ++ */ ++ ++#define DC_IEPTX(n) (1 << (11 + 2 * (n))) ++#define DC_IEPRX(n) (1 << (10 + 2 * (n))) ++#define DC_IEPRXTX(n) (3 << (10 + 2 * (n))) ++ ++#define ISP176x_DC_CDBGMOD_ACK BIT(6) ++#define ISP176x_DC_DDBGMODIN_ACK BIT(4) ++#define ISP176x_DC_DDBGMODOUT_ACK BIT(2) ++ ++#define ISP176x_DC_IEP0SETUP BIT(8) ++#define ISP176x_DC_IEVBUS BIT(7) ++#define ISP176x_DC_IEHS_STA BIT(5) ++#define ISP176x_DC_IERESM BIT(4) ++#define ISP176x_DC_IESUSP BIT(3) ++#define ISP176x_DC_IEBRST BIT(0) ++ ++#define ISP176x_DC_ENDPTYP_ISOC 0x01 ++#define ISP176x_DC_ENDPTYP_BULK 0x02 ++#define ISP176x_DC_ENDPTYP_INTERRUPT 0x03 ++ ++/* Initialization Registers */ ++#define ISP176x_DC_ADDRESS 0x0200 ++#define ISP176x_DC_MODE 0x020c ++#define ISP176x_DC_INTCONF 0x0210 ++#define ISP176x_DC_DEBUG 0x0212 ++#define ISP176x_DC_INTENABLE 0x0214 ++ ++/* Data Flow Registers */ ++#define ISP176x_DC_EPMAXPKTSZ 0x0204 ++#define ISP176x_DC_EPTYPE 0x0208 ++ ++#define ISP176x_DC_BUFLEN 0x021c ++#define ISP176x_DC_BUFSTAT 0x021e ++#define ISP176x_DC_DATAPORT 0x0220 ++ ++#define ISP176x_DC_CTRLFUNC 0x0228 ++#define ISP176x_DC_EPINDEX 0x022c ++ ++/* DMA Registers */ ++#define ISP176x_DC_DMACMD 0x0230 ++#define ISP176x_DC_DMATXCOUNT 0x0234 ++#define ISP176x_DC_DMACONF 0x0238 ++#define ISP176x_DC_DMAHW 0x023c ++#define ISP176x_DC_DMAINTREASON 0x0250 ++#define ISP176x_DC_DMAINTEN 0x0254 ++#define ISP176x_DC_DMAEP 0x0258 ++#define ISP176x_DC_DMABURSTCOUNT 0x0264 ++ ++/* General Registers */ ++#define ISP176x_DC_INTERRUPT 0x0218 ++#define ISP176x_DC_CHIPID 0x0270 ++#define ISP176x_DC_FRAMENUM 0x0274 ++#define ISP176x_DC_SCRATCH 0x0278 ++#define ISP176x_DC_UNLOCKDEV 0x027c ++#define ISP176x_DC_INTPULSEWIDTH 0x0280 ++#define ISP176x_DC_TESTMODE 0x0284 ++ ++enum isp176x_device_controller_fields { ++ /* DC_ADDRESS */ ++ DC_DEVEN, DC_DEVADDR, ++ /* DC_MODE */ ++ DC_VBUSSTAT, DC_SFRESET, DC_GLINTENA, ++ /* DC_INTCONF */ ++ DC_CDBGMOD_ACK, DC_DDBGMODIN_ACK, DC_DDBGMODOUT_ACK, DC_INTPOL, ++ /* DC_INTENABLE */ ++ DC_IEPRXTX_7, DC_IEPRXTX_6, DC_IEPRXTX_5, DC_IEPRXTX_4, DC_IEPRXTX_3, ++ DC_IEPRXTX_2, DC_IEPRXTX_1, DC_IEPRXTX_0, ++ DC_IEP0SETUP, DC_IEVBUS, DC_IEHS_STA, DC_IERESM, DC_IESUSP, DC_IEBRST, ++ /* DC_EPINDEX */ ++ DC_EP0SETUP, DC_ENDPIDX, DC_EPDIR, ++ /* DC_CTRLFUNC */ ++ DC_CLBUF, DC_VENDP, DC_DSEN, DC_STATUS, DC_STALL, ++ /* DC_BUFLEN */ ++ DC_BUFLEN, ++ /* DC_EPMAXPKTSZ */ ++ DC_FFOSZ, ++ /* DC_EPTYPE */ ++ DC_EPENABLE, DC_ENDPTYP, ++ /* DC_FRAMENUM */ ++ DC_FRAMENUM, DC_UFRAMENUM, ++ /* DC_CHIP_ID */ ++ DC_CHIP_ID_HIGH, DC_CHIP_ID_LOW, ++ /* DC_SCRATCH */ ++ DC_SCRATCH, ++ /* Last element */ ++ DC_FIELD_MAX, ++}; ++ ++/* ISP1763 */ ++/* Initialization Registers */ ++#define ISP1763_DC_ADDRESS 0x00 ++#define ISP1763_DC_MODE 0x0c ++#define ISP1763_DC_INTCONF 0x10 ++#define ISP1763_DC_INTENABLE 0x14 ++ ++/* Data Flow Registers */ ++#define ISP1763_DC_EPMAXPKTSZ 0x04 ++#define ISP1763_DC_EPTYPE 0x08 ++ ++#define ISP1763_DC_BUFLEN 0x1c ++#define ISP1763_DC_BUFSTAT 0x1e ++#define ISP1763_DC_DATAPORT 0x20 ++ ++#define ISP1763_DC_CTRLFUNC 0x28 ++#define ISP1763_DC_EPINDEX 0x2c ++ ++/* DMA Registers */ ++#define ISP1763_DC_DMACMD 0x30 ++#define ISP1763_DC_DMATXCOUNT 0x34 ++#define ISP1763_DC_DMACONF 0x38 ++#define ISP1763_DC_DMAHW 0x3c ++#define ISP1763_DC_DMAINTREASON 0x50 ++#define ISP1763_DC_DMAINTEN 0x54 ++#define ISP1763_DC_DMAEP 0x58 ++#define ISP1763_DC_DMABURSTCOUNT 0x64 ++ ++/* General Registers */ ++#define ISP1763_DC_INTERRUPT 0x18 ++#define ISP1763_DC_CHIPID_LOW 0x70 ++#define ISP1763_DC_CHIPID_HIGH 0x72 ++#define ISP1763_DC_FRAMENUM 0x74 ++#define ISP1763_DC_SCRATCH 0x78 ++#define ISP1763_DC_UNLOCKDEV 0x7c ++#define ISP1763_DC_INTPULSEWIDTH 0x80 ++#define ISP1763_DC_TESTMODE 0x84 ++ ++#endif +diff --git a/drivers/usb/isp1760/isp1760-uboot.c b/drivers/usb/isp1760/isp1760-uboot.c +new file mode 100644 +index 0000000000..9f2eaa75f3 +--- /dev/null ++++ b/drivers/usb/isp1760/isp1760-uboot.c +@@ -0,0 +1,64 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Driver for the NXP ISP1760 chip ++ * ++ * Copyright 2021 Linaro, Rui Miguel Silva ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "isp1760-core.h" ++#include "isp1760-hcd.h" ++#include "isp1760-regs.h" ++#include "isp1760-uboot.h" ++ ++static int isp1760_msg_submit_control(struct udevice *dev, ++ struct usb_device *udev, ++ unsigned long pipe, void *buffer, ++ int length, struct devrequest *setup) ++{ ++ struct isp1760_host_data *host = dev_get_priv(dev); ++ ++ return usb_urb_submit_control(&host->hcd, &host->urb, &host->hep, udev, ++ pipe, buffer, length, setup, 0, ++ host->host_speed); ++} ++ ++static int isp1760_msg_submit_bulk(struct udevice *dev, struct usb_device *udev, ++ unsigned long pipe, void *buffer, int length) ++{ ++ struct isp1760_host_data *host = dev_get_priv(dev); ++ ++ return usb_urb_submit_bulk(&host->hcd, &host->urb, &host->hep, udev, ++ pipe, buffer, length); ++} ++ ++static int isp1760_msg_submit_irq(struct udevice *dev, struct usb_device *udev, ++ unsigned long pipe, void *buffer, int length, ++ int interval, bool nonblock) ++{ ++ struct isp1760_host_data *host = dev_get_priv(dev); ++ ++ return usb_urb_submit_irq(&host->hcd, &host->urb, &host->hep, udev, ++ pipe, buffer, length, interval); ++} ++ ++struct dm_usb_ops isp1760_usb_ops = { ++ .control = isp1760_msg_submit_control, ++ .bulk = isp1760_msg_submit_bulk, ++ .interrupt = isp1760_msg_submit_irq, ++}; ++ +diff --git a/drivers/usb/isp1760/isp1760-uboot.h b/drivers/usb/isp1760/isp1760-uboot.h +new file mode 100644 +index 0000000000..2486de6f9e +--- /dev/null ++++ b/drivers/usb/isp1760/isp1760-uboot.h +@@ -0,0 +1,27 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Driver for the NXP ISP1760 chip ++ * ++ * Copyright 2021 Linaro, Rui Miguel Silva ++ * ++ */ ++ ++#ifndef __ISP1760_UBOOT_H__ ++#define __ISP1760_UBOOT_H__ ++ ++#include ++#include ++ ++#include "isp1760-core.h" ++ ++struct isp1760_host_data { ++ struct isp1760_hcd *priv; ++ struct usb_hcd hcd; ++ enum usb_device_speed host_speed; ++ struct usb_host_endpoint hep; ++ struct urb urb; ++}; ++ ++extern struct dm_usb_ops isp1760_usb_ops; ++ ++#endif +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0005-corstone1000-enable-isp1763-and-usb-stack.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0005-corstone1000-enable-isp1763-and-usb-stack.patch new file mode 100644 index 0000000..2e41677 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0005-corstone1000-enable-isp1763-and-usb-stack.patch @@ -0,0 +1,92 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From 663bfde59a56d65c031526f75f0e08126f02d845 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Tue, 27 Jul 2021 23:34:57 +0100 +Subject: [PATCH 05/16] corstone1000: enable isp1763 and usb stack + +MPS3 board have a ISP1763 usb controller, add the correspondent mmio +area and enable it to be used for mass storage access for example. + +Signed-off-by: Rui Miguel Silva +--- + board/armltd/corstone1000/corstone1000.c | 8 ++++++++ + configs/corstone1000_defconfig | 19 +++++++++---------- + 2 files changed, 17 insertions(+), 10 deletions(-) + +diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c +index ab98fa87fb..a51f5ddfa0 100644 +--- a/board/armltd/corstone1000/corstone1000.c ++++ b/board/armltd/corstone1000/corstone1000.c +@@ -46,6 +46,14 @@ static struct mm_region corstone1000_mem_map[] = { + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN ++ }, { ++ /* USB */ ++ .virt = 0x40200000UL, ++ .phys = 0x40200000UL, ++ .size = 0x00100000UL, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | ++ PTE_BLOCK_NON_SHARE | ++ PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OCVM */ + .virt = 0x80000000UL, +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index 54c746d829..fed2b16c93 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -1,13 +1,12 @@ + CONFIG_ARM=y +-CONFIG_ARM64=y + CONFIG_TARGET_CORSTONE1000=y + CONFIG_SYS_TEXT_BASE=0x02100000 + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_IDENT_STRING=" corstone1000 aarch64 " +-CONFIG_BOOTDELAY=3 +-CONFIG_OF_CONTROL=y + CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3" ++CONFIG_FIT=y ++CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9" + # CONFIG_DISPLAY_CPUINFO is not set +@@ -16,12 +15,11 @@ CONFIG_HUSH_PARSER=y + CONFIG_SYS_PROMPT="corstone1000# " + # CONFIG_CMD_CONSOLE is not set + CONFIG_CMD_BOOTZ=y +-CONFIG_CMD_BOOTM=y + # CONFIG_CMD_XIMG is not set + # CONFIG_CMD_EDITENV is not set + # CONFIG_CMD_ENV_EXISTS is not set +-# CONFIG_CMD_ARMFLASH=y + # CONFIG_CMD_LOADS is not set ++CONFIG_CMD_USB=y + # CONFIG_CMD_ITEST is not set + # CONFIG_CMD_SETEXPR is not set + CONFIG_CMD_DHCP=y +@@ -29,12 +27,13 @@ CONFIG_CMD_DHCP=y + CONFIG_CMD_MII=y + CONFIG_CMD_PING=y + CONFIG_CMD_CACHE=y +-CONFIG_FIT=y +-# CONFIG_CMD_MISC is not set + CONFIG_CMD_FAT=y +-CONFIG_DM=y ++CONFIG_OF_CONTROL=y ++CONFIG_REGMAP=y + # CONFIG_MMC is not set +-# CONFIG_MTD_NOR_FLASH=y + CONFIG_DM_ETH=y + CONFIG_DM_SERIAL=y +-CONFIG_OF_LIBFDT=y ++CONFIG_USB=y ++CONFIG_DM_USB=y ++CONFIG_USB_ISP1760=y ++CONFIG_USB_STORAGE=y +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0006-corstone1000-enable-support-for-FVP.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0006-corstone1000-enable-support-for-FVP.patch new file mode 100644 index 0000000..38e77dc --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0006-corstone1000-enable-support-for-FVP.patch @@ -0,0 +1,240 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From 8244c266643d7fe77e360d2927adcd123a691dd1 Mon Sep 17 00:00:00 2001 +From: "Arpita S.K" +Date: Mon, 11 Oct 2021 11:41:25 +0530 +Subject: [PATCH 06/16] corstone1000: enable support for FVP + +Introduces a new device tree for the FVP. + +Signed-off-by: Arpita S.K +--- + arch/arm/dts/Makefile | 2 + + arch/arm/dts/corstone1000-fvp.dts | 28 ++++++ + arch/arm/dts/corstone1000.dtsi | 152 ++++++++++++++++++++++++++++++ + configs/corstone1000_defconfig | 1 - + 4 files changed, 182 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/dts/corstone1000-fvp.dts + create mode 100644 arch/arm/dts/corstone1000.dtsi + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 9fb38682e6..c70c20b9a5 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -1112,6 +1112,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb + + dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb + ++dtb-$(CONFIG_TARGET_CORSTONE1000) += $(DEVICE_TREE).dtb ++ + targets += $(dtb-y) + + # Add any required device tree compiler flags here +diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts +new file mode 100644 +index 0000000000..2188ca5e0e +--- /dev/null ++++ b/arch/arm/dts/corstone1000-fvp.dts +@@ -0,0 +1,28 @@ ++/* ++ * Copyright (c) 2021, Arm Limited. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++/dts-v1/; ++ ++#include "corstone1000.dtsi" ++ ++/ { ++ model = "corstone1000-fvp"; ++ ++ ethernet: eth@4010000 { ++ compatible = "smsc,lan91c111"; ++ reg = <0x40100000 0x10000>; ++ phy-mode = "mii"; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ reg-io-width = <2>; ++ smsc,irq-push-pull; ++ }; ++ ++}; ++ ++&refclk { ++ clock-frequency = <50000000>; ++}; +diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi +new file mode 100644 +index 0000000000..b863193fb6 +--- /dev/null ++++ b/arch/arm/dts/corstone1000.dtsi +@@ -0,0 +1,152 @@ ++/* ++ * Copyright (c) 2021, Arm Limited. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++ ++/ { ++ compatible = "arm,corstone1000"; ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ chosen { }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,armv8"; ++ reg = <0>; ++ next-level-cache = <&L2_0>; ++ }; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x80000000 0x80000000>; ++ }; ++ ++ gic: interrupt-controller@1c000000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ #address-cells = <0>; ++ interrupt-controller; ++ reg = <0x1c010000 0x1000>, ++ <0x1c02f000 0x2000>, ++ <0x1c04f000 0x1000>, ++ <0x1c06f000 0x2000>; ++ interrupts = <1 9 0xf08>; ++ }; ++ ++ L2_0: l2-cache0 { ++ compatible = "cache"; ++ }; ++ ++ refclk100mhz: refclk100mhz { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <100000000>; ++ clock-output-names = "apb_pclk"; ++ }; ++ ++ smbclk: refclk24mhzx2 { ++ /* Reference 24MHz clock x 2 */ ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <48000000>; ++ clock-output-names = "smclk"; ++ }; ++ ++ uartclk: uartclk { ++ /* UART clock - 50MHz */ ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <50000000>; ++ clock-output-names = "uartclk"; ++ }; ++ ++ serial0: uart@1a510000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x1a510000 0x1000>; ++ interrupt-parent = <&gic>; ++ interrupts = <0 19 4>; ++ clocks = <&uartclk>, <&refclk100mhz>; ++ clock-names = "uartclk", "apb_pclk"; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <1 13 0xf08>, ++ <1 14 0xf08>, ++ <1 11 0xf08>, ++ <1 10 0xf08>; ++ }; ++ ++ refclk: refclk@1a220000 { ++ compatible = "arm,armv7-timer-mem"; ++ reg = <0x1a220000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ frame@1a230000 { ++ frame-number = <0>; ++ interrupts = <0 2 0xf04>; ++ reg = <0x1a230000 0x1000>; ++ }; ++ }; ++ ++ mbox_es0mhu0: mhu@1b000000 { ++ compatible = "arm,mhuv2","arm,primecell"; ++ reg = <0x1b000000 0x1000>, ++ <0x1b010000 0x1000>; ++ clocks = <&refclk100mhz>; ++ clock-names = "apb_pclk"; ++ interrupts = <0 12 4>; ++ interrupt-names = "mhu_rx"; ++ #mbox-cells = <1>; ++ mbox-name = "arm-es0-mhu0"; ++ }; ++ ++ mbox_es0mhu1: mhu@1b020000 { ++ compatible = "arm,mhuv2","arm,primecell"; ++ reg = <0x1b020000 0x1000>, ++ <0x1b030000 0x1000>; ++ clocks = <&refclk100mhz>; ++ clock-names = "apb_pclk"; ++ interrupts = <0 47 4>; ++ interrupt-names = "mhu_rx"; ++ #mbox-cells = <1>; ++ mbox-name = "arm-es0-mhu1"; ++ }; ++ ++ mbox_semhu1: mhu@1b820000 { ++ compatible = "arm,mhuv2","arm,primecell"; ++ reg = <0x1b820000 0x1000>, ++ <0x1b830000 0x1000>; ++ clocks = <&refclk100mhz>; ++ clock-names = "apb_pclk"; ++ interrupts = <0 45 4>; ++ interrupt-names = "mhu_rx"; ++ #mbox-cells = <1>; ++ mbox-name = "arm-se-mhu1"; ++ }; ++ ++ client { ++ compatible = "arm,client"; ++ mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>; ++ mbox-names = "es0mhu0", "es0mhu1", "semhu1"; ++ }; ++ ++ extsys0: extsys@1A010310 { ++ compatible = "arm,extsys_ctrl"; ++ reg = <0x1A010310 0x4>, ++ <0x1A010314 0x4>; ++ reg-names = "rstreg", "streg"; ++ }; ++}; +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index fed2b16c93..c7f291efb6 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x02100000 + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_IDENT_STRING=" corstone1000 aarch64 " +-CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3" + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0007-arm-corstone1000-sharing-PSCI-DTS-node-between-FVP-a.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0007-arm-corstone1000-sharing-PSCI-DTS-node-between-FVP-a.patch new file mode 100644 index 0000000..3ed5529 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0007-arm-corstone1000-sharing-PSCI-DTS-node-between-FVP-a.patch @@ -0,0 +1,34 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From b50c1457fcd05cddf633bff074fc5edecff22e7e Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi +Date: Wed, 25 Aug 2021 16:50:40 +0100 +Subject: [PATCH 07/16] arm: corstone1000: sharing PSCI DTS node between FVP + and MPS3 + +At this level of development PSCI is needed to initialize the SMCCC. + +SMCCC is needed by FF-A and it is relevant to the MPS3 and FVP. + +Signed-off-by: Abdellatif El Khlifi +--- + arch/arm/dts/corstone1000.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi +index b863193fb6..da1725e01f 100644 +--- a/arch/arm/dts/corstone1000.dtsi ++++ b/arch/arm/dts/corstone1000.dtsi +@@ -149,4 +149,8 @@ + <0x1A010314 0x4>; + reg-names = "rstreg", "streg"; + }; ++ psci { ++ compatible = "arm,psci-1.0", "arm,psci-0.2"; ++ method = "smc"; ++ }; + }; +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0008-arm-corstone1000-Emulated-RTC-Support.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0008-arm-corstone1000-Emulated-RTC-Support.patch new file mode 100644 index 0000000..ba01fe5 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0008-arm-corstone1000-Emulated-RTC-Support.patch @@ -0,0 +1,32 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From 9a045bf04210bf9a00803fc47016e1af59d31e8f Mon Sep 17 00:00:00 2001 +From: "Arpita S.K" +Date: Mon, 11 Oct 2021 11:45:41 +0530 +Subject: [PATCH 08/16] arm: corstone1000: Emulated RTC Support + +This patch adds the options that should be +enabled to turn on emulated RTC support. + +Signed-off-by: Arpita S.K +--- + configs/corstone1000_defconfig | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index c7f291efb6..dbe3c9e3f3 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -36,3 +36,8 @@ CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_USB_ISP1760=y + CONFIG_USB_STORAGE=y ++CONFIG_DM_RTC=y ++CONFIG_CMD_RTC=y ++CONFIG_EFI_GET_TIME=y ++CONFIG_EFI_SET_TIME=y ++CONFIG_RTC_EMULATION=y +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0009-arm-corstone1000-execute-uboot-from-DDR.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0009-arm-corstone1000-execute-uboot-from-DDR.patch new file mode 100644 index 0000000..b004e1b --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0009-arm-corstone1000-execute-uboot-from-DDR.patch @@ -0,0 +1,31 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From b720b166364407ceb05385f5e72cb238195622ad Mon Sep 17 00:00:00 2001 +From: Vishnu Banavath +Date: Wed, 1 Sep 2021 18:33:32 +0100 +Subject: [PATCH 09/16] arm: corstone1000: execute uboot from DDR + +Previously uboot was executing from CVM. With the addition of +secure partitions in optee, uboot has been moved to DDR. + +Signed-off-by: Vishnu Banavath +--- + configs/corstone1000_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index dbe3c9e3f3..af1c5ecd89 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -1,6 +1,6 @@ + CONFIG_ARM=y + CONFIG_TARGET_CORSTONE1000=y +-CONFIG_SYS_TEXT_BASE=0x02100000 ++CONFIG_SYS_TEXT_BASE=0x80000000 + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_IDENT_STRING=" corstone1000 aarch64 " +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend index e4746de..30a6f7f 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend @@ -2,6 +2,27 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" +# +# Corstone1000 64-bit machines +# + +CORSTONE1000_DEVICE_TREE:corstone1000-fvp = "corstone1000-fvp" +EXTRA_OEMAKE:append:corstone1000 = ' DEVICE_TREE=${CORSTONE1000_DEVICE_TREE}' + +SYSROOT_DIRS:append:corstone1000 = " /boot" + +SRC_URI:append:corstone1000 = " \ + file://0001-arm-add-corstone1000-platform.patch \ + file://0002-arm-corstone1000-enable-devicetree-in-defconfig.patch \ + file://0003-usb-common-move-urb-code-to-common.patch \ + file://0004-usb-add-isp1760-family-driver.patch \ + file://0005-corstone1000-enable-isp1763-and-usb-stack.patch \ + file://0006-corstone1000-enable-support-for-FVP.patch \ + file://0007-arm-corstone1000-sharing-PSCI-DTS-node-between-FVP-a.patch \ + file://0008-arm-corstone1000-Emulated-RTC-Support.patch \ + file://0009-arm-corstone1000-execute-uboot-from-DDR.patch \ + " + # # FVP BASE # From patchwork Tue Nov 23 15:59:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 286E8C4332F for ; Tue, 23 Nov 2021 16:00:01 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.13038.1637683200496945256 for ; Tue, 23 Nov 2021 08:00:00 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BA921FB; Tue, 23 Nov 2021 08:00:00 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A5E1A3F5A1; Tue, 23 Nov 2021 07:59:58 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Abdellatif El Khlifi , Jon Mason Subject: [PATCH][honister 10/19] arm-bsp/trusted-firmware-a: introducing corstone1000 FVP machine Date: Tue, 23 Nov 2021 15:59:17 +0000 Message-Id: <20211123155926.31743-11-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:01 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2439 From: Abdellatif El Khlifi This commit enables TF-A v2.5 with Trusted Board Boot support for the Corstone1000 64-bit platform. Disables Non-Volatile counters in the TBB. Change-Id: Idb9e18df7066cb617df72b2e147147ce49db292c Signed-off-by: Arpita S.K Signed-off-by: Abdellatif El Khlifi Signed-off-by: Vishnu Banavath Signed-off-by: Jon Mason --- .../conf/machine/include/corstone1000.inc | 5 + .../0001-Rename-Diphda-to-corstone1000.patch | 587 ++++++++++++++++++ ...e1000-made-changes-to-accommodate-3M.patch | 201 ++++++ .../trusted-firmware-a-corstone1000.inc | 47 ++ .../trusted-firmware-a_2.5.bbappend | 1 + 5 files changed, 841 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0001-Rename-Diphda-to-corstone1000.patch create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-plat-arm-corstone1000-made-changes-to-accommodate-3M.patch create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc diff --git a/meta-arm-bsp/conf/machine/include/corstone1000.inc b/meta-arm-bsp/conf/machine/include/corstone1000.inc index 2c2293f..a673e6b 100644 --- a/meta-arm-bsp/conf/machine/include/corstone1000.inc +++ b/meta-arm-bsp/conf/machine/include/corstone1000.inc @@ -2,6 +2,11 @@ require conf/machine/include/arm/armv8a/tune-cortexa35.inc MACHINEOVERRIDES =. "corstone1000:" +# TF-A +TFA_PLATFORM = "corstone1000" +PREFERRED_VERSION_trusted-firmware-a ?= "2.5%" +EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-a" + # TF-M PREFERRED_VERSION_trusted-firmware-m ?= "1.4%" TFM_PLATFORM = "arm/corstone1000" diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0001-Rename-Diphda-to-corstone1000.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0001-Rename-Diphda-to-corstone1000.patch new file mode 100644 index 0000000..47eb4e0 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0001-Rename-Diphda-to-corstone1000.patch @@ -0,0 +1,587 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From b4d59c85d1045998275cd219efe5849803c2c616 Mon Sep 17 00:00:00 2001 +From: "Arpita S.K" +Date: Wed, 13 Oct 2021 18:05:11 +0530 +Subject: [PATCH] Rename Diphda to corstone1000 + +Replace all the instances of Diphda as functions, +macros etc. with corstone1000 + +Signed-off-by: Arpita S.K +--- + docs/about/maintainers.rst | 2 +- + .../arm/{diphda => corstone1000}/index.rst | 6 +- + docs/plat/arm/index.rst | 2 +- + plat/arm/board/common/rotpk/arm_dev_rotpk.S | 2 +- + .../corstone1000_bl2_mem_params_desc.c} | 8 +- + .../common/corstone1000_err.c} | 2 +- + .../common/corstone1000_helpers.S} | 4 +- + .../common/corstone1000_plat.c} | 6 +- + .../common/corstone1000_pm.c} | 0 + .../common/corstone1000_security.c} | 0 + .../common/corstone1000_stack_protector.c} | 0 + .../common/corstone1000_topology.c} | 12 +-- + .../common/corstone1000_trusted_boot.c} | 2 +- + .../fdts/corstone1000_spmc_manifest.dts} | 0 + .../common/include/platform_def.h | 52 ++++++------ + .../include/plat_macros.S | 0 + plat/arm/board/corstone1000/platform.mk | 83 +++++++++++++++++++ + plat/arm/board/diphda/platform.mk | 83 ------------------- + 18 files changed, 132 insertions(+), 132 deletions(-) + rename docs/plat/arm/{diphda => corstone1000}/index.rst (93%) + rename plat/arm/board/{diphda/common/diphda_bl2_mem_params_desc.c => corstone1000/common/corstone1000_bl2_mem_params_desc.c} (92%) + rename plat/arm/board/{diphda/common/diphda_err.c => corstone1000/common/corstone1000_err.c} (89%) + rename plat/arm/board/{diphda/common/diphda_helpers.S => corstone1000/common/corstone1000_helpers.S} (94%) + rename plat/arm/board/{diphda/common/diphda_plat.c => corstone1000/common/corstone1000_plat.c} (92%) + rename plat/arm/board/{diphda/common/diphda_pm.c => corstone1000/common/corstone1000_pm.c} (100%) + rename plat/arm/board/{diphda/common/diphda_security.c => corstone1000/common/corstone1000_security.c} (100%) + rename plat/arm/board/{diphda/common/diphda_stack_protector.c => corstone1000/common/corstone1000_stack_protector.c} (100%) + rename plat/arm/board/{diphda/common/diphda_topology.c => corstone1000/common/corstone1000_topology.c} (77%) + rename plat/arm/board/{diphda/common/diphda_trusted_boot.c => corstone1000/common/corstone1000_trusted_boot.c} (97%) + rename plat/arm/board/{diphda/common/fdts/diphda_spmc_manifest.dts => corstone1000/common/fdts/corstone1000_spmc_manifest.dts} (100%) + rename plat/arm/board/{diphda => corstone1000}/common/include/platform_def.h (89%) + rename plat/arm/board/{diphda => corstone1000}/include/plat_macros.S (100%) + create mode 100644 plat/arm/board/corstone1000/platform.mk + delete mode 100644 plat/arm/board/diphda/platform.mk + +diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst +index 07f258c774..2d9eb1440d 100644 +--- a/docs/about/maintainers.rst ++++ b/docs/about/maintainers.rst +@@ -399,7 +399,7 @@ Arm Rich IoT Platform ports + :|G|: `vishnu-banavath`_ + :|F|: plat/arm/board/corstone700 + :|F|: plat/arm/board/a5ds +-:|F|: plat/arm/board/diphda ++:|F|: plat/arm/board/corstone1000 + + Arm Reference Design platform ports + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +diff --git a/docs/plat/arm/diphda/index.rst b/docs/plat/arm/corstone1000/index.rst +similarity index 93% +rename from docs/plat/arm/diphda/index.rst +rename to docs/plat/arm/corstone1000/index.rst +index 27afda43f5..b889b7f2e9 100644 +--- a/docs/plat/arm/diphda/index.rst ++++ b/docs/plat/arm/corstone1000/index.rst +@@ -1,7 +1,7 @@ +-Diphda Platform ++Corstone1000 Platform + ========================== + +-Some of the features of the Diphda platform referenced in TF-A include: ++Some of the features of the Corstone1000 platform referenced in TF-A include: + + - Cortex-A35 application processor (64-bit mode) + - Secure Enclave +@@ -37,7 +37,7 @@ Build Procedure (TF-A only) + CC=aarch64-none-elf-gcc \ + V=1 \ + BUILD_BASE= \ +- PLAT=diphda \ ++ PLAT=corstone1000 \ + SPD=spmd \ + SPMD_SPM_AT_SEL2=0 \ + DEBUG=1 \ +diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst +index c834f6ae70..23c561ff57 100644 +--- a/docs/plat/arm/index.rst ++++ b/docs/plat/arm/index.rst +@@ -12,7 +12,7 @@ Arm Development Platforms + arm_fpga/index + arm-build-options + morello/index +- diphda/index ++ corstone1000/index + + This chapter holds documentation related to Arm's development platforms, + including both software models (FVPs) and hardware development boards +diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S +index 38f91fe5f8..125ddf67c7 100644 +--- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S ++++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S +@@ -4,7 +4,7 @@ + * SPDX-License-Identifier: BSD-3-Clause + */ + +-/* diphda platform provides custom values for the macros defined in ++/* corstone1000 platform provides custom values for the macros defined in + * arm_def.h , so only platform_def.h needs to be included + */ + #if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA) +diff --git a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c +similarity index 92% +rename from plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c +rename to plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c +index 916c868d21..7baa82d31b 100644 +--- a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c ++++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c +@@ -44,7 +44,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, +- .ep_info.args.arg0 = DIPHDA_TOS_FW_CONFIG_BASE, ++ .ep_info.args.arg0 = CORSTONE1000_TOS_FW_CONFIG_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, +@@ -56,9 +56,9 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { + /* Fill TOS_FW_CONFIG related information */ + { + .image_id = TOS_FW_CONFIG_ID, +- .image_info.image_base = DIPHDA_TOS_FW_CONFIG_BASE, +- .image_info.image_max_size = DIPHDA_TOS_FW_CONFIG_LIMIT - \ +- DIPHDA_TOS_FW_CONFIG_BASE, ++ .image_info.image_base = CORSTONE1000_TOS_FW_CONFIG_BASE, ++ .image_info.image_max_size = CORSTONE1000_TOS_FW_CONFIG_LIMIT - \ ++ CORSTONE1000_TOS_FW_CONFIG_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, +diff --git a/plat/arm/board/diphda/common/diphda_err.c b/plat/arm/board/corstone1000/common/corstone1000_err.c +similarity index 89% +rename from plat/arm/board/diphda/common/diphda_err.c +rename to plat/arm/board/corstone1000/common/corstone1000_err.c +index 89a3b8249c..5f8e7da437 100644 +--- a/plat/arm/board/diphda/common/diphda_err.c ++++ b/plat/arm/board/corstone1000/common/corstone1000_err.c +@@ -7,7 +7,7 @@ + #include + + /* +- * diphda error handler ++ * corstone1000 error handler + */ + void __dead2 plat_arm_error_handler(int err) + { +diff --git a/plat/arm/board/diphda/common/diphda_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S +similarity index 94% +rename from plat/arm/board/diphda/common/diphda_helpers.S +rename to plat/arm/board/corstone1000/common/corstone1000_helpers.S +index c9d2a88de9..87122270b0 100644 +--- a/plat/arm/board/diphda/common/diphda_helpers.S ++++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S +@@ -29,7 +29,7 @@ endfunc plat_secondary_cold_boot_setup + * unsigned long plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and warm +- * boot. On diphda, this information can be queried from the power ++ * boot. On corstone1000, this information can be queried from the power + * controller. The Power Control SYS Status Register (PSYSR) indicates + * the wake-up reason for the CPU. + * +@@ -61,7 +61,7 @@ func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + mov_imm x1, MPIDR_AFFINITY_MASK + and x0, x0, x1 +- cmp x0, #DIPHDA_PRIMARY_CPU ++ cmp x0, #CORSTONE1000_PRIMARY_CPU + cset w0, eq + ret + endfunc plat_is_my_cpu_primary +diff --git a/plat/arm/board/diphda/common/diphda_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c +similarity index 92% +rename from plat/arm/board/diphda/common/diphda_plat.c +rename to plat/arm/board/corstone1000/common/corstone1000_plat.c +index 28d15a59e6..7a38b0b2ee 100644 +--- a/plat/arm/board/diphda/common/diphda_plat.c ++++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c +@@ -21,12 +21,12 @@ const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + ARM_MAP_NS_SHARED_RAM, + ARM_MAP_NS_DRAM1, +- DIPHDA_MAP_DEVICE, +- DIPHDA_EXTERNAL_FLASH, ++ CORSTONE1000_MAP_DEVICE, ++ CORSTONE1000_EXTERNAL_FLASH, + {0} + }; + +-/* diphda only has one always-on power domain and there ++/* corstone1000 only has one always-on power domain and there + * is no power control present + */ + void __init plat_arm_pwrc_setup(void) +diff --git a/plat/arm/board/diphda/common/diphda_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c +similarity index 100% +rename from plat/arm/board/diphda/common/diphda_pm.c +rename to plat/arm/board/corstone1000/common/corstone1000_pm.c +diff --git a/plat/arm/board/diphda/common/diphda_security.c b/plat/arm/board/corstone1000/common/corstone1000_security.c +similarity index 100% +rename from plat/arm/board/diphda/common/diphda_security.c +rename to plat/arm/board/corstone1000/common/corstone1000_security.c +diff --git a/plat/arm/board/diphda/common/diphda_stack_protector.c b/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c +similarity index 100% +rename from plat/arm/board/diphda/common/diphda_stack_protector.c +rename to plat/arm/board/corstone1000/common/corstone1000_stack_protector.c +diff --git a/plat/arm/board/diphda/common/diphda_topology.c b/plat/arm/board/corstone1000/common/corstone1000_topology.c +similarity index 77% +rename from plat/arm/board/diphda/common/diphda_topology.c +rename to plat/arm/board/corstone1000/common/corstone1000_topology.c +index 9dfd05d091..2a3b6913a1 100644 +--- a/plat/arm/board/diphda/common/diphda_topology.c ++++ b/plat/arm/board/corstone1000/common/corstone1000_topology.c +@@ -7,8 +7,8 @@ + #include + #include + +-/* The diphda power domain tree descriptor */ +-static unsigned char diphda_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT ++/* The corstone1000 power domain tree descriptor */ ++static unsigned char corstone1000_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT + + 2]; + /******************************************************************************* + * This function dynamically constructs the topology according to +@@ -22,13 +22,13 @@ const unsigned char *plat_get_power_domain_tree_desc(void) + * The highest level is the system level. The next level is constituted + * by clusters and then cores in clusters. + */ +- diphda_power_domain_tree_desc[0] = 1; +- diphda_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT; ++ corstone1000_power_domain_tree_desc[0] = 1; ++ corstone1000_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT; + + for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++) +- diphda_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; ++ corstone1000_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; + +- return diphda_power_domain_tree_desc; ++ return corstone1000_power_domain_tree_desc; + } + + /****************************************************************************** +diff --git a/plat/arm/board/diphda/common/diphda_trusted_boot.c b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c +similarity index 97% +rename from plat/arm/board/diphda/common/diphda_trusted_boot.c +rename to plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c +index ddb41faa6b..2e2e9475a5 100644 +--- a/plat/arm/board/diphda/common/diphda_trusted_boot.c ++++ b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c +@@ -38,7 +38,7 @@ int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + */ + int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) + { +- *nv_ctr = DIPHDA_FW_NVCTR_VAL; ++ *nv_ctr = CORSTONE1000_FW_NVCTR_VAL; + return 0; + } + +diff --git a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts b/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts +similarity index 100% +rename from plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts +rename to plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts +diff --git a/plat/arm/board/diphda/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h +similarity index 89% +rename from plat/arm/board/diphda/common/include/platform_def.h +rename to plat/arm/board/corstone1000/common/include/platform_def.h +index 37fd71b6aa..e36bb626ee 100644 +--- a/plat/arm/board/diphda/common/include/platform_def.h ++++ b/plat/arm/board/corstone1000/common/include/platform_def.h +@@ -34,17 +34,17 @@ + #define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000 + #define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000 + +-/* Core/Cluster/Thread counts for diphda */ +-#define DIPHDA_CLUSTER_COUNT U(1) +-#define DIPHDA_MAX_CPUS_PER_CLUSTER U(4) +-#define DIPHDA_MAX_PE_PER_CPU U(1) +-#define DIPHDA_PRIMARY_CPU U(0) ++/* Core/Cluster/Thread counts for corstone1000 */ ++#define CORSTONE1000_CLUSTER_COUNT U(1) ++#define CORSTONE1000_MAX_CPUS_PER_CLUSTER U(4) ++#define CORSTONE1000_MAX_PE_PER_CPU U(1) ++#define CORSTONE1000_PRIMARY_CPU U(0) + +-#define PLAT_ARM_CLUSTER_COUNT DIPHDA_CLUSTER_COUNT ++#define PLAT_ARM_CLUSTER_COUNT CORSTONE1000_CLUSTER_COUNT + + #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ +- DIPHDA_MAX_CPUS_PER_CLUSTER * \ +- DIPHDA_MAX_PE_PER_CPU) ++ CORSTONE1000_MAX_CPUS_PER_CLUSTER * \ ++ CORSTONE1000_MAX_PE_PER_CPU) + + /* UART related constants */ + #define PLAT_ARM_BOOT_UART_BASE 0x1a510000 +@@ -85,7 +85,7 @@ + * + * BL32 (optee-os) + * +- * = 0x20ae000 ++ * = 0x20ae000 + * + * partition size: 8 KB + * +@@ -132,7 +132,7 @@ + #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - 1) + +-/* DRAM1 and DRAM2 are the same for diphda */ ++/* DRAM1 and DRAM2 are the same for corstone1000 */ + #define ARM_DRAM2_BASE ARM_DRAM1_BASE + #define ARM_DRAM2_SIZE ARM_DRAM1_SIZE + #define ARM_DRAM2_END ARM_DRAM1_END +@@ -173,13 +173,13 @@ + PLAT_ARM_MAX_BL31_SIZE) + #define BL31_LIMIT BL2_SIGNATURE_BASE + +-#define DIPHDA_TOS_FW_CONFIG_BASE (BL31_BASE - \ +- DIPHDA_TOS_FW_CONFIG_SIZE) +-#define DIPHDA_TOS_FW_CONFIG_SIZE UL(0x00002000) /* 8 KB */ +-#define DIPHDA_TOS_FW_CONFIG_LIMIT BL31_BASE ++#define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \ ++ CORSTONE1000_TOS_FW_CONFIG_SIZE) ++#define CORSTONE1000_TOS_FW_CONFIG_SIZE UL(0x00002000) /* 8 KB */ ++#define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE + + #define BL32_BASE ARM_BL_RAM_BASE +-#define PLAT_ARM_MAX_BL32_SIZE (DIPHDA_TOS_FW_CONFIG_BASE - \ ++#define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - \ + BL32_BASE) /* 688 KB */ + #define BL32_LIMIT (BL32_BASE + \ + PLAT_ARM_MAX_BL32_SIZE) +@@ -220,7 +220,7 @@ + /* + * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo. + * FW_CONFIG is intended to host the device tree. Currently, This area is not +- * used because diphda platform doesn't use a device tree at TF-A level. ++ * used because corstone1000 platform doesn't use a device tree at TF-A level. + */ + #define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \ + + sizeof(meminfo_t)) +@@ -261,8 +261,8 @@ + + #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ + +-#define DIPHDA_IRQ_TZ_WDOG 32 +-#define DIPHDA_IRQ_SEC_SYS_TIMER 34 ++#define CORSTONE1000_IRQ_TZ_WDOG 32 ++#define CORSTONE1000_IRQ_SEC_SYS_TIMER 34 + + #define PLAT_MAX_PWR_LVL 2 + /* +@@ -308,7 +308,7 @@ + + #define PLATFORM_STACK_SIZE UL(0x440) + +-#define DIPHDA_EXTERNAL_FLASH MAP_REGION_FLAT( \ ++#define CORSTONE1000_EXTERNAL_FLASH MAP_REGION_FLAT( \ + PLAT_ARM_NVM_BASE, \ + PLAT_ARM_NVM_SIZE, \ + MT_DEVICE | MT_RO | MT_SECURE) +@@ -356,11 +356,11 @@ + ARM_FW_CONFIG_BASE), \ + MT_MEMORY | MT_RW | MT_SECURE) + +-#define DIPHDA_DEVICE_BASE (0x1A000000) +-#define DIPHDA_DEVICE_SIZE (0x26000000) +-#define DIPHDA_MAP_DEVICE MAP_REGION_FLAT( \ +- DIPHDA_DEVICE_BASE, \ +- DIPHDA_DEVICE_SIZE, \ ++#define CORSTONE1000_DEVICE_BASE (0x1A000000) ++#define CORSTONE1000_DEVICE_SIZE (0x26000000) ++#define CORSTONE1000_MAP_DEVICE MAP_REGION_FLAT( \ ++ CORSTONE1000_DEVICE_BASE, \ ++ CORSTONE1000_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + + #define ARM_IRQ_SEC_PHY_TIMER 29 +@@ -406,9 +406,9 @@ + */ + #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ +- INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ ++ INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_LEVEL), \ +- INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \ ++ INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) + + #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) +diff --git a/plat/arm/board/diphda/include/plat_macros.S b/plat/arm/board/corstone1000/include/plat_macros.S +similarity index 100% +rename from plat/arm/board/diphda/include/plat_macros.S +rename to plat/arm/board/corstone1000/include/plat_macros.S +diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk +new file mode 100644 +index 0000000000..93e2ea0826 +--- /dev/null ++++ b/plat/arm/board/corstone1000/platform.mk +@@ -0,0 +1,83 @@ ++# ++# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. ++# ++# SPDX-License-Identifier: BSD-3-Clause ++# ++ ++# Making sure the corstone1000 platform type is specified ++ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),) ++ $(error TARGET_PLATFORM must be fpga or fvp) ++endif ++ ++CORSTONE1000_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S ++ ++PLAT_INCLUDES := -Iplat/arm/board/corstone1000/common/include \ ++ -Iplat/arm/board/corstone1000/include \ ++ -Iinclude/plat/arm/common \ ++ -Iinclude/plat/arm/css/common/aarch64 ++ ++ ++CORSTONE1000_FW_NVCTR_VAL := 255 ++TFW_NVCTR_VAL := ${CORSTONE1000_FW_NVCTR_VAL} ++NTFW_NVCTR_VAL := ${CORSTONE1000_FW_NVCTR_VAL} ++ ++override NEED_BL1 := no ++ ++override NEED_BL2 := yes ++FIP_BL2_ARGS := tb-fw ++ ++override NEED_BL2U := no ++override NEED_BL31 := yes ++NEED_BL32 := yes ++override NEED_BL33 := yes ++ ++# Include GICv2 driver files ++include drivers/arm/gic/v2/gicv2.mk ++ ++CORSTONE1000_GIC_SOURCES := ${GICV2_SOURCES} \ ++ plat/common/plat_gicv2.c \ ++ plat/arm/common/arm_gicv2.c ++ ++ ++BL2_SOURCES += plat/arm/board/corstone1000/common/corstone1000_security.c \ ++ plat/arm/board/corstone1000/common/corstone1000_err.c \ ++ plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c \ ++ lib/utils/mem_region.c \ ++ plat/arm/board/corstone1000/common/corstone1000_helpers.S \ ++ plat/arm/board/corstone1000/common/corstone1000_plat.c \ ++ plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \ ++ ${CORSTONE1000_CPU_LIBS} \ ++ ++ ++BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ ++ lib/utils/mem_region.c \ ++ plat/arm/board/corstone1000/common/corstone1000_helpers.S \ ++ plat/arm/board/corstone1000/common/corstone1000_topology.c \ ++ plat/arm/board/corstone1000/common/corstone1000_security.c \ ++ plat/arm/board/corstone1000/common/corstone1000_plat.c \ ++ plat/arm/board/corstone1000/common/corstone1000_pm.c \ ++ ${CORSTONE1000_CPU_LIBS} \ ++ ${CORSTONE1000_GIC_SOURCES} ++ ++ifneq (${ENABLE_STACK_PROTECTOR},0) ++ ifneq (${ENABLE_STACK_PROTECTOR},none) ++ CORSTONE1000_SECURITY_SOURCES := plat/arm/board/corstone1000/common/corstone1000_stack_protector.c ++ BL2_SOURCES += ${CORSTONE1000_SECURITY_SOURCES} ++ BL31_SOURCES += ${CORSTONE1000_SECURITY_SOURCES} ++ endif ++endif ++ ++FDT_SOURCES += plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts ++CORSTONE1000_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/corstone1000_spmc_manifest.dtb ++ ++# Add the SPMC manifest to FIP and specify the same to certtool ++$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE1000_TOS_FW_CONFIG},--tos-fw-config,${CORSTONE1000_TOS_FW_CONFIG})) ++ ++# Adding TARGET_PLATFORM as a GCC define (-D option) ++$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM}))) ++ ++# Adding CORSTONE1000_FW_NVCTR_VAL as a GCC define (-D option) ++$(eval $(call add_define,CORSTONE1000_FW_NVCTR_VAL)) ++ ++include plat/arm/common/arm_common.mk ++include plat/arm/board/common/board_common.mk +diff --git a/plat/arm/board/diphda/platform.mk b/plat/arm/board/diphda/platform.mk +deleted file mode 100644 +index 8b89cee7ed..0000000000 +--- a/plat/arm/board/diphda/platform.mk ++++ /dev/null +@@ -1,83 +0,0 @@ +-# +-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +-# +-# SPDX-License-Identifier: BSD-3-Clause +-# +- +-# Making sure the diphda platform type is specified +-ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),) +- $(error TARGET_PLATFORM must be fpga or fvp) +-endif +- +-DIPHDA_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S +- +-PLAT_INCLUDES := -Iplat/arm/board/diphda/common/include \ +- -Iplat/arm/board/diphda/include \ +- -Iinclude/plat/arm/common \ +- -Iinclude/plat/arm/css/common/aarch64 +- +- +-DIPHDA_FW_NVCTR_VAL := 255 +-TFW_NVCTR_VAL := ${DIPHDA_FW_NVCTR_VAL} +-NTFW_NVCTR_VAL := ${DIPHDA_FW_NVCTR_VAL} +- +-override NEED_BL1 := no +- +-override NEED_BL2 := yes +-FIP_BL2_ARGS := tb-fw +- +-override NEED_BL2U := no +-override NEED_BL31 := yes +-NEED_BL32 := yes +-override NEED_BL33 := yes +- +-# Include GICv2 driver files +-include drivers/arm/gic/v2/gicv2.mk +- +-DIPHDA_GIC_SOURCES := ${GICV2_SOURCES} \ +- plat/common/plat_gicv2.c \ +- plat/arm/common/arm_gicv2.c +- +- +-BL2_SOURCES += plat/arm/board/diphda/common/diphda_security.c \ +- plat/arm/board/diphda/common/diphda_err.c \ +- plat/arm/board/diphda/common/diphda_trusted_boot.c \ +- lib/utils/mem_region.c \ +- plat/arm/board/diphda/common/diphda_helpers.S \ +- plat/arm/board/diphda/common/diphda_plat.c \ +- plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c \ +- ${DIPHDA_CPU_LIBS} \ +- +- +-BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ +- lib/utils/mem_region.c \ +- plat/arm/board/diphda/common/diphda_helpers.S \ +- plat/arm/board/diphda/common/diphda_topology.c \ +- plat/arm/board/diphda/common/diphda_security.c \ +- plat/arm/board/diphda/common/diphda_plat.c \ +- plat/arm/board/diphda/common/diphda_pm.c \ +- ${DIPHDA_CPU_LIBS} \ +- ${DIPHDA_GIC_SOURCES} +- +-ifneq (${ENABLE_STACK_PROTECTOR},0) +- ifneq (${ENABLE_STACK_PROTECTOR},none) +- DIPHDA_SECURITY_SOURCES := plat/arm/board/diphda/common/diphda_stack_protector.c +- BL2_SOURCES += ${DIPHDA_SECURITY_SOURCES} +- BL31_SOURCES += ${DIPHDA_SECURITY_SOURCES} +- endif +-endif +- +-FDT_SOURCES += plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts +-DIPHDA_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/diphda_spmc_manifest.dtb +- +-# Add the SPMC manifest to FIP and specify the same to certtool +-$(eval $(call TOOL_ADD_PAYLOAD,${DIPHDA_TOS_FW_CONFIG},--tos-fw-config,${DIPHDA_TOS_FW_CONFIG})) +- +-# Adding TARGET_PLATFORM as a GCC define (-D option) +-$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM}))) +- +-# Adding DIPHDA_FW_NVCTR_VAL as a GCC define (-D option) +-$(eval $(call add_define,DIPHDA_FW_NVCTR_VAL)) +- +-include plat/arm/common/arm_common.mk +-include plat/arm/board/common/board_common.mk +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-plat-arm-corstone1000-made-changes-to-accommodate-3M.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-plat-arm-corstone1000-made-changes-to-accommodate-3M.patch new file mode 100644 index 0000000..ee62ff0 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-plat-arm-corstone1000-made-changes-to-accommodate-3M.patch @@ -0,0 +1,201 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From bf95f27e300e962140a5dec45c2b1727c0829511 Mon Sep 17 00:00:00 2001 +From: "Arpita S.K" +Date: Wed, 13 Oct 2021 14:49:26 +0530 +Subject: [PATCH] plat/arm: corstone1000: made changes to accommodate 3MB for + optee + +* These changes are required to accommodate 3MB for OP-TEE and this +is required for SP's part of optee +* Added size macro's for better readability of the code +* Moved uboot execution memory from CVM to DDR + +Signed-off-by: Vishnu Banavath +--- + include/plat/common/common_def.h | 25 ++++++++ + .../common/corstone1000_bl2_mem_params_desc.c | 7 +-- + .../common/include/platform_def.h | 59 +++++++++++-------- + 3 files changed, 64 insertions(+), 27 deletions(-) + +diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h +index 14ae603b9b..5bb58692ef 100644 +--- a/include/plat/common/common_def.h ++++ b/include/plat/common/common_def.h +@@ -12,6 +12,31 @@ + #include + #include + ++#define SZ_1K 0x00000400 ++#define SZ_2K 0x00000800 ++#define SZ_4K 0x00001000 ++#define SZ_8K 0x00002000 ++#define SZ_16K 0x00004000 ++#define SZ_32K 0x00008000 ++#define SZ_64K 0x00010000 ++#define SZ_128K 0x00020000 ++#define SZ_256K 0x00040000 ++#define SZ_512K 0x00080000 ++ ++#define SZ_1M 0x00100000 ++#define SZ_2M 0x00200000 ++#define SZ_4M 0x00400000 ++#define SZ_8M 0x00800000 ++#define SZ_16M 0x01000000 ++#define SZ_32M 0x02000000 ++#define SZ_64M 0x04000000 ++#define SZ_128M 0x08000000 ++#define SZ_256M 0x10000000 ++#define SZ_512M 0x20000000 ++ ++#define SZ_1G 0x40000000 ++#define SZ_2G 0x80000000 ++ + /****************************************************************************** + * Required platform porting definitions that are expected to be common to + * all platforms +diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c +index 7baa82d31b..6e90936a14 100644 +--- a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c ++++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c +@@ -71,13 +71,12 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), +- .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, ++ .ep_info.pc = BL33_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), +- .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, +- .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE +- - PLAT_ARM_NS_IMAGE_BASE, ++ .image_info.image_base = BL33_BASE, ++ .image_info.image_max_size = BL33_LIMIT - BL33_BASE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h +index e36bb626ee..a0ac0fe758 100644 +--- a/plat/arm/board/corstone1000/common/include/platform_def.h ++++ b/plat/arm/board/corstone1000/common/include/platform_def.h +@@ -119,7 +119,7 @@ + * + * = + 1 MB + * +- * partition size: 3 MB ++ * partition size: 512 KB + * + * content: + * +@@ -128,13 +128,13 @@ + + /* DDR memory */ + #define ARM_DRAM1_BASE UL(0x80000000) +-#define ARM_DRAM1_SIZE UL(0x80000000) ++#define ARM_DRAM1_SIZE (SZ_2G) /* 2GB*/ + #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - 1) + + /* DRAM1 and DRAM2 are the same for corstone1000 */ +-#define ARM_DRAM2_BASE ARM_DRAM1_BASE +-#define ARM_DRAM2_SIZE ARM_DRAM1_SIZE ++#define ARM_DRAM2_BASE ARM_DRAM1_BASE ++#define ARM_DRAM2_SIZE ARM_DRAM1_SIZE + #define ARM_DRAM2_END ARM_DRAM1_END + + #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +@@ -144,23 +144,31 @@ + + /* The first 8 KB of Trusted SRAM are used as shared memory */ + #define ARM_TRUSTED_SRAM_BASE UL(0x02000000) +-#define ARM_SHARED_RAM_SIZE UL(0x00002000) /* 8 KB */ ++#define ARM_SHARED_RAM_SIZE (SZ_8K) /* 8 KB */ + #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE + + /* The remaining Trusted SRAM is used to load the BL images */ ++#define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */ + +-#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00100000) /* 1 MB */ ++/* Last 512KB of CVM is allocated for shared RAM ++ * as an example openAMP */ ++#define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K) + +-#define PLAT_ARM_MAX_BL2_SIZE UL(0x0002d000) /* 180 KB */ ++#define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \ ++ ARM_NS_SHARED_RAM_SIZE - \ ++ ARM_SHARED_RAM_SIZE) + +-#define PLAT_ARM_MAX_BL31_SIZE UL(0x00023000) /* 140 KB */ ++#define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */ + +-#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ +- ARM_SHARED_RAM_SIZE) +-#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ +- ARM_SHARED_RAM_SIZE) ++#define PLAT_ARM_MAX_BL31_SIZE (140 * SZ_1K) /* 140 KB */ ++ ++#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ ++ ARM_SHARED_RAM_SIZE) ++#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ ++ ARM_SHARED_RAM_SIZE) ++ ++#define BL2_SIGNATURE_SIZE (SZ_4K) /* 4 KB */ + +-#define BL2_SIGNATURE_SIZE UL(0x00001000) /* 4 KB */ + #define BL2_SIGNATURE_BASE (BL2_LIMIT - \ + PLAT_ARM_MAX_BL2_SIZE) + #define BL2_BASE (BL2_LIMIT - \ +@@ -175,14 +183,15 @@ + + #define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \ + CORSTONE1000_TOS_FW_CONFIG_SIZE) +-#define CORSTONE1000_TOS_FW_CONFIG_SIZE UL(0x00002000) /* 8 KB */ ++#define CORSTONE1000_TOS_FW_CONFIG_SIZE (SZ_8K) /* 8 KB */ + #define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE + + #define BL32_BASE ARM_BL_RAM_BASE +-#define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - \ +- BL32_BASE) /* 688 KB */ +-#define BL32_LIMIT (BL32_BASE + \ +- PLAT_ARM_MAX_BL32_SIZE) ++#define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - \ ++ BL32_BASE) ++ ++#define BL32_LIMIT (BL32_BASE + \ ++ PLAT_ARM_MAX_BL32_SIZE) + + /* SPD_spmd settings */ + +@@ -191,10 +200,14 @@ + + /* NS memory */ + +-/* The last 3 MB of the SRAM is allocated to the non secure area */ +-#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + \ +- PLAT_ARM_TRUSTED_SRAM_SIZE) +-#define ARM_NS_SHARED_RAM_SIZE UL(0x00300000) /* 3 MB */ ++/* The last 512KB of the SRAM is allocated as shared memory */ ++#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \ ++ (PLAT_ARM_MAX_BL31_SIZE + \ ++ PLAT_ARM_MAX_BL32_SIZE)) ++ ++#define BL33_BASE ARM_DRAM1_BASE ++#define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/ ++#define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE) + + /* end of the definition of SRAM memory layout */ + +@@ -204,7 +217,7 @@ + #define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ + + #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +-#define PLAT_ARM_NVM_SIZE UL(0x02000000) /* 32 MB */ ++#define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */ + + #define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE + #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc new file mode 100644 index 0000000..44f2696 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc @@ -0,0 +1,47 @@ +# Corstone1000 64-bit machines specific TFA support + +COMPATIBLE_MACHINE = "(corstone1000)" + +SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;protocol=https;name=tfa" + +# TF-A master branch with all Corstone1000 patches merged +SRCREV_tfa = "459b24451a0829460783ce8dfa15561e36d901d8" +PV .= "+git${SRCREV_tfa}" + +LIC_FILES_CHKSUM="file://docs/license.rst;md5=b2c740efedc159745b9b31f88ff03dde file://mbedtls/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57" + +FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:" +SRC_URI:append = " \ + file://0001-Rename-Diphda-to-corstone1000.patch \ + file://0002-plat-arm-corstone1000-made-changes-to-accommodate-3M.patch \ + " + +TFA_DEBUG = "1" +TFA_UBOOT = "1" +TFA_MBEDTLS = "1" +TFA_BUILD_TARGET = "bl2 bl31 fip" + +# Enabling Secure-EL1 Payload Dispatcher (SPD) +TFA_SPD = "spmd" +# Cortex-A35 supports Armv8.0-A (no S-EL2 execution state). +# So, the SPD SPMC component should run at the S-EL1 execution state +TFA_SPMD_SPM_AT_SEL2 = "0" + +# BL2 loads BL32 (optee). So, optee needs to be built first: +DEPENDS += "optee-os" + +EXTRA_OEMAKE:append = " \ + ARCH=aarch64 \ + TARGET_PLATFORM=${TFA_TARGET_PLATFORM} \ + ENABLE_STACK_PROTECTOR=strong \ + ENABLE_PIE=1 \ + BL2_AT_EL3=1 \ + CREATE_KEYS=1 \ + GENERATE_COT=1 \ + TRUSTED_BOARD_BOOT=1 \ + COT=tbbr \ + ARM_ROTPK_LOCATION=devel_rsa \ + ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ + BL32=${RECIPE_SYSROOT}/lib/firmware/tee-pager_v2.bin \ + LOG_LEVEL=50 \ + " diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.5.bbappend b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.5.bbappend index ea39dbd..659ba35 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.5.bbappend +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.5.bbappend @@ -3,6 +3,7 @@ MACHINE_TFA_REQUIRE ?= "" MACHINE_TFA_REQUIRE:corstone500 = "trusted-firmware-a-corstone500.inc" MACHINE_TFA_REQUIRE:corstone700 = "trusted-firmware-a-corstone700.inc" +MACHINE_TFA_REQUIRE:corstone1000 = "trusted-firmware-a-corstone1000.inc" MACHINE_TFA_REQUIRE:fvp-base = "trusted-firmware-a-fvp.inc" MACHINE_TFA_REQUIRE:fvp-base-arm32 = "trusted-firmware-a-fvp-arm32.inc" MACHINE_TFA_REQUIRE:juno = "trusted-firmware-a-juno.inc" From patchwork Tue Nov 23 15:59:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BCFCC433F5 for ; Tue, 23 Nov 2021 16:00:03 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.13102.1637683202039035810 for ; Tue, 23 Nov 2021 08:00:02 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B18321FB; Tue, 23 Nov 2021 08:00:01 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 666173F5A1; Tue, 23 Nov 2021 08:00:00 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Jon Mason Subject: [PATCH][honister 11/19] arm-bsp/optee: introducing corstone1000 FVP machine Date: Tue, 23 Nov 2021 15:59:18 +0000 Message-Id: <20211123155926.31743-12-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:03 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2440 From: Vishnu Banavath These changes are to add corstone1000-fvp machine to optee-os. Change-Id: I9ddfaca476234c0307a89d5444ae2d0e688a9b59 Signed-off-by: Arpita S.K Signed-off-by: Vishnu Banavath Signed-off-by: Jon Mason --- .../conf/machine/include/corstone1000.inc | 5 + ...rstone1000-add-corstone1000-platform.patch | 201 ++++++++++++++++++ ...000-reserve-3MB-CVM-memory-for-optee.patch | 30 +++ .../optee/optee-os_3.14.0.bbappend | 1 + .../optee/optee-os_corstone1000.inc | 27 +++ 5 files changed, 264 insertions(+) create mode 100644 meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0001-plat-corstone1000-add-corstone1000-platform.patch create mode 100644 meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0002-plat-corstone1000-reserve-3MB-CVM-memory-for-optee.patch create mode 100644 meta-arm-bsp/recipes-security/optee/optee-os_corstone1000.inc diff --git a/meta-arm-bsp/conf/machine/include/corstone1000.inc b/meta-arm-bsp/conf/machine/include/corstone1000.inc index a673e6b..0cc315b 100644 --- a/meta-arm-bsp/conf/machine/include/corstone1000.inc +++ b/meta-arm-bsp/conf/machine/include/corstone1000.inc @@ -24,6 +24,11 @@ UBOOT_BOOTARGS = "earlycon=pl011,0x1a510000 console=ttyAMA0 loglevel=9" UBOOT_ARCH = "arm" UBOOT_EXTLINUX = "0" +# optee +EXTRA_IMAGEDEPENDS += "optee-os" +OPTEE_ARCH = "arm64" +OPTEE_BINARY = "tee-pager_v2.bin" + # Linux kernel PREFERRED_PROVIDER_virtual/kernel:forcevariable = "linux-yocto" PREFERRED_VERSION_linux-yocto = "5.10%" diff --git a/meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0001-plat-corstone1000-add-corstone1000-platform.patch b/meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0001-plat-corstone1000-add-corstone1000-platform.patch new file mode 100644 index 0000000..7666486 --- /dev/null +++ b/meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0001-plat-corstone1000-add-corstone1000-platform.patch @@ -0,0 +1,201 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From 439a87df6a9f60f2b29afd988ad58a67e6f0b603 Mon Sep 17 00:00:00 2001 +From: Vishnu Banavath +Date: Tue, 22 Jun 2021 22:09:28 +0100 +Subject: [PATCH] plat-corstone1000: add corstone1000 platform + +These changes are to add corstone1000 platform to optee core + +Signed-off-by: Vishnu Banavath + +diff --git a/core/arch/arm/plat-corstone1000/conf.mk b/core/arch/arm/plat-corstone1000/conf.mk +new file mode 100644 +index 00000000..b14dd442 +--- /dev/null ++++ b/core/arch/arm/plat-corstone1000/conf.mk +@@ -0,0 +1,37 @@ ++PLATFORM_FLAVOR ?= mps3 ++ ++$(call force,CFG_HWSUPP_MEM_PERM_WXN,y) ++$(call force,CFG_HWSUPP_MEM_PERM_PXN,y) ++$(call force,CFG_ENABLE_SCTLR_RR,n) ++$(call force,CFG_ENABLE_SCTLR_Z,n) ++ ++arm64-platform-cpuarch := cortex-a35 ++arm64-platform-cflags += -mcpu=$(arm64-platform-cpuarch) ++arm64-platform-aflags += -mcpu=$(arm64-platform-cpuarch) ++platform-flavor-armv8 := 1 ++ ++$(call force,CFG_GIC,y) ++$(call force,CFG_PL011,y) ++$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) ++ ++$(call force,CFG_ARM64_core,y) ++ ++CFG_WITH_STATS ?= y ++ ++CFG_WITH_ARM_TRUSTED_FW ?= y ++CFG_WITH_LPAE ?=y ++ ++CFG_TEE_CORE_NB_CORE = 1 ++CFG_TZDRAM_START ?= 0x02002000 ++CFG_TZDRAM_SIZE ?= 0x000FE000 ++CFG_TEE_RAM_VA_SIZE ?= 0x00AF000 ++CFG_SHMEM_START ?= 0x86000000 ++CFG_SHMEM_SIZE ?= 0x00200000 ++ ++CFG_DDR_SIZE ?= 0x80000000 ++CFG_DT_ADDR ?= 0x82100000 ++CFG_DTB_MAX_SIZE ?= 0x100000 ++ ++$(call force,CFG_PSCI_ARM64,y) ++$(call force,CFG_DT,y) ++$(call force,CFG_EXTERNAL_DTB_OVERLAY,y) +diff --git a/core/arch/arm/plat-corstone1000/main.c b/core/arch/arm/plat-corstone1000/main.c +new file mode 100644 +index 00000000..35d89535 +--- /dev/null ++++ b/core/arch/arm/plat-corstone1000/main.c +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: BSD-2-Clause ++/* ++ * Copyright (c) 2020, Linaro Limited ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct gic_data gic_data __nex_bss; ++static struct pl011_data console_data __nex_bss; ++ ++register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); ++#ifdef DRAM0_BASE ++register_ddr(DRAM0_BASE, DRAM0_SIZE); ++#endif ++ ++#ifdef GIC_BASE ++register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); ++register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); ++ ++void main_init_gic(void) ++{ ++ vaddr_t gicc_base; ++ vaddr_t gicd_base; ++ ++ gicc_base = core_mmu_get_va(GICC_BASE, MEM_AREA_IO_SEC); ++ gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC); ++ ++ if (!gicc_base || !gicd_base) ++ panic(); ++ ++ /* Initialize GIC */ ++ gic_init(&gic_data, gicc_base, gicd_base); ++ itr_init(&gic_data.chip); ++ ++} ++ ++void main_secondary_init_gic(void) ++{ ++ gic_cpu_init(&gic_data); ++} ++ ++void itr_core_handler(void) ++{ ++ gic_it_handle(&gic_data); ++} ++#endif ++ ++void console_init(void) ++{ ++ pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, ++ CONSOLE_BAUDRATE); ++ register_serial_console(&console_data.chip); ++} ++ ++void ffa_secondary_cpu_boot_req(vaddr_t secondary_ep, uint64_t cookie) ++{ ++ DMSG("This is single core platform\n"); ++} ++ +diff --git a/core/arch/arm/plat-corstone1000/platform_config.h b/core/arch/arm/plat-corstone1000/platform_config.h +new file mode 100644 +index 00000000..cfee6fa4 +--- /dev/null ++++ b/core/arch/arm/plat-corstone1000/platform_config.h +@@ -0,0 +1,46 @@ ++/* SPDX-License-Identifier: BSD-2-Clause */ ++/* ++ * Copyright (c) 2020, Linaro Limited ++ */ ++ ++#ifndef PLATFORM_CONFIG_H ++#define PLATFORM_CONFIG_H ++ ++#include ++#include ++ ++/* Make stacks aligned to data cache line length */ ++#define STACK_ALIGNMENT 64 ++ ++ ++#define GIC_BASE 0x1c000000 ++#define UART0_BASE 0x1a510000 ++#define UART1_BASE 0x1a520000 ++ ++#define CONSOLE_UART_BASE UART1_BASE ++ ++#define DRAM0_BASE 0x80000000 ++#define DRAM0_SIZE 0x7f000000 ++ ++#define GICD_OFFSET 0x10000 ++#define GICC_OFFSET 0x2f000 ++ ++#ifdef GIC_BASE ++#define GICD_BASE (GIC_BASE + GICD_OFFSET) ++#define GICC_BASE (GIC_BASE + GICC_OFFSET) ++#endif ++ ++#ifndef UART_BAUDRATE ++#define UART_BAUDRATE 115200 ++#endif ++#ifndef CONSOLE_BAUDRATE ++#define CONSOLE_BAUDRATE UART_BAUDRATE ++#endif ++ ++#ifndef SYS_COUNTER_FREQ_IN_TICKS ++#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 32MHz */ ++#endif ++ ++#define CONSOLE_UART_CLK_IN_HZ UL(50000000) /* 32MHz*/ ++ ++#endif /*PLATFORM_CONFIG_H*/ +diff --git a/core/arch/arm/plat-corstone1000/sub.mk b/core/arch/arm/plat-corstone1000/sub.mk +new file mode 100644 +index 00000000..8ddc2fd4 +--- /dev/null ++++ b/core/arch/arm/plat-corstone1000/sub.mk +@@ -0,0 +1,2 @@ ++global-incdirs-y += . ++srcs-y += main.c +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0002-plat-corstone1000-reserve-3MB-CVM-memory-for-optee.patch b/meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0002-plat-corstone1000-reserve-3MB-CVM-memory-for-optee.patch new file mode 100644 index 0000000..ea60fee --- /dev/null +++ b/meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0002-plat-corstone1000-reserve-3MB-CVM-memory-for-optee.patch @@ -0,0 +1,30 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From dbaf7a11e686d362eb09e63841eb718ea777dd03 Mon Sep 17 00:00:00 2001 +From: Vishnu Banavath +Date: Wed, 1 Sep 2021 16:46:42 +0100 +Subject: [PATCH] plat-corstone1000: reserve 3MB CVM memory for optee + +optee requires 3MB CVM memory to include SecurePartition's into +it's image + +Signed-off-by: Vishnu Banavath + +diff --git a/core/arch/arm/plat-corstone1000/conf.mk b/core/arch/arm/plat-corstone1000/conf.mk +index b14dd442..7a4aa13c 100644 +--- a/core/arch/arm/plat-corstone1000/conf.mk ++++ b/core/arch/arm/plat-corstone1000/conf.mk +@@ -23,8 +23,7 @@ CFG_WITH_LPAE ?=y + + CFG_TEE_CORE_NB_CORE = 1 + CFG_TZDRAM_START ?= 0x02002000 +-CFG_TZDRAM_SIZE ?= 0x000FE000 +-CFG_TEE_RAM_VA_SIZE ?= 0x00AF000 ++CFG_TZDRAM_SIZE ?= 0x300000 # OPTEE CODE + DATA +TA_RAM = 3MB + CFG_SHMEM_START ?= 0x86000000 + CFG_SHMEM_SIZE ?= 0x00200000 + +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-security/optee/optee-os_3.14.0.bbappend b/meta-arm-bsp/recipes-security/optee/optee-os_3.14.0.bbappend index e276fb8..7834b64 100644 --- a/meta-arm-bsp/recipes-security/optee/optee-os_3.14.0.bbappend +++ b/meta-arm-bsp/recipes-security/optee/optee-os_3.14.0.bbappend @@ -1,6 +1,7 @@ # Machine specific configurations MACHINE_OPTEE_OS_REQUIRE ?= "" +MACHINE_OPTEE_OS_REQUIRE:corstone1000 = "optee-os_corstone1000.inc" MACHINE_OPTEE_OS_REQUIRE:tc = "optee-os-tc.inc" require ${MACHINE_OPTEE_OS_REQUIRE} diff --git a/meta-arm-bsp/recipes-security/optee/optee-os_corstone1000.inc b/meta-arm-bsp/recipes-security/optee/optee-os_corstone1000.inc new file mode 100644 index 0000000..e2cc7d6 --- /dev/null +++ b/meta-arm-bsp/recipes-security/optee/optee-os_corstone1000.inc @@ -0,0 +1,27 @@ +SRC_URI = "git://git.trustedfirmware.org/OP-TEE/optee_os.git;protocol=https;branch=psa-development" +SRCREV = "f9de2c9520ed97b89760cc4c99424aae440b63f4" +PV .= "+git${SRCREV}" + +DEPENDS += "python3-pycryptodomex-native" + +FILESEXTRAPATHS:prepend := "${THISDIR}/files/optee-os/corstone1000:" + +SRC_URI:append = " \ + file://0001-plat-corstone1000-add-corstone1000-platform.patch \ + file://0002-plat-corstone1000-reserve-3MB-CVM-memory-for-optee.patch" + +COMPATIBLE_MACHINE = "corstone1000" + +OPTEEMACHINE = "corstone1000" +# Enable optee memory layout and boot logs +EXTRA_OEMAKE += " CFG_TEE_CORE_LOG_LEVEL=4" + +# default disable latency benchmarks (over all OP-TEE layers) +EXTRA_OEMAKE += " CFG_TEE_BENCHMARK=n" + +EXTRA_OEMAKE += " CFG_CORE_SEL1_SPMC=y CFG_CORE_FFA=y" + +EXTRA_OEMAKE += " CFG_WITH_SP=y" + +EXTRA_OEMAKE += " HOST_PREFIX=${HOST_PREFIX}" +EXTRA_OEMAKE += " CROSS_COMPILE64=${HOST_PREFIX}" From patchwork Tue Nov 23 15:59:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 284E3C43217 for ; Tue, 23 Nov 2021 16:00:05 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.13297.1637683204218928321 for ; Tue, 23 Nov 2021 08:00:04 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E3E6C1063; Tue, 23 Nov 2021 08:00:03 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0E6EA3F5A1; Tue, 23 Nov 2021 08:00:01 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Rui Miguel Silva , Jon Mason Subject: [PATCH][honister 12/19] arm-bsp/u-boot: corstone1000: extend efi support Date: Tue, 23 Nov 2021 15:59:19 +0000 Message-Id: <20211123155926.31743-13-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:05 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2441 From: Vishnu Banavath enable efi boot including secure config options, add a load command which integrate with efi subsystem. And as at it, enable the efi capsule options for future use. Change-Id: Iced8ab2b9bca41805f6201150760692b4b716d7d Signed-off-by: Arpita S.K Signed-off-by: Vishnu Banavath Signed-off-by: Rui Miguel Silva Signed-off-by: Jon Mason --- ...d-add-load-command-for-memory-mapped.patch | 177 ++++++++++++++++++ ...-corstone1000-enable-boot-using-uefi.patch | 61 ++++++ ...corstone1000-enable-uefi-secure-boot.patch | 32 ++++ ...0-enable-handlers-for-uefi-variables.patch | 47 +++++ ...stone1000-enable-efi-capsule-options.patch | 36 ++++ .../recipes-bsp/u-boot/u-boot_%.bbappend | 5 + 6 files changed, 358 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0010-cmd-load-add-load-command-for-memory-mapped.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0011-arm-corstone1000-enable-boot-using-uefi.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0012-arm-corstone1000-enable-uefi-secure-boot.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0013-arm-corstone1000-enable-handlers-for-uefi-variables.patch create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0014-arm-corstone1000-enable-efi-capsule-options.patch diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0010-cmd-load-add-load-command-for-memory-mapped.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0010-cmd-load-add-load-command-for-memory-mapped.patch new file mode 100644 index 0000000..ca2039c --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0010-cmd-load-add-load-command-for-memory-mapped.patch @@ -0,0 +1,177 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From 5278fb64beabeddd6c80229e5165f91ed1e95376 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Thu, 24 Jun 2021 09:25:00 +0100 +Subject: [PATCH 10/16] cmd: load: add load command for memory mapped + +cp.b is used a lot as a way to load binaries to memory and execute +them, however we may need to integrate this with the efi subsystem to +set it up as a bootdev. + +So, introduce a loadm command that will be consistent with the other +loadX commands and will call the efi API's. + +ex: loadm $kernel_addr $kernel_addr_r $kernel_size + +with this a kernel with CONFIG_EFI_STUB enabled will be loaded and +then subsequently booted with bootefi command. + +Signed-off-by: Rui Miguel Silva +--- + cmd/Kconfig | 6 ++++ + cmd/bootefi.c | 12 ++++++++ + cmd/load.c | 49 ++++++++++++++++++++++++++++++++ + include/efi_loader.h | 2 ++ + lib/efi_loader/efi_device_path.c | 10 +++++++ + 5 files changed, 79 insertions(+) + +diff --git a/cmd/Kconfig b/cmd/Kconfig +index a9fb4eead2..56fa0ceade 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -1048,6 +1048,12 @@ config CMD_LOADB + help + Load a binary file over serial line. + ++config CMD_LOADM ++ bool "loadm" ++ default y ++ help ++ Load a binary over memory mapped. ++ + config CMD_LOADS + bool "loads" + default y +diff --git a/cmd/bootefi.c b/cmd/bootefi.c +index cba81ffe75..9e1b91c89e 100644 +--- a/cmd/bootefi.c ++++ b/cmd/bootefi.c +@@ -34,6 +34,18 @@ static struct efi_device_path *bootefi_device_path; + static void *image_addr; + static size_t image_size; + ++/** ++ * efi_get_image_parameters() - return image parameters ++ * ++ * @img_addr: address of loaded image in memory ++ * @img_size: size of loaded image ++ */ ++void efi_get_image_parameters(void **img_addr, size_t *img_size) ++{ ++ *img_addr = image_addr; ++ *img_size = image_size; ++} ++ + /** + * efi_clear_bootdev() - clear boot device + */ +diff --git a/cmd/load.c b/cmd/load.c +index b7894d7db0..4de197681c 100644 +--- a/cmd/load.c ++++ b/cmd/load.c +@@ -1020,6 +1020,45 @@ static ulong load_serial_ymodem(ulong offset, int mode) + + #endif + ++#if defined(CONFIG_CMD_LOADM) ++static int do_load_memory_bin(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ ulong addr, dest, size; ++ void *src, *dst; ++ ++ if (argc != 4) ++ return CMD_RET_USAGE; ++ ++ addr = simple_strtoul(argv[1], NULL, 16); ++ ++ dest = simple_strtoul(argv[2], NULL, 16); ++ ++ size = simple_strtoul(argv[3], NULL, 16); ++ ++ ++ if (!size) { ++ puts ("can not load zero bytes\n"); ++ return 1; ++ } ++ ++ src = map_sysmem(addr, size); ++ dst = map_sysmem(dest, size); ++ ++ memcpy(dst, src, size); ++ ++ unmap_sysmem(src); ++ unmap_sysmem(dst); ++ ++ if (IS_ENABLED(CONFIG_CMD_BOOTEFI)) ++ efi_set_bootdev("Mem", "", "", map_sysmem(dest, 0), size); ++ ++ printf("loaded bin to memory: size: %lu\n", size); ++ ++ return 0; ++} ++#endif ++ + /* -------------------------------------------------------------------- */ + + #if defined(CONFIG_CMD_LOADS) +@@ -1094,3 +1133,13 @@ U_BOOT_CMD( + ); + + #endif /* CONFIG_CMD_LOADB */ ++ ++#if defined(CONFIG_CMD_LOADM) ++U_BOOT_CMD( ++ loadm, 4, 0, do_load_memory_bin, ++ "load binary blob from two addresses", ++ "[src_addr] [dst_addr] [size]\n" ++ " - load a binary blob from one memory location to other" ++ " from src_addr to dst_addr by size bytes" ++); ++#endif /* CONFIG_CMD_LOADM */ +diff --git a/include/efi_loader.h b/include/efi_loader.h +index b81180cfda..fc4f1ec67a 100644 +--- a/include/efi_loader.h ++++ b/include/efi_loader.h +@@ -485,6 +485,8 @@ void efi_save_gd(void); + void efi_restore_gd(void); + /* Call this to relocate the runtime section to an address space */ + void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map); ++/* Call this to get image parameters */ ++void efi_get_image_parameters(void **img_addr, size_t *img_size); + /* Call this to set the current device name */ + void efi_set_bootdev(const char *dev, const char *devnr, const char *path, + void *buffer, size_t buffer_size); +diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c +index 76c2f82fe6..a610b6ff0e 100644 +--- a/lib/efi_loader/efi_device_path.c ++++ b/lib/efi_loader/efi_device_path.c +@@ -1170,6 +1170,8 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr, + { + struct blk_desc *desc = NULL; + struct disk_partition fs_partition; ++ size_t image_size; ++ void *image_addr; + int part = 0; + char *filename; + char *s; +@@ -1185,6 +1187,14 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr, + } else if (!strcmp(dev, "Uart")) { + if (device) + *device = efi_dp_from_uart(); ++ } else if (!strcmp(dev, "Mem")) { ++ ++ efi_get_image_parameters(&image_addr, &image_size); ++ ++ if (device) ++ *device = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, ++ (uintptr_t)image_addr, ++ image_size); + } else { + part = blk_get_device_part_str(dev, devnr, &desc, &fs_partition, + 1); +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0011-arm-corstone1000-enable-boot-using-uefi.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0011-arm-corstone1000-enable-boot-using-uefi.patch new file mode 100644 index 0000000..95b97ee --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0011-arm-corstone1000-enable-boot-using-uefi.patch @@ -0,0 +1,61 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From 283cae5b37eced831080a50d76006359662fb6bf Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Wed, 23 Jun 2021 00:45:38 +0100 +Subject: [PATCH 11/16] arm: corstone1000: enable boot using uefi + +In a way to prepare future use of uefi features, enable booting using +the bootefi binary loading. + +Signed-off-by: Rui Miguel Silva +Signed-off-by: Rui Miguel Silva +--- + configs/corstone1000_defconfig | 7 +++++++ + include/configs/corstone1000.h | 6 +++--- + 2 files changed, 10 insertions(+), 3 deletions(-) + +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index af1c5ecd89..aa664029fc 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -2,6 +2,7 @@ CONFIG_ARM=y + CONFIG_TARGET_CORSTONE1000=y + CONFIG_SYS_TEXT_BASE=0x80000000 + CONFIG_SYS_MALLOC_F_LEN=0x2000 ++CONFIG_SYS_LOAD_ADDR=0x82100000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_IDENT_STRING=" corstone1000 aarch64 " + CONFIG_FIT=y +@@ -14,6 +15,12 @@ CONFIG_HUSH_PARSER=y + CONFIG_SYS_PROMPT="corstone1000# " + # CONFIG_CMD_CONSOLE is not set + CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_BOOTM=y ++CONFIG_CMD_LOADM=y ++CONFIG_CMD_BOOTEFI=y ++CONFIG_EFI_LOADER=y ++CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y ++CONFIG_CMD_BOOTEFI_HELLO=y + # CONFIG_CMD_XIMG is not set + # CONFIG_CMD_EDITENV is not set + # CONFIG_CMD_ENV_EXISTS is not set +diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h +index 389ac45a58..5e22e075ad 100644 +--- a/include/configs/corstone1000.h ++++ b/include/configs/corstone1000.h +@@ -70,7 +70,7 @@ + "fdt_high=0xffffffff\0" + + #define CONFIG_BOOTCOMMAND \ +- "echo Copying Kernel to memory ... ;" \ +- "cp.b $kernel_addr $kernel_addr_r 0xc00000;" \ +- "booti $kernel_addr_r - $fdtcontroladdr; " ++ "echo Loading Kernel to memory ... ;" \ ++ "loadm $kernel_addr $kernel_addr_r 0xc00000;" \ ++ "bootefi $kernel_addr_r $fdtcontroladdr;" + #endif +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0012-arm-corstone1000-enable-uefi-secure-boot.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0012-arm-corstone1000-enable-uefi-secure-boot.patch new file mode 100644 index 0000000..e71ae2c --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0012-arm-corstone1000-enable-uefi-secure-boot.patch @@ -0,0 +1,32 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From e49597b8d9058d8c5b925339b0041fd7096c622d Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Tue, 14 Sep 2021 10:46:49 +0100 +Subject: [PATCH 12/16] arm: corstone1000: enable uefi secure boot + +To make it possible to have a secure way to execute UEFI images +enable UEFI secure boot support and by inherit the +cryptographic functionalities. + +Signed-off-by: Rui Miguel Silva +--- + configs/corstone1000_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index aa664029fc..a8651287ed 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -43,6 +43,7 @@ CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_USB_ISP1760=y + CONFIG_USB_STORAGE=y ++CONFIG_EFI_SECURE_BOOT=y + CONFIG_DM_RTC=y + CONFIG_CMD_RTC=y + CONFIG_EFI_GET_TIME=y +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0013-arm-corstone1000-enable-handlers-for-uefi-variables.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0013-arm-corstone1000-enable-handlers-for-uefi-variables.patch new file mode 100644 index 0000000..594e9f5 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0013-arm-corstone1000-enable-handlers-for-uefi-variables.patch @@ -0,0 +1,47 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From de37d61d1414cb6408390412cf77d7a88f8964e1 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Tue, 14 Sep 2021 22:00:47 +0100 +Subject: [PATCH 13/16] arm: corstone1000: enable handlers for uefi variables + +Enable the setenv/printenv -e option to handle uefi +variables and the efidebug command. + +Signed-off-by: Rui Miguel Silva +--- + configs/corstone1000_defconfig | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index a8651287ed..b17e2df47b 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -24,6 +24,7 @@ CONFIG_CMD_BOOTEFI_HELLO=y + # CONFIG_CMD_XIMG is not set + # CONFIG_CMD_EDITENV is not set + # CONFIG_CMD_ENV_EXISTS is not set ++CONFIG_CMD_NVEDIT_EFI=y + # CONFIG_CMD_LOADS is not set + CONFIG_CMD_USB=y + # CONFIG_CMD_ITEST is not set +@@ -33,6 +34,7 @@ CONFIG_CMD_DHCP=y + CONFIG_CMD_MII=y + CONFIG_CMD_PING=y + CONFIG_CMD_CACHE=y ++CONFIG_CMD_EFIDEBUG=y + CONFIG_CMD_FAT=y + CONFIG_OF_CONTROL=y + CONFIG_REGMAP=y +@@ -43,6 +45,7 @@ CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_USB_ISP1760=y + CONFIG_USB_STORAGE=y ++# CONFIG_HEXDUMP is not set + CONFIG_EFI_SECURE_BOOT=y + CONFIG_DM_RTC=y + CONFIG_CMD_RTC=y +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0014-arm-corstone1000-enable-efi-capsule-options.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0014-arm-corstone1000-enable-efi-capsule-options.patch new file mode 100644 index 0000000..a414a09 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0014-arm-corstone1000-enable-efi-capsule-options.patch @@ -0,0 +1,36 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From fe0acf22a0c30f7d3eb1a8c66fb423b4146d35ab Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Tue, 14 Sep 2021 22:07:15 +0100 +Subject: [PATCH 14/16] arm: dipha: enable efi capsule options + +Enable the set of efi capsule config options to enable the +variables. + +Signed-off-by: Rui Miguel Silva +--- + configs/corstone1000_defconfig | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index b17e2df47b..cfe80cf5f4 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -46,6 +46,12 @@ CONFIG_DM_USB=y + CONFIG_USB_ISP1760=y + CONFIG_USB_STORAGE=y + # CONFIG_HEXDUMP is not set ++CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y ++CONFIG_EFI_CAPSULE_ON_DISK=y ++CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y ++CONFIG_EFI_CAPSULE_AUTHENTICATE=y ++CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y ++CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y + CONFIG_EFI_SECURE_BOOT=y + CONFIG_DM_RTC=y + CONFIG_CMD_RTC=y +-- +2.33.0 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend index 30a6f7f..b73e6f7 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend @@ -21,6 +21,11 @@ SRC_URI:append:corstone1000 = " \ file://0007-arm-corstone1000-sharing-PSCI-DTS-node-between-FVP-a.patch \ file://0008-arm-corstone1000-Emulated-RTC-Support.patch \ file://0009-arm-corstone1000-execute-uboot-from-DDR.patch \ + file://0010-cmd-load-add-load-command-for-memory-mapped.patch \ + file://0011-arm-corstone1000-enable-boot-using-uefi.patch \ + file://0012-arm-corstone1000-enable-uefi-secure-boot.patch \ + file://0013-arm-corstone1000-enable-handlers-for-uefi-variables.patch \ + file://0014-arm-corstone1000-enable-efi-capsule-options.patch \ " # From patchwork Tue Nov 23 15:59:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 213ADC43219 for ; Tue, 23 Nov 2021 16:00:07 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.13284.1637683206176021467 for ; Tue, 23 Nov 2021 08:00:06 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D3EF01FB; Tue, 23 Nov 2021 08:00:05 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 337ED3F5A1; Tue, 23 Nov 2021 08:00:04 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Rui Miguel Silva , Jon Mason Subject: [PATCH][honister 13/19] arm-bsp/linux: corstone1000: enable efi Date: Tue, 23 Nov 2021 15:59:20 +0000 Message-Id: <20211123155926.31743-14-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:07 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2442 From: Rui Miguel Silva In an effort to setup capsule update and efi runtime service handlers, enable the correspondent efi config options. Signed-off-by: Rui Miguel Silva Change-Id: Ib068448564268dcacb9bcad3667a3b293f177a83 Signed-off-by: Jon Mason --- .../recipes-kernel/linux/files/corstone1000/defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig index cc7dc3e..4642352 100644 --- a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig @@ -8,7 +8,12 @@ CONFIG_RELAY=y CONFIG_BOOT_CONFIG=y CONFIG_ARCH_VEXPRESS=y CONFIG_CMDLINE="console=ttyAMA0 loglevel=9" +CONFIG_EFI=y # CONFIG_SUSPEND is not set +CONFIG_EFI_BOOTLOADER_CONTROL=y +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_EFI_TEST=y +CONFIG_RESET_ATTACK_MITIGATION=y # CONFIG_STACKPROTECTOR is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set From patchwork Tue Nov 23 15:59:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22D9BC433EF for ; Tue, 23 Nov 2021 16:00:09 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.13285.1637683208176654589 for ; Tue, 23 Nov 2021 08:00:08 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C66351063; Tue, 23 Nov 2021 08:00:07 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1BE5B3F5A1; Tue, 23 Nov 2021 08:00:05 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Abdellatif El Khlifi , Jon Mason Subject: [PATCH][honister 14/19] arm-bsp/python3-imgtool: add the recipe Date: Tue, 23 Nov 2021 15:59:21 +0000 Message-Id: <20211123155926.31743-15-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:09 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2443 From: Abdellatif El Khlifi Until this is integrated into meta-python, hold a copy of python3-imgtool in meta-arm-bsp used by trusted-firmware-m. Change-Id: I2e86be503bee03de549f5714dc52921165afa2bf Signed-off-by: Abdellatif El Khlifi Signed-off-by: Arpita S.K Signed-off-by: Jon Mason --- meta-arm-bsp/conf/layer.conf | 1 + .../corstone1000-imgtool/python3-imgtool_1.7.1.bb | 14 ++++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 meta-arm-bsp/recipes-devtool/corstone1000-imgtool/python3-imgtool_1.7.1.bb diff --git a/meta-arm-bsp/conf/layer.conf b/meta-arm-bsp/conf/layer.conf index f4306a6..954e5d8 100644 --- a/meta-arm-bsp/conf/layer.conf +++ b/meta-arm-bsp/conf/layer.conf @@ -13,6 +13,7 @@ LAYERSERIES_COMPAT_meta-arm-bsp = "honister" LAYERDEPENDS_meta-arm-bsp = "core meta-arm" # This won't be used by layerindex-fetch, but works everywhere else +LAYERDEPENDS_meta-arm-bsp:append:corstone1000 = " meta-python" LAYERDEPENDS_meta-arm-bsp:append:musca-b1 = " meta-python" LAYERDEPENDS_meta-arm-bsp:append:musca-s1 = " meta-python" diff --git a/meta-arm-bsp/recipes-devtool/corstone1000-imgtool/python3-imgtool_1.7.1.bb b/meta-arm-bsp/recipes-devtool/corstone1000-imgtool/python3-imgtool_1.7.1.bb new file mode 100644 index 0000000..06d52d0 --- /dev/null +++ b/meta-arm-bsp/recipes-devtool/corstone1000-imgtool/python3-imgtool_1.7.1.bb @@ -0,0 +1,14 @@ +SUMMARY = "MCUboot's image signing and key management" +LICENSE = "Apache-2.0" +AUTHOR = "The MCUboot committers , \ + Abdellatif El Khlifi " + +LIC_FILES_CHKSUM = "file://PKG-INFO;md5=e32b214fd9c204b77a99a97aa903757b" + +SRC_URI[md5sum] = "de0005dc13ce9e5e6aecdedfd0956286" + +DEPENDS:corstone1000 = "python3-cryptography python3-intelhex python3-click python3-cbor" + +inherit pypi setuptools3 + +BBCLASSEXTEND = "native nativesdk" From patchwork Tue Nov 23 15:59:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 294D9C43219 for ; Tue, 23 Nov 2021 16:00:11 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.13044.1637683210418395014 for ; Tue, 23 Nov 2021 08:00:10 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0F9AC1FB; Tue, 23 Nov 2021 08:00:10 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 31BFB3F5A1; Tue, 23 Nov 2021 08:00:08 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Abdellatif El Khlifi , Satish Kumar , Jon Mason Subject: [PATCH][honister 15/19] arm-bsp/trusted-firmware-m: corstone1000: signing trusted-firmware-a binaries Date: Tue, 23 Nov 2021 15:59:22 +0000 Message-Id: <20211123155926.31743-16-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:11 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2444 From: Abdellatif El Khlifi This commit allows to sign trusted-firmware-a BL2 and FIP using MCUBOOT tools. Change-Id: Ide3045982f5f8515c1ccd59b6b0d29816fbfdd68 Signed-off-by: Abdellatif El Khlifi Signed-off-by: Satish Kumar Signed-off-by: Jon Mason --- .../conf/machine/include/corstone1000.inc | 12 +++++ .../trusted-firmware-a-corstone1000.inc | 3 ++ .../trusted-firmware-m-corstone1000.inc | 19 +++++++ .../trusted-firmware-m-sign-host-images.inc | 50 +++++++++++++++++++ 4 files changed, 84 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-sign-host-images.inc diff --git a/meta-arm-bsp/conf/machine/include/corstone1000.inc b/meta-arm-bsp/conf/machine/include/corstone1000.inc index 0cc315b..753347d 100644 --- a/meta-arm-bsp/conf/machine/include/corstone1000.inc +++ b/meta-arm-bsp/conf/machine/include/corstone1000.inc @@ -7,11 +7,23 @@ TFA_PLATFORM = "corstone1000" PREFERRED_VERSION_trusted-firmware-a ?= "2.5%" EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-a" +TFA_BL2_BINARY = "bl2-corstone1000.bin" +TFA_FIP_BINARY = "fip-corstone1000.bin" + # TF-M PREFERRED_VERSION_trusted-firmware-m ?= "1.4%" TFM_PLATFORM = "arm/corstone1000" EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-m" +# TF-M settings for signing host images +TFA_BL2_RE_IMAGE_LOAD_ADDRESS = "0x62353000" +TFA_BL2_RE_SIGN_BIN_SIZE = "0x2d000" +TFA_FIP_RE_IMAGE_LOAD_ADDRESS = "0x68130000" +TFA_FIP_RE_SIGN_BIN_SIZE = "0x00200000" +RE_LAYOUT_WRAPPER_VERSION = "0.0.7" +TFM_SIGN_PRIVATE_KEY = "${S}/bl2/ext/mcuboot/root-RSA-3072_1.pem" +RE_IMAGE_OFFSET = "0x1000" + # u-boot PREFERRED_VERSION_u-boot ?= "2021.07" EXTRA_IMAGEDEPENDS += "u-boot" diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc index 44f2696..833396e 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc @@ -45,3 +45,6 @@ EXTRA_OEMAKE:append = " \ BL32=${RECIPE_SYSROOT}/lib/firmware/tee-pager_v2.bin \ LOG_LEVEL=50 \ " + +# trigger TF-M build so TF-A binaries get signed +do_deploy[depends]+= "virtual/trusted-firmware-m:do_prepare_recipe_sysroot" diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc index 1967365..997859c 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc @@ -17,6 +17,13 @@ SRCREV_tfm = "ccd82e35f539c0d7261b2935d6d30c550cfc6736" SRCREV_FORMAT = "tfm_mcuboot_tfm-tests_mbedtls" +# The install task signs the TF-A BL2 and FIP binaries. +# So they need to be copied to the sysroot. Hence the dependencies below: +do_prepare_recipe_sysroot[depends]+= "virtual/trusted-firmware-a:do_populate_sysroot" + +# adding host images signing support +require trusted-firmware-m-sign-host-images.inc + do_install() { if [ ! -d "${B}/install/outputs/ARM/CORSTONE1000" ] then @@ -27,4 +34,16 @@ do_install() { install -D -p -m 0644 ${B}/install/outputs/ARM/CORSTONE1000/bl2_signed.bin ${D}/firmware/bl2_signed.bin install -D -p -m 0644 ${B}/install/outputs/ARM/CORSTONE1000/bl1.bin ${D}/firmware/bl1.bin + # + # Signing TF-A BL2 and the FIP image + # + + sign_host_image ${TFA_BL2_BINARY} ${RECIPE_SYSROOT}/firmware ${TFA_BL2_RE_IMAGE_LOAD_ADDRESS} ${TFA_BL2_RE_SIGN_BIN_SIZE} + + fiptool update \ + --tb-fw ${D}/firmware/signed_${TFA_BL2_BINARY} \ + ${RECIPE_SYSROOT}/firmware/${TFA_FIP_BINARY} + + sign_host_image ${TFA_FIP_BINARY} ${RECIPE_SYSROOT}/firmware ${TFA_FIP_RE_IMAGE_LOAD_ADDRESS} ${TFA_FIP_RE_SIGN_BIN_SIZE} + } diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-sign-host-images.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-sign-host-images.inc new file mode 100644 index 0000000..49af356 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-sign-host-images.inc @@ -0,0 +1,50 @@ +# Signing host images using TF-M tools + +DEPENDS += "python3-imgtool-native fiptool-native" + +# +# sign_host_image +# +# Description: +# +# A generic function that signs a host image +# using MCUBOOT format +# +# Arguments: +# +# $1 ... host binary to sign +# $2 ... host binary path +# $3 ... load address of the given binary +# $4 ... signed binary size +# +# Note: The signed binary is copied to ${D}/firmware +# +sign_host_image() { + + host_binary_filename="`basename -s .bin ${1}`" + host_binary_layout="${host_binary_filename}_ns" + + cat << EOF > ${B}/${host_binary_layout} +enum image_attributes { + RE_IMAGE_LOAD_ADDRESS = ${3}, + RE_SIGN_BIN_SIZE = ${4}, +}; +EOF + + host_binary="${2}/`basename ${1}`" + host_binary_signed="${D}/firmware/signed_`basename ${1}`" + + ${PYTHON} ${S}/bl2/ext/mcuboot/scripts/wrapper/wrapper.py \ + -v ${RE_LAYOUT_WRAPPER_VERSION} \ + --layout ${B}/${host_binary_layout} \ + -k ${TFM_SIGN_PRIVATE_KEY} \ + --public-key-format full \ + --align 1 \ + --pad \ + --pad-header \ + -H ${RE_IMAGE_OFFSET} \ + -s auto \ + ${host_binary} \ + ${host_binary_signed} + +} From patchwork Tue Nov 23 15:59:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 355ADC433EF for ; Tue, 23 Nov 2021 16:00:13 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.13286.1637683212500260267 for ; Tue, 23 Nov 2021 08:00:12 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22BE81FB; Tue, 23 Nov 2021 08:00:12 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6F63A3F5A1; Tue, 23 Nov 2021 08:00:10 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Abdellatif El Khlifi , Jon Mason Subject: [PATCH][honister 16/19] arm-bsp/linux: corstone1000: integrating ARM_FFA_TRANSPORT in v5.10 kernel Date: Tue, 23 Nov 2021 15:59:23 +0000 Message-Id: <20211123155926.31743-17-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:13 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2445 From: Abdellatif El Khlifi This commit adds the Arm Firmware Framework for Armv8-A to the v5.10 kernel. The integrated patches are cherry-picked from kernel v5.14-rc2 and compatible with SMCCCv1.2 Change-Id: If8964b94ed83caa5e0fc5d2a8a9b6a21f8b378ec Signed-off-by: Abdellatif El Khlifi Signed-off-by: Jon Mason --- ...ccc-Add-SMCCC-TRNG-function-call-IDs.patch | 69 +++ ...smccc-Introduce-SMCCC-TRNG-framework.patch | 103 +++++ ...v1.2-extended-input-output-registers.patch | 192 ++++++++ ...A-bus-support-for-device-enumeration.patch | 423 ++++++++++++++++++ ...a-Add-initial-Arm-FFA-driver-support.patch | 422 +++++++++++++++++ ...for-SMCCC-as-transport-to-ffa-driver.patch | 119 +++++ ...up-in-kernel-users-of-FFA-partitions.patch | 410 +++++++++++++++++ ..._ffa-Add-support-for-MEM_-interfaces.patch | 409 +++++++++++++++++ ...ure-drivers-provide-a-probe-function.patch | 40 ++ ...ware-arm_ffa-Simplify-probe-function.patch | 38 ++ ...rmware-arm_ffa-Fix-the-comment-style.patch | 41 ++ ...ble-ffa_linux_errmap-buffer-overflow.patch | 46 ++ .../linux/files/corstone1000/defconfig | 1 + .../linux/linux-arm-platforms.inc | 12 + 14 files changed, 2325 insertions(+) create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0010-firmware-smccc-Add-SMCCC-TRNG-function-call-IDs.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0011-firmware-smccc-Introduce-SMCCC-TRNG-framework.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0012-arm64-smccc-Add-support-for-SMCCCv1.2-extended-input-output-registers.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0013-firmware-arm_ffa-Add-initial-FFA-bus-support-for-device-enumeration.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0014-firmware-arm_ffa-Add-initial-Arm-FFA-driver-support.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0015-firmware-arm_ffa-Add-support-for-SMCCC-as-transport-to-ffa-driver.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0016-firmware-arm_ffa-Setup-in-kernel-users-of-FFA-partitions.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0017-firmware-arm_ffa-Add-support-for-MEM_-interfaces.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0018-firmware-arm_ffa-Ensure-drivers-provide-a-probe-function.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0019-firmware-arm_ffa-Simplify-probe-function.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0020-firmware-arm_ffa-Fix-the-comment-style.patch create mode 100644 meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0021-firmware-arm_ffa-Fix-a-possible-ffa_linux_errmap-buffer-overflow.patch diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0010-firmware-smccc-Add-SMCCC-TRNG-function-call-IDs.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0010-firmware-smccc-Add-SMCCC-TRNG-function-call-IDs.patch new file mode 100644 index 0000000..56efe4d --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0010-firmware-smccc-Add-SMCCC-TRNG-function-call-IDs.patch @@ -0,0 +1,69 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From 67c6bb56b649590a3f59c2a92331aa4e83d4534c Mon Sep 17 00:00:00 2001 +From: Ard Biesheuvel +Date: Wed, 6 Jan 2021 10:34:49 +0000 +Subject: [PATCH] firmware: smccc: Add SMCCC TRNG function call IDs + +The ARM architected TRNG firmware interface, described in ARM spec +DEN0098, define an ARM SMCCC based interface to a true random number +generator, provided by firmware. + +Add the definitions of the SMCCC functions as defined by the spec. + +Signed-off-by: Ard Biesheuvel +Signed-off-by: Andre Przywara +Reviewed-by: Linus Walleij +Reviewed-by: Sudeep Holla +Link: https://lore.kernel.org/r/20210106103453.152275-2-andre.przywara@arm.com +Signed-off-by: Will Deacon +--- + include/linux/arm-smccc.h | 31 +++++++++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h +index f860645f6512..62c54234576c 100644 +--- a/include/linux/arm-smccc.h ++++ b/include/linux/arm-smccc.h +@@ -102,6 +102,37 @@ + ARM_SMCCC_OWNER_STANDARD_HYP, \ + 0x21) + ++/* TRNG entropy source calls (defined by ARM DEN0098) */ ++#define ARM_SMCCC_TRNG_VERSION \ ++ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ++ ARM_SMCCC_SMC_32, \ ++ ARM_SMCCC_OWNER_STANDARD, \ ++ 0x50) ++ ++#define ARM_SMCCC_TRNG_FEATURES \ ++ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ++ ARM_SMCCC_SMC_32, \ ++ ARM_SMCCC_OWNER_STANDARD, \ ++ 0x51) ++ ++#define ARM_SMCCC_TRNG_GET_UUID \ ++ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ++ ARM_SMCCC_SMC_32, \ ++ ARM_SMCCC_OWNER_STANDARD, \ ++ 0x52) ++ ++#define ARM_SMCCC_TRNG_RND32 \ ++ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ++ ARM_SMCCC_SMC_32, \ ++ ARM_SMCCC_OWNER_STANDARD, \ ++ 0x53) ++ ++#define ARM_SMCCC_TRNG_RND64 \ ++ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ ++ ARM_SMCCC_SMC_64, \ ++ ARM_SMCCC_OWNER_STANDARD, \ ++ 0x53) ++ + /* + * Return codes defined in ARM DEN 0070A + * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0011-firmware-smccc-Introduce-SMCCC-TRNG-framework.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0011-firmware-smccc-Introduce-SMCCC-TRNG-framework.patch new file mode 100644 index 0000000..44140fa --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0011-firmware-smccc-Introduce-SMCCC-TRNG-framework.patch @@ -0,0 +1,103 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From a37e31fc97efe7f7c68cb381cf4390e472c09061 Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Wed, 6 Jan 2021 10:34:50 +0000 +Subject: [PATCH] firmware: smccc: Introduce SMCCC TRNG framework + +The ARM DEN0098 document describe an SMCCC based firmware service to +deliver hardware generated random numbers. Its existence is advertised +according to the SMCCC v1.1 specification. + +Add a (dummy) call to probe functions implemented in each architecture +(ARM and arm64), to determine the existence of this interface. +For now this return false, but this will be overwritten by each +architecture's support patch. + +Signed-off-by: Andre Przywara +Reviewed-by: Linus Walleij +Reviewed-by: Sudeep Holla +Signed-off-by: Will Deacon +--- + arch/arm/include/asm/archrandom.h | 10 ++++++++++ + arch/arm64/include/asm/archrandom.h | 12 ++++++++++++ + drivers/firmware/smccc/smccc.c | 6 ++++++ + 3 files changed, 28 insertions(+) + create mode 100644 arch/arm/include/asm/archrandom.h + +diff --git a/arch/arm/include/asm/archrandom.h b/arch/arm/include/asm/archrandom.h +new file mode 100644 +index 000000000000..a8e84ca5c2ee +--- /dev/null ++++ b/arch/arm/include/asm/archrandom.h +@@ -0,0 +1,10 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef _ASM_ARCHRANDOM_H ++#define _ASM_ARCHRANDOM_H ++ ++static inline bool __init smccc_probe_trng(void) ++{ ++ return false; ++} ++ ++#endif /* _ASM_ARCHRANDOM_H */ +diff --git a/arch/arm64/include/asm/archrandom.h b/arch/arm64/include/asm/archrandom.h +index ffb1a40d5475..abe07c21da8e 100644 +--- a/arch/arm64/include/asm/archrandom.h ++++ b/arch/arm64/include/asm/archrandom.h +@@ -8,6 +8,11 @@ + #include + #include + ++static inline bool __init smccc_probe_trng(void) ++{ ++ return false; ++} ++ + static inline bool __arm64_rndr(unsigned long *v) + { + bool ok; +@@ -79,5 +84,12 @@ arch_get_random_seed_long_early(unsigned long *v) + } + #define arch_get_random_seed_long_early arch_get_random_seed_long_early + ++#else /* !CONFIG_ARCH_RANDOM */ ++ ++static inline bool __init smccc_probe_trng(void) ++{ ++ return false; ++} ++ + #endif /* CONFIG_ARCH_RANDOM */ + #endif /* _ASM_ARCHRANDOM_H */ +diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c +index 00c88b809c0c..d52bfc5ed5e4 100644 +--- a/drivers/firmware/smccc/smccc.c ++++ b/drivers/firmware/smccc/smccc.c +@@ -5,16 +5,22 @@ + + #define pr_fmt(fmt) "smccc: " fmt + ++#include + #include + #include ++#include + + static u32 smccc_version = ARM_SMCCC_VERSION_1_0; + static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE; + ++bool __ro_after_init smccc_trng_available = false; ++ + void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit) + { + smccc_version = version; + smccc_conduit = conduit; ++ ++ smccc_trng_available = smccc_probe_trng(); + } + + enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void) +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0012-arm64-smccc-Add-support-for-SMCCCv1.2-extended-input-output-registers.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0012-arm64-smccc-Add-support-for-SMCCCv1.2-extended-input-output-registers.patch new file mode 100644 index 0000000..c338a50 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0012-arm64-smccc-Add-support-for-SMCCCv1.2-extended-input-output-registers.patch @@ -0,0 +1,192 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From 3fdc0cb59d97f87e2cc708d424f1538e31744286 Mon Sep 17 00:00:00 2001 +From: Sudeep Holla +Date: Tue, 18 May 2021 17:36:18 +0100 +Subject: [PATCH] arm64: smccc: Add support for SMCCCv1.2 extended input/output + registers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +SMCCC v1.2 allows x8-x17 to be used as parameter registers and x4—x17 +to be used as result registers in SMC64/HVC64. Arm Firmware Framework +for Armv8-A specification makes use of x0-x7 as parameter and result +registers. There are other users like Hyper-V who intend to use beyond +x0-x7 as well. + +Current SMCCC interface in the kernel just use x0-x7 as parameter and +x0-x3 as result registers as required by SMCCCv1.0. Let us add new +interface to support this extended set of input/output registers namely +x0-x17 as both parameter and result registers. + +Acked-by: Mark Rutland +Tested-by: Michael Kelley +Reviewed-by: Michael Kelley +Cc: Will Deacon +Cc: Catalin Marinas +Signed-off-by: Sudeep Holla +Reviewed-by: Mark Brown +Link: https://lore.kernel.org/r/20210518163618.43950-1-sudeep.holla@arm.com +Signed-off-by: Will Deacon +--- + arch/arm64/kernel/asm-offsets.c | 9 ++++++ + arch/arm64/kernel/smccc-call.S | 57 +++++++++++++++++++++++++++++++++ + include/linux/arm-smccc.h | 55 +++++++++++++++++++++++++++++++ + 3 files changed, 121 insertions(+) + +diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c +index 0cb34ccb6e73..74321bc9a459 100644 +--- a/arch/arm64/kernel/asm-offsets.c ++++ b/arch/arm64/kernel/asm-offsets.c +@@ -138,6 +138,15 @@ int main(void) + DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); + DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); + DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); ++ DEFINE(ARM_SMCCC_1_2_REGS_X0_OFFS, offsetof(struct arm_smccc_1_2_regs, a0)); ++ DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS, offsetof(struct arm_smccc_1_2_regs, a2)); ++ DEFINE(ARM_SMCCC_1_2_REGS_X4_OFFS, offsetof(struct arm_smccc_1_2_regs, a4)); ++ DEFINE(ARM_SMCCC_1_2_REGS_X6_OFFS, offsetof(struct arm_smccc_1_2_regs, a6)); ++ DEFINE(ARM_SMCCC_1_2_REGS_X8_OFFS, offsetof(struct arm_smccc_1_2_regs, a8)); ++ DEFINE(ARM_SMCCC_1_2_REGS_X10_OFFS, offsetof(struct arm_smccc_1_2_regs, a10)); ++ DEFINE(ARM_SMCCC_1_2_REGS_X12_OFFS, offsetof(struct arm_smccc_1_2_regs, a12)); ++ DEFINE(ARM_SMCCC_1_2_REGS_X14_OFFS, offsetof(struct arm_smccc_1_2_regs, a14)); ++ DEFINE(ARM_SMCCC_1_2_REGS_X16_OFFS, offsetof(struct arm_smccc_1_2_regs, a16)); + BLANK(); + DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address)); + DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address)); +diff --git a/arch/arm64/kernel/smccc-call.S b/arch/arm64/kernel/smccc-call.S +index d62447964ed9..2def9d0dd3dd 100644 +--- a/arch/arm64/kernel/smccc-call.S ++++ b/arch/arm64/kernel/smccc-call.S +@@ -43,3 +43,60 @@ SYM_FUNC_START(__arm_smccc_hvc) + SMCCC hvc + SYM_FUNC_END(__arm_smccc_hvc) + EXPORT_SYMBOL(__arm_smccc_hvc) ++ ++ .macro SMCCC_1_2 instr ++ /* Save `res` and free a GPR that won't be clobbered */ ++ stp x1, x19, [sp, #-16]! ++ ++ /* Ensure `args` won't be clobbered while loading regs in next step */ ++ mov x19, x0 ++ ++ /* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */ ++ ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS] ++ ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS] ++ ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS] ++ ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS] ++ ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS] ++ ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS] ++ ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS] ++ ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] ++ ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] ++ ++ \instr #0 ++ ++ /* Load the `res` from the stack */ ++ ldr x19, [sp] ++ ++ /* Store the registers x0 - x17 into the result structure */ ++ stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS] ++ stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS] ++ stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS] ++ stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS] ++ stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS] ++ stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS] ++ stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS] ++ stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] ++ stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] ++ ++ /* Restore original x19 */ ++ ldp xzr, x19, [sp], #16 ++ ret ++.endm ++ ++/* ++ * void arm_smccc_1_2_hvc(const struct arm_smccc_1_2_regs *args, ++ * struct arm_smccc_1_2_regs *res); ++ */ ++SYM_FUNC_START(arm_smccc_1_2_hvc) ++ SMCCC_1_2 hvc ++SYM_FUNC_END(arm_smccc_1_2_hvc) ++EXPORT_SYMBOL(arm_smccc_1_2_hvc) ++ ++/* ++ * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, ++ * struct arm_smccc_1_2_regs *res); ++ */ ++SYM_FUNC_START(arm_smccc_1_2_smc) ++ SMCCC_1_2 smc ++SYM_FUNC_END(arm_smccc_1_2_smc) ++EXPORT_SYMBOL(arm_smccc_1_2_smc) +diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h +index 6861489a1890..5cef2b8b0479 100644 +--- a/include/linux/arm-smccc.h ++++ b/include/linux/arm-smccc.h +@@ -227,6 +227,61 @@ struct arm_smccc_res { + unsigned long a3; + }; + ++#ifdef CONFIG_ARM64 ++/** ++ * struct arm_smccc_1_2_regs - Arguments for or Results from SMC/HVC call ++ * @a0-a17 argument values from registers 0 to 17 ++ */ ++struct arm_smccc_1_2_regs { ++ unsigned long a0; ++ unsigned long a1; ++ unsigned long a2; ++ unsigned long a3; ++ unsigned long a4; ++ unsigned long a5; ++ unsigned long a6; ++ unsigned long a7; ++ unsigned long a8; ++ unsigned long a9; ++ unsigned long a10; ++ unsigned long a11; ++ unsigned long a12; ++ unsigned long a13; ++ unsigned long a14; ++ unsigned long a15; ++ unsigned long a16; ++ unsigned long a17; ++}; ++ ++/** ++ * arm_smccc_1_2_hvc() - make HVC calls ++ * @args: arguments passed via struct arm_smccc_1_2_regs ++ * @res: result values via struct arm_smccc_1_2_regs ++ * ++ * This function is used to make HVC calls following SMC Calling Convention ++ * v1.2 or above. The content of the supplied param are copied from the ++ * structure to registers prior to the HVC instruction. The return values ++ * are updated with the content from registers on return from the HVC ++ * instruction. ++ */ ++asmlinkage void arm_smccc_1_2_hvc(const struct arm_smccc_1_2_regs *args, ++ struct arm_smccc_1_2_regs *res); ++ ++/** ++ * arm_smccc_1_2_smc() - make SMC calls ++ * @args: arguments passed via struct arm_smccc_1_2_regs ++ * @res: result values via struct arm_smccc_1_2_regs ++ * ++ * This function is used to make SMC calls following SMC Calling Convention ++ * v1.2 or above. The content of the supplied param are copied from the ++ * structure to registers prior to the SMC instruction. The return values ++ * are updated with the content from registers on return from the SMC ++ * instruction. ++ */ ++asmlinkage void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, ++ struct arm_smccc_1_2_regs *res); ++#endif ++ + /** + * struct arm_smccc_quirk - Contains quirk information + * @id: quirk identification +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0013-firmware-arm_ffa-Add-initial-FFA-bus-support-for-device-enumeration.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0013-firmware-arm_ffa-Add-initial-FFA-bus-support-for-device-enumeration.patch new file mode 100644 index 0000000..511d63e --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0013-firmware-arm_ffa-Add-initial-FFA-bus-support-for-device-enumeration.patch @@ -0,0 +1,423 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From e781858488b918e30a6ff28e9eab6058b787e3b3 Mon Sep 17 00:00:00 2001 +From: Sudeep Holla +Date: Fri, 21 May 2021 16:10:29 +0100 +Subject: [PATCH] firmware: arm_ffa: Add initial FFA bus support for device + enumeration + +The Arm FF for Armv8-A specification has concept of endpoints or +partitions. In the Normal world, a partition could be a VM when +the Virtualization extension is enabled or the kernel itself. + +In order to handle multiple partitions, we can create a FFA device for +each such partition on a dedicated FFA bus. Similarly, different drivers +requiring FFA transport can be registered on the same bus. We can match +the device and drivers using UUID. This is mostly for the in-kernel +users with FFA drivers. + +Link: https://lore.kernel.org/r/20210521151033.181846-2-sudeep.holla@arm.com +Tested-by: Jens Wiklander +Signed-off-by: Sudeep Holla +--- + MAINTAINERS | 7 + + drivers/firmware/Kconfig | 1 + + drivers/firmware/Makefile | 1 + + drivers/firmware/arm_ffa/Kconfig | 16 +++ + drivers/firmware/arm_ffa/Makefile | 4 + + drivers/firmware/arm_ffa/bus.c | 207 ++++++++++++++++++++++++++++++ + include/linux/arm_ffa.h | 91 +++++++++++++ + 7 files changed, 327 insertions(+) + create mode 100644 drivers/firmware/arm_ffa/Kconfig + create mode 100644 drivers/firmware/arm_ffa/Makefile + create mode 100644 drivers/firmware/arm_ffa/bus.c + create mode 100644 include/linux/arm_ffa.h + +diff --git a/MAINTAINERS b/MAINTAINERS +index bd7aff0c120f..3b8ab94cf697 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -7069,6 +7069,13 @@ F: include/linux/firewire.h + F: include/uapi/linux/firewire*.h + F: tools/firewire/ + ++FIRMWARE FRAMEWORK FOR ARMV8-A ++M: Sudeep Holla ++L: linux-arm-kernel@lists.infradead.org ++S: Maintained ++F: drivers/firmware/arm_ffa/ ++F: include/linux/arm_ffa.h ++ + FIRMWARE LOADER (request_firmware) + M: Luis Chamberlain + L: linux-kernel@vger.kernel.org +diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig +index db0ea2d2d75a..b53ac9fc7704 100644 +--- a/drivers/firmware/Kconfig ++++ b/drivers/firmware/Kconfig +@@ -296,6 +296,7 @@ config TURRIS_MOX_RWTM + other manufacturing data and also utilize the Entropy Bit Generator + for hardware random number generation. + ++source "drivers/firmware/arm_ffa/Kconfig" + source "drivers/firmware/broadcom/Kconfig" + source "drivers/firmware/google/Kconfig" + source "drivers/firmware/efi/Kconfig" +diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile +index 5e013b6a3692..546ac8e7f6d0 100644 +--- a/drivers/firmware/Makefile ++++ b/drivers/firmware/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o + obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o + obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o + ++obj-y += arm_ffa/ + obj-y += arm_scmi/ + obj-y += broadcom/ + obj-y += meson/ +diff --git a/drivers/firmware/arm_ffa/Kconfig b/drivers/firmware/arm_ffa/Kconfig +new file mode 100644 +index 000000000000..261a3660650a +--- /dev/null ++++ b/drivers/firmware/arm_ffa/Kconfig +@@ -0,0 +1,16 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config ARM_FFA_TRANSPORT ++ tristate "Arm Firmware Framework for Armv8-A" ++ depends on OF ++ depends on ARM64 ++ default n ++ help ++ This Firmware Framework(FF) for Arm A-profile processors describes ++ interfaces that standardize communication between the various ++ software images which includes communication between images in ++ the Secure world and Normal world. It also leverages the ++ virtualization extension to isolate software images provided ++ by an ecosystem of vendors from each other. ++ ++ This driver provides interface for all the client drivers making ++ use of the features offered by ARM FF-A. +diff --git a/drivers/firmware/arm_ffa/Makefile b/drivers/firmware/arm_ffa/Makefile +new file mode 100644 +index 000000000000..bfe4323a8784 +--- /dev/null ++++ b/drivers/firmware/arm_ffa/Makefile +@@ -0,0 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ffa-bus-y = bus.o ++ffa-module-objs := $(ffa-bus-y) ++obj-$(CONFIG_ARM_FFA_TRANSPORT) = ffa-module.o +diff --git a/drivers/firmware/arm_ffa/bus.c b/drivers/firmware/arm_ffa/bus.c +new file mode 100644 +index 000000000000..a17874bed946 +--- /dev/null ++++ b/drivers/firmware/arm_ffa/bus.c +@@ -0,0 +1,207 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2021 ARM Ltd. ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int ffa_device_match(struct device *dev, struct device_driver *drv) ++{ ++ const struct ffa_device_id *id_table; ++ struct ffa_device *ffa_dev; ++ ++ id_table = to_ffa_driver(drv)->id_table; ++ ffa_dev = to_ffa_dev(dev); ++ ++ while (!uuid_is_null(&id_table->uuid)) { ++ if (uuid_equal(&ffa_dev->uuid, &id_table->uuid)) ++ return 1; ++ id_table++; ++ } ++ ++ return 0; ++} ++ ++static int ffa_device_probe(struct device *dev) ++{ ++ struct ffa_driver *ffa_drv = to_ffa_driver(dev->driver); ++ struct ffa_device *ffa_dev = to_ffa_dev(dev); ++ ++ if (!ffa_device_match(dev, dev->driver)) ++ return -ENODEV; ++ ++ return ffa_drv->probe(ffa_dev); ++} ++ ++static int ffa_device_uevent(struct device *dev, struct kobj_uevent_env *env) ++{ ++ struct ffa_device *ffa_dev = to_ffa_dev(dev); ++ ++ return add_uevent_var(env, "MODALIAS=arm_ffa:%04x:%pUb", ++ ffa_dev->vm_id, &ffa_dev->uuid); ++} ++ ++static ssize_t partition_id_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct ffa_device *ffa_dev = to_ffa_dev(dev); ++ ++ return sprintf(buf, "0x%04x\n", ffa_dev->vm_id); ++} ++static DEVICE_ATTR_RO(partition_id); ++ ++static ssize_t uuid_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct ffa_device *ffa_dev = to_ffa_dev(dev); ++ ++ return sprintf(buf, "%pUb\n", &ffa_dev->uuid); ++} ++static DEVICE_ATTR_RO(uuid); ++ ++static struct attribute *ffa_device_attributes_attrs[] = { ++ &dev_attr_partition_id.attr, ++ &dev_attr_uuid.attr, ++ NULL, ++}; ++ATTRIBUTE_GROUPS(ffa_device_attributes); ++ ++struct bus_type ffa_bus_type = { ++ .name = "arm_ffa", ++ .match = ffa_device_match, ++ .probe = ffa_device_probe, ++ .uevent = ffa_device_uevent, ++ .dev_groups = ffa_device_attributes_groups, ++}; ++EXPORT_SYMBOL_GPL(ffa_bus_type); ++ ++int ffa_driver_register(struct ffa_driver *driver, struct module *owner, ++ const char *mod_name) ++{ ++ int ret; ++ ++ driver->driver.bus = &ffa_bus_type; ++ driver->driver.name = driver->name; ++ driver->driver.owner = owner; ++ driver->driver.mod_name = mod_name; ++ ++ ret = driver_register(&driver->driver); ++ if (!ret) ++ pr_debug("registered new ffa driver %s\n", driver->name); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(ffa_driver_register); ++ ++void ffa_driver_unregister(struct ffa_driver *driver) ++{ ++ driver_unregister(&driver->driver); ++} ++EXPORT_SYMBOL_GPL(ffa_driver_unregister); ++ ++static void ffa_release_device(struct device *dev) ++{ ++ struct ffa_device *ffa_dev = to_ffa_dev(dev); ++ ++ kfree(ffa_dev); ++} ++ ++static int __ffa_devices_unregister(struct device *dev, void *data) ++{ ++ ffa_release_device(dev); ++ ++ return 0; ++} ++ ++static void ffa_devices_unregister(void) ++{ ++ bus_for_each_dev(&ffa_bus_type, NULL, NULL, ++ __ffa_devices_unregister); ++} ++ ++bool ffa_device_is_valid(struct ffa_device *ffa_dev) ++{ ++ bool valid = false; ++ struct device *dev = NULL; ++ struct ffa_device *tmp_dev; ++ ++ do { ++ dev = bus_find_next_device(&ffa_bus_type, dev); ++ tmp_dev = to_ffa_dev(dev); ++ if (tmp_dev == ffa_dev) { ++ valid = true; ++ break; ++ } ++ put_device(dev); ++ } while (dev); ++ ++ put_device(dev); ++ ++ return valid; ++} ++ ++struct ffa_device *ffa_device_register(const uuid_t *uuid, int vm_id) ++{ ++ int ret; ++ struct device *dev; ++ struct ffa_device *ffa_dev; ++ ++ ffa_dev = kzalloc(sizeof(*ffa_dev), GFP_KERNEL); ++ if (!ffa_dev) ++ return NULL; ++ ++ dev = &ffa_dev->dev; ++ dev->bus = &ffa_bus_type; ++ dev->release = ffa_release_device; ++ dev_set_name(&ffa_dev->dev, "arm-ffa-%04x", vm_id); ++ ++ ffa_dev->vm_id = vm_id; ++ uuid_copy(&ffa_dev->uuid, uuid); ++ ++ ret = device_register(&ffa_dev->dev); ++ if (ret) { ++ dev_err(dev, "unable to register device %s err=%d\n", ++ dev_name(dev), ret); ++ put_device(dev); ++ return NULL; ++ } ++ ++ return ffa_dev; ++} ++EXPORT_SYMBOL_GPL(ffa_device_register); ++ ++void ffa_device_unregister(struct ffa_device *ffa_dev) ++{ ++ if (!ffa_dev) ++ return; ++ ++ device_unregister(&ffa_dev->dev); ++} ++EXPORT_SYMBOL_GPL(ffa_device_unregister); ++ ++static int __init arm_ffa_bus_init(void) ++{ ++ return bus_register(&ffa_bus_type); ++} ++module_init(arm_ffa_bus_init); ++ ++static void __exit arm_ffa_bus_exit(void) ++{ ++ ffa_devices_unregister(); ++ bus_unregister(&ffa_bus_type); ++} ++ ++module_exit(arm_ffa_bus_exit); ++ ++MODULE_ALIAS("arm-ffa-bus"); ++MODULE_AUTHOR("Sudeep Holla "); ++MODULE_DESCRIPTION("Arm FF-A bus driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h +new file mode 100644 +index 000000000000..331ff62c9873 +--- /dev/null ++++ b/include/linux/arm_ffa.h +@@ -0,0 +1,91 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2021 ARM Ltd. ++ */ ++ ++#ifndef _LINUX_ARM_FFA_H ++#define _LINUX_ARM_FFA_H ++ ++#include ++#include ++#include ++#include ++#include ++ ++/* FFA Bus/Device/Driver related */ ++struct ffa_device { ++ int vm_id; ++ uuid_t uuid; ++ struct device dev; ++}; ++ ++#define to_ffa_dev(d) container_of(d, struct ffa_device, dev) ++ ++struct ffa_device_id { ++ uuid_t uuid; ++}; ++ ++struct ffa_driver { ++ const char *name; ++ int (*probe)(struct ffa_device *sdev); ++ void (*remove)(struct ffa_device *sdev); ++ const struct ffa_device_id *id_table; ++ ++ struct device_driver driver; ++}; ++ ++#define to_ffa_driver(d) container_of(d, struct ffa_driver, driver) ++ ++static inline void ffa_dev_set_drvdata(struct ffa_device *fdev, void *data) ++{ ++ fdev->dev.driver_data = data; ++} ++ ++#if IS_REACHABLE(CONFIG_ARM_FFA_TRANSPORT) ++struct ffa_device *ffa_device_register(const uuid_t *uuid, int vm_id); ++void ffa_device_unregister(struct ffa_device *ffa_dev); ++int ffa_driver_register(struct ffa_driver *driver, struct module *owner, ++ const char *mod_name); ++void ffa_driver_unregister(struct ffa_driver *driver); ++bool ffa_device_is_valid(struct ffa_device *ffa_dev); ++ ++#else ++static inline ++struct ffa_device *ffa_device_register(const uuid_t *uuid, int vm_id) ++{ ++ return NULL; ++} ++ ++static inline void ffa_device_unregister(struct ffa_device *dev) {} ++ ++static inline int ++ffa_driver_register(struct ffa_driver *driver, struct module *owner, ++ const char *mod_name) ++{ ++ return -EINVAL; ++} ++ ++static inline void ffa_driver_unregister(struct ffa_driver *driver) {} ++ ++static inline ++bool ffa_device_is_valid(struct ffa_device *ffa_dev) { return false; } ++ ++#endif /* CONFIG_ARM_FFA_TRANSPORT */ ++ ++#define ffa_register(driver) \ ++ ffa_driver_register(driver, THIS_MODULE, KBUILD_MODNAME) ++#define ffa_unregister(driver) \ ++ ffa_driver_unregister(driver) ++ ++/** ++ * module_ffa_driver() - Helper macro for registering a psa_ffa driver ++ * @__ffa_driver: ffa_driver structure ++ * ++ * Helper macro for psa_ffa drivers to set up proper module init / exit ++ * functions. Replaces module_init() and module_exit() and keeps people from ++ * printing pointless things to the kernel log when their driver is loaded. ++ */ ++#define module_ffa_driver(__ffa_driver) \ ++ module_driver(__ffa_driver, ffa_register, ffa_unregister) ++ ++#endif /* _LINUX_ARM_FFA_H */ +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0014-firmware-arm_ffa-Add-initial-Arm-FFA-driver-support.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0014-firmware-arm_ffa-Add-initial-Arm-FFA-driver-support.patch new file mode 100644 index 0000000..c0dcfdc --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0014-firmware-arm_ffa-Add-initial-Arm-FFA-driver-support.patch @@ -0,0 +1,422 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From 3bbfe9871005f38df2955b2e125933edf1d2feef Mon Sep 17 00:00:00 2001 +From: Sudeep Holla +Date: Fri, 21 May 2021 16:10:30 +0100 +Subject: [PATCH] firmware: arm_ffa: Add initial Arm FFA driver support + +This just add a basic driver that sets up the transport(e.g. SMCCC), +checks the FFA version implemented, get the partition ID for self and +sets up the Tx/Rx buffers for communication. + +Link: https://lore.kernel.org/r/20210521151033.181846-3-sudeep.holla@arm.com +Tested-by: Jens Wiklander +Signed-off-by: Sudeep Holla +--- + drivers/firmware/arm_ffa/Makefile | 3 +- + drivers/firmware/arm_ffa/bus.c | 14 +- + drivers/firmware/arm_ffa/common.h | 24 +++ + drivers/firmware/arm_ffa/driver.c | 311 ++++++++++++++++++++++++++++++ + 4 files changed, 341 insertions(+), 11 deletions(-) + create mode 100644 drivers/firmware/arm_ffa/common.h + create mode 100644 drivers/firmware/arm_ffa/driver.c + +diff --git a/drivers/firmware/arm_ffa/Makefile b/drivers/firmware/arm_ffa/Makefile +index bfe4323a8784..82d0d35c5324 100644 +--- a/drivers/firmware/arm_ffa/Makefile ++++ b/drivers/firmware/arm_ffa/Makefile +@@ -1,4 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0-only + ffa-bus-y = bus.o +-ffa-module-objs := $(ffa-bus-y) ++ffa-driver-y = driver.o ++ffa-module-objs := $(ffa-bus-y) $(ffa-driver-y) + obj-$(CONFIG_ARM_FFA_TRANSPORT) = ffa-module.o +diff --git a/drivers/firmware/arm_ffa/bus.c b/drivers/firmware/arm_ffa/bus.c +index a17874bed946..ae1eada5dc0c 100644 +--- a/drivers/firmware/arm_ffa/bus.c ++++ b/drivers/firmware/arm_ffa/bus.c +@@ -13,6 +13,8 @@ + #include + #include + ++#include "common.h" ++ + static int ffa_device_match(struct device *dev, struct device_driver *drv) + { + const struct ffa_device_id *id_table; +@@ -187,21 +189,13 @@ void ffa_device_unregister(struct ffa_device *ffa_dev) + } + EXPORT_SYMBOL_GPL(ffa_device_unregister); + +-static int __init arm_ffa_bus_init(void) ++int arm_ffa_bus_init(void) + { + return bus_register(&ffa_bus_type); + } +-module_init(arm_ffa_bus_init); + +-static void __exit arm_ffa_bus_exit(void) ++void arm_ffa_bus_exit(void) + { + ffa_devices_unregister(); + bus_unregister(&ffa_bus_type); + } +- +-module_exit(arm_ffa_bus_exit); +- +-MODULE_ALIAS("arm-ffa-bus"); +-MODULE_AUTHOR("Sudeep Holla "); +-MODULE_DESCRIPTION("Arm FF-A bus driver"); +-MODULE_LICENSE("GPL v2"); +diff --git a/drivers/firmware/arm_ffa/common.h b/drivers/firmware/arm_ffa/common.h +new file mode 100644 +index 000000000000..2d3a32f67d5d +--- /dev/null ++++ b/drivers/firmware/arm_ffa/common.h +@@ -0,0 +1,24 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2021 ARM Ltd. ++ */ ++ ++#ifndef _FFA_COMMON_H ++#define _FFA_COMMON_H ++ ++#include ++#include ++ ++typedef struct arm_smccc_1_2_regs ffa_value_t; ++ ++typedef void (ffa_fn)(ffa_value_t, ffa_value_t *); ++ ++int arm_ffa_bus_init(void); ++void arm_ffa_bus_exit(void); ++ ++static inline int __init ffa_transport_init(ffa_fn **invoke_ffa_fn) ++{ ++ return -EOPNOTSUPP; ++} ++ ++#endif /* _FFA_COMMON_H */ +diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c +new file mode 100644 +index 000000000000..4846f079dca0 +--- /dev/null ++++ b/drivers/firmware/arm_ffa/driver.c +@@ -0,0 +1,311 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Arm Firmware Framework for ARMv8-A(FFA) interface driver ++ * ++ * The Arm FFA specification[1] describes a software architecture to ++ * leverages the virtualization extension to isolate software images ++ * provided by an ecosystem of vendors from each other and describes ++ * interfaces that standardize communication between the various software ++ * images including communication between images in the Secure world and ++ * Normal world. Any Hypervisor could use the FFA interfaces to enable ++ * communication between VMs it manages. ++ * ++ * The Hypervisor a.k.a Partition managers in FFA terminology can assign ++ * system resources(Memory regions, Devices, CPU cycles) to the partitions ++ * and manage isolation amongst them. ++ * ++ * [1] https://developer.arm.com/docs/den0077/latest ++ * ++ * Copyright (C) 2021 ARM Ltd. ++ */ ++ ++#define DRIVER_NAME "ARM FF-A" ++#define pr_fmt(fmt) DRIVER_NAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "common.h" ++ ++#define FFA_DRIVER_VERSION FFA_VERSION_1_0 ++ ++#define FFA_SMC(calling_convention, func_num) \ ++ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, (calling_convention), \ ++ ARM_SMCCC_OWNER_STANDARD, (func_num)) ++ ++#define FFA_SMC_32(func_num) FFA_SMC(ARM_SMCCC_SMC_32, (func_num)) ++#define FFA_SMC_64(func_num) FFA_SMC(ARM_SMCCC_SMC_64, (func_num)) ++ ++#define FFA_ERROR FFA_SMC_32(0x60) ++#define FFA_SUCCESS FFA_SMC_32(0x61) ++#define FFA_INTERRUPT FFA_SMC_32(0x62) ++#define FFA_VERSION FFA_SMC_32(0x63) ++#define FFA_FEATURES FFA_SMC_32(0x64) ++#define FFA_RX_RELEASE FFA_SMC_32(0x65) ++#define FFA_RXTX_MAP FFA_SMC_32(0x66) ++#define FFA_FN64_RXTX_MAP FFA_SMC_64(0x66) ++#define FFA_RXTX_UNMAP FFA_SMC_32(0x67) ++#define FFA_PARTITION_INFO_GET FFA_SMC_32(0x68) ++#define FFA_ID_GET FFA_SMC_32(0x69) ++#define FFA_MSG_POLL FFA_SMC_32(0x6A) ++#define FFA_MSG_WAIT FFA_SMC_32(0x6B) ++#define FFA_YIELD FFA_SMC_32(0x6C) ++#define FFA_RUN FFA_SMC_32(0x6D) ++#define FFA_MSG_SEND FFA_SMC_32(0x6E) ++#define FFA_MSG_SEND_DIRECT_REQ FFA_SMC_32(0x6F) ++#define FFA_FN64_MSG_SEND_DIRECT_REQ FFA_SMC_64(0x6F) ++#define FFA_MSG_SEND_DIRECT_RESP FFA_SMC_32(0x70) ++#define FFA_FN64_MSG_SEND_DIRECT_RESP FFA_SMC_64(0x70) ++#define FFA_MEM_DONATE FFA_SMC_32(0x71) ++#define FFA_FN64_MEM_DONATE FFA_SMC_64(0x71) ++#define FFA_MEM_LEND FFA_SMC_32(0x72) ++#define FFA_FN64_MEM_LEND FFA_SMC_64(0x72) ++#define FFA_MEM_SHARE FFA_SMC_32(0x73) ++#define FFA_FN64_MEM_SHARE FFA_SMC_64(0x73) ++#define FFA_MEM_RETRIEVE_REQ FFA_SMC_32(0x74) ++#define FFA_FN64_MEM_RETRIEVE_REQ FFA_SMC_64(0x74) ++#define FFA_MEM_RETRIEVE_RESP FFA_SMC_32(0x75) ++#define FFA_MEM_RELINQUISH FFA_SMC_32(0x76) ++#define FFA_MEM_RECLAIM FFA_SMC_32(0x77) ++#define FFA_MEM_OP_PAUSE FFA_SMC_32(0x78) ++#define FFA_MEM_OP_RESUME FFA_SMC_32(0x79) ++#define FFA_MEM_FRAG_RX FFA_SMC_32(0x7A) ++#define FFA_MEM_FRAG_TX FFA_SMC_32(0x7B) ++#define FFA_NORMAL_WORLD_RESUME FFA_SMC_32(0x7C) ++ ++/* ++ * For some calls it is necessary to use SMC64 to pass or return 64-bit values. ++ * For such calls FFA_FN_NATIVE(name) will choose the appropriate ++ * (native-width) function ID. ++ */ ++#ifdef CONFIG_64BIT ++#define FFA_FN_NATIVE(name) FFA_FN64_##name ++#else ++#define FFA_FN_NATIVE(name) FFA_##name ++#endif ++ ++/* FFA error codes. */ ++#define FFA_RET_SUCCESS (0) ++#define FFA_RET_NOT_SUPPORTED (-1) ++#define FFA_RET_INVALID_PARAMETERS (-2) ++#define FFA_RET_NO_MEMORY (-3) ++#define FFA_RET_BUSY (-4) ++#define FFA_RET_INTERRUPTED (-5) ++#define FFA_RET_DENIED (-6) ++#define FFA_RET_RETRY (-7) ++#define FFA_RET_ABORTED (-8) ++ ++#define MAJOR_VERSION_MASK GENMASK(30, 16) ++#define MINOR_VERSION_MASK GENMASK(15, 0) ++#define MAJOR_VERSION(x) ((u16)(FIELD_GET(MAJOR_VERSION_MASK, (x)))) ++#define MINOR_VERSION(x) ((u16)(FIELD_GET(MINOR_VERSION_MASK, (x)))) ++#define PACK_VERSION_INFO(major, minor) \ ++ (FIELD_PREP(MAJOR_VERSION_MASK, (major)) | \ ++ FIELD_PREP(MINOR_VERSION_MASK, (minor))) ++#define FFA_VERSION_1_0 PACK_VERSION_INFO(1, 0) ++#define FFA_MIN_VERSION FFA_VERSION_1_0 ++ ++#define SENDER_ID_MASK GENMASK(31, 16) ++#define RECEIVER_ID_MASK GENMASK(15, 0) ++#define SENDER_ID(x) ((u16)(FIELD_GET(SENDER_ID_MASK, (x)))) ++#define RECEIVER_ID(x) ((u16)(FIELD_GET(RECEIVER_ID_MASK, (x)))) ++#define PACK_TARGET_INFO(s, r) \ ++ (FIELD_PREP(SENDER_ID_MASK, (s)) | FIELD_PREP(RECEIVER_ID_MASK, (r))) ++ ++/** ++ * FF-A specification mentions explicitly about '4K pages'. This should ++ * not be confused with the kernel PAGE_SIZE, which is the translation ++ * granule kernel is configured and may be one among 4K, 16K and 64K. ++ */ ++#define FFA_PAGE_SIZE SZ_4K ++/* ++ * Keeping RX TX buffer size as 4K for now ++ * 64K may be preferred to keep it min a page in 64K PAGE_SIZE config ++ */ ++#define RXTX_BUFFER_SIZE SZ_4K ++ ++static ffa_fn *invoke_ffa_fn; ++ ++static const int ffa_linux_errmap[] = { ++ /* better than switch case as long as return value is continuous */ ++ 0, /* FFA_RET_SUCCESS */ ++ -EOPNOTSUPP, /* FFA_RET_NOT_SUPPORTED */ ++ -EINVAL, /* FFA_RET_INVALID_PARAMETERS */ ++ -ENOMEM, /* FFA_RET_NO_MEMORY */ ++ -EBUSY, /* FFA_RET_BUSY */ ++ -EINTR, /* FFA_RET_INTERRUPTED */ ++ -EACCES, /* FFA_RET_DENIED */ ++ -EAGAIN, /* FFA_RET_RETRY */ ++ -ECANCELED, /* FFA_RET_ABORTED */ ++}; ++ ++static inline int ffa_to_linux_errno(int errno) ++{ ++ if (errno < FFA_RET_SUCCESS && errno >= -ARRAY_SIZE(ffa_linux_errmap)) ++ return ffa_linux_errmap[-errno]; ++ return -EINVAL; ++} ++ ++struct ffa_drv_info { ++ u32 version; ++ u16 vm_id; ++ struct mutex rx_lock; /* lock to protect Rx buffer */ ++ struct mutex tx_lock; /* lock to protect Tx buffer */ ++ void *rx_buffer; ++ void *tx_buffer; ++}; ++ ++static struct ffa_drv_info *drv_info; ++ ++static int ffa_version_check(u32 *version) ++{ ++ ffa_value_t ver; ++ ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_VERSION, .a1 = FFA_DRIVER_VERSION, ++ }, &ver); ++ ++ if (ver.a0 == FFA_RET_NOT_SUPPORTED) { ++ pr_info("FFA_VERSION returned not supported\n"); ++ return -EOPNOTSUPP; ++ } ++ ++ if (ver.a0 < FFA_MIN_VERSION || ver.a0 > FFA_DRIVER_VERSION) { ++ pr_err("Incompatible version %d.%d found\n", ++ MAJOR_VERSION(ver.a0), MINOR_VERSION(ver.a0)); ++ return -EINVAL; ++ } ++ ++ *version = ver.a0; ++ pr_info("Version %d.%d found\n", MAJOR_VERSION(ver.a0), ++ MINOR_VERSION(ver.a0)); ++ return 0; ++} ++ ++static int ffa_rxtx_map(phys_addr_t tx_buf, phys_addr_t rx_buf, u32 pg_cnt) ++{ ++ ffa_value_t ret; ++ ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_FN_NATIVE(RXTX_MAP), ++ .a1 = tx_buf, .a2 = rx_buf, .a3 = pg_cnt, ++ }, &ret); ++ ++ if (ret.a0 == FFA_ERROR) ++ return ffa_to_linux_errno((int)ret.a2); ++ ++ return 0; ++} ++ ++static int ffa_rxtx_unmap(u16 vm_id) ++{ ++ ffa_value_t ret; ++ ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_RXTX_UNMAP, .a1 = PACK_TARGET_INFO(vm_id, 0), ++ }, &ret); ++ ++ if (ret.a0 == FFA_ERROR) ++ return ffa_to_linux_errno((int)ret.a2); ++ ++ return 0; ++} ++ ++#define VM_ID_MASK GENMASK(15, 0) ++static int ffa_id_get(u16 *vm_id) ++{ ++ ffa_value_t id; ++ ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_ID_GET, ++ }, &id); ++ ++ if (id.a0 == FFA_ERROR) ++ return ffa_to_linux_errno((int)id.a2); ++ ++ *vm_id = FIELD_GET(VM_ID_MASK, (id.a2)); ++ ++ return 0; ++} ++ ++static int __init ffa_init(void) ++{ ++ int ret; ++ ++ ret = ffa_transport_init(&invoke_ffa_fn); ++ if (ret) ++ return ret; ++ ++ ret = arm_ffa_bus_init(); ++ if (ret) ++ return ret; ++ ++ drv_info = kzalloc(sizeof(*drv_info), GFP_KERNEL); ++ if (!drv_info) { ++ ret = -ENOMEM; ++ goto ffa_bus_exit; ++ } ++ ++ ret = ffa_version_check(&drv_info->version); ++ if (ret) ++ goto free_drv_info; ++ ++ if (ffa_id_get(&drv_info->vm_id)) { ++ pr_err("failed to obtain VM id for self\n"); ++ ret = -ENODEV; ++ goto free_drv_info; ++ } ++ ++ drv_info->rx_buffer = alloc_pages_exact(RXTX_BUFFER_SIZE, GFP_KERNEL); ++ if (!drv_info->rx_buffer) { ++ ret = -ENOMEM; ++ goto free_pages; ++ } ++ ++ drv_info->tx_buffer = alloc_pages_exact(RXTX_BUFFER_SIZE, GFP_KERNEL); ++ if (!drv_info->tx_buffer) { ++ ret = -ENOMEM; ++ goto free_pages; ++ } ++ ++ ret = ffa_rxtx_map(virt_to_phys(drv_info->tx_buffer), ++ virt_to_phys(drv_info->rx_buffer), ++ RXTX_BUFFER_SIZE / FFA_PAGE_SIZE); ++ if (ret) { ++ pr_err("failed to register FFA RxTx buffers\n"); ++ goto free_pages; ++ } ++ ++ mutex_init(&drv_info->rx_lock); ++ mutex_init(&drv_info->tx_lock); ++ ++ return 0; ++free_pages: ++ if (drv_info->tx_buffer) ++ free_pages_exact(drv_info->tx_buffer, RXTX_BUFFER_SIZE); ++ free_pages_exact(drv_info->rx_buffer, RXTX_BUFFER_SIZE); ++free_drv_info: ++ kfree(drv_info); ++ffa_bus_exit: ++ arm_ffa_bus_exit(); ++ return ret; ++} ++subsys_initcall(ffa_init); ++ ++static void __exit ffa_exit(void) ++{ ++ ffa_rxtx_unmap(drv_info->vm_id); ++ free_pages_exact(drv_info->tx_buffer, RXTX_BUFFER_SIZE); ++ free_pages_exact(drv_info->rx_buffer, RXTX_BUFFER_SIZE); ++ kfree(drv_info); ++ arm_ffa_bus_exit(); ++} ++module_exit(ffa_exit); ++ ++MODULE_ALIAS("arm-ffa"); ++MODULE_AUTHOR("Sudeep Holla "); ++MODULE_DESCRIPTION("Arm FF-A interface driver"); ++MODULE_LICENSE("GPL v2"); +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0015-firmware-arm_ffa-Add-support-for-SMCCC-as-transport-to-ffa-driver.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0015-firmware-arm_ffa-Add-support-for-SMCCC-as-transport-to-ffa-driver.patch new file mode 100644 index 0000000..0d0298c --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0015-firmware-arm_ffa-Add-support-for-SMCCC-as-transport-to-ffa-driver.patch @@ -0,0 +1,119 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From 714be77e976a4b013b935b3223b2ef68856084d0 Mon Sep 17 00:00:00 2001 +From: Sudeep Holla +Date: Fri, 21 May 2021 16:10:31 +0100 +Subject: [PATCH] firmware: arm_ffa: Add support for SMCCC as transport to FFA + driver + +There are requests to keep the transport separate in order to allow +other possible transports like virtio. So let us keep the SMCCC transport +specific routines abstracted. + +It is kept simple for now. Once we add another transport, we can develop +better abstraction. + +Link: https://lore.kernel.org/r/20210521151033.181846-4-sudeep.holla@arm.com +Tested-by: Jens Wiklander +Reviewed-by: Jens Wiklander +Signed-off-by: Sudeep Holla +--- + drivers/firmware/arm_ffa/Kconfig | 5 ++++ + drivers/firmware/arm_ffa/Makefile | 3 ++- + drivers/firmware/arm_ffa/common.h | 4 ++++ + drivers/firmware/arm_ffa/smccc.c | 39 +++++++++++++++++++++++++++++++ + 4 files changed, 50 insertions(+), 1 deletion(-) + create mode 100644 drivers/firmware/arm_ffa/smccc.c + +diff --git a/drivers/firmware/arm_ffa/Kconfig b/drivers/firmware/arm_ffa/Kconfig +index 261a3660650a..5e3ae5cf82e8 100644 +--- a/drivers/firmware/arm_ffa/Kconfig ++++ b/drivers/firmware/arm_ffa/Kconfig +@@ -14,3 +14,8 @@ config ARM_FFA_TRANSPORT + + This driver provides interface for all the client drivers making + use of the features offered by ARM FF-A. ++ ++config ARM_FFA_SMCCC ++ bool ++ default ARM_FFA_TRANSPORT ++ depends on ARM64 && HAVE_ARM_SMCCC_DISCOVERY +diff --git a/drivers/firmware/arm_ffa/Makefile b/drivers/firmware/arm_ffa/Makefile +index 82d0d35c5324..9d9f37523200 100644 +--- a/drivers/firmware/arm_ffa/Makefile ++++ b/drivers/firmware/arm_ffa/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0-only + ffa-bus-y = bus.o + ffa-driver-y = driver.o +-ffa-module-objs := $(ffa-bus-y) $(ffa-driver-y) ++ffa-transport-$(CONFIG_ARM_FFA_SMCCC) += smccc.o ++ffa-module-objs := $(ffa-bus-y) $(ffa-driver-y) $(ffa-transport-y) + obj-$(CONFIG_ARM_FFA_TRANSPORT) = ffa-module.o +diff --git a/drivers/firmware/arm_ffa/common.h b/drivers/firmware/arm_ffa/common.h +index 2d3a32f67d5d..f24754a59f47 100644 +--- a/drivers/firmware/arm_ffa/common.h ++++ b/drivers/firmware/arm_ffa/common.h +@@ -16,9 +16,13 @@ typedef void (ffa_fn)(ffa_value_t, ffa_value_t *); + int arm_ffa_bus_init(void); + void arm_ffa_bus_exit(void); + ++#ifdef CONFIG_ARM_FFA_SMCCC ++int __init ffa_transport_init(ffa_fn **invoke_ffa_fn); ++#else + static inline int __init ffa_transport_init(ffa_fn **invoke_ffa_fn) + { + return -EOPNOTSUPP; + } ++#endif + + #endif /* _FFA_COMMON_H */ +diff --git a/drivers/firmware/arm_ffa/smccc.c b/drivers/firmware/arm_ffa/smccc.c +new file mode 100644 +index 000000000000..4d85bfff0a4e +--- /dev/null ++++ b/drivers/firmware/arm_ffa/smccc.c +@@ -0,0 +1,39 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2021 ARM Ltd. ++ */ ++ ++#include ++ ++#include "common.h" ++ ++static void __arm_ffa_fn_smc(ffa_value_t args, ffa_value_t *res) ++{ ++ arm_smccc_1_2_smc(&args, res); ++} ++ ++static void __arm_ffa_fn_hvc(ffa_value_t args, ffa_value_t *res) ++{ ++ arm_smccc_1_2_hvc(&args, res); ++} ++ ++int __init ffa_transport_init(ffa_fn **invoke_ffa_fn) ++{ ++ enum arm_smccc_conduit conduit; ++ ++ if (arm_smccc_get_version() < ARM_SMCCC_VERSION_1_2) ++ return -EOPNOTSUPP; ++ ++ conduit = arm_smccc_1_1_get_conduit(); ++ if (conduit == SMCCC_CONDUIT_NONE) { ++ pr_err("%s: invalid SMCCC conduit\n", __func__); ++ return -EOPNOTSUPP; ++ } ++ ++ if (conduit == SMCCC_CONDUIT_SMC) ++ *invoke_ffa_fn = __arm_ffa_fn_smc; ++ else ++ *invoke_ffa_fn = __arm_ffa_fn_hvc; ++ ++ return 0; ++} +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0016-firmware-arm_ffa-Setup-in-kernel-users-of-FFA-partitions.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0016-firmware-arm_ffa-Setup-in-kernel-users-of-FFA-partitions.patch new file mode 100644 index 0000000..975c62e --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0016-firmware-arm_ffa-Setup-in-kernel-users-of-FFA-partitions.patch @@ -0,0 +1,410 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From d0c0bce831223b08e5bade2cefc93c3ddb790796 Mon Sep 17 00:00:00 2001 +From: Sudeep Holla +Date: Fri, 21 May 2021 16:10:32 +0100 +Subject: [PATCH] firmware: arm_ffa: Setup in-kernel users of FFA partitions + +Parse the FFA nodes from the device-tree and register all the partitions +whose services will be used in the kernel. + +In order to also enable in-kernel users of FFA interface, let us add +simple set of operations for such devices. + +The in-kernel users are registered without the character device interface. + +Link: https://lore.kernel.org/r/20210521151033.181846-5-sudeep.holla@arm.com +Tested-by: Jens Wiklander +Reviewed-by: Jens Wiklander +Signed-off-by: Sudeep Holla +--- + drivers/firmware/arm_ffa/bus.c | 9 ++ + drivers/firmware/arm_ffa/common.h | 3 + + drivers/firmware/arm_ffa/driver.c | 221 ++++++++++++++++++++++++++++++ + include/linux/arm_ffa.h | 39 +++++- + 4 files changed, 271 insertions(+), 1 deletion(-) + +diff --git a/drivers/firmware/arm_ffa/bus.c b/drivers/firmware/arm_ffa/bus.c +index ae1eada5dc0c..83166e02b191 100644 +--- a/drivers/firmware/arm_ffa/bus.c ++++ b/drivers/firmware/arm_ffa/bus.c +@@ -24,6 +24,15 @@ static int ffa_device_match(struct device *dev, struct device_driver *drv) + ffa_dev = to_ffa_dev(dev); + + while (!uuid_is_null(&id_table->uuid)) { ++ /* ++ * FF-A v1.0 doesn't provide discovery of UUIDs, just the ++ * partition IDs, so fetch the partitions IDs for this ++ * id_table UUID and assign the UUID to the device if the ++ * partition ID matches ++ */ ++ if (uuid_is_null(&ffa_dev->uuid)) ++ ffa_device_match_uuid(ffa_dev, &id_table->uuid); ++ + if (uuid_equal(&ffa_dev->uuid, &id_table->uuid)) + return 1; + id_table++; +diff --git a/drivers/firmware/arm_ffa/common.h b/drivers/firmware/arm_ffa/common.h +index f24754a59f47..d6eccf1fd3f6 100644 +--- a/drivers/firmware/arm_ffa/common.h ++++ b/drivers/firmware/arm_ffa/common.h +@@ -6,6 +6,7 @@ + #ifndef _FFA_COMMON_H + #define _FFA_COMMON_H + ++#include + #include + #include + +@@ -15,6 +16,8 @@ typedef void (ffa_fn)(ffa_value_t, ffa_value_t *); + + int arm_ffa_bus_init(void); + void arm_ffa_bus_exit(void); ++bool ffa_device_is_valid(struct ffa_device *ffa_dev); ++void ffa_device_match_uuid(struct ffa_device *ffa_dev, const uuid_t *uuid); + + #ifdef CONFIG_ARM_FFA_SMCCC + int __init ffa_transport_init(ffa_fn **invoke_ffa_fn); +diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c +index 4846f079dca0..85b9bbdbeabe 100644 +--- a/drivers/firmware/arm_ffa/driver.c ++++ b/drivers/firmware/arm_ffa/driver.c +@@ -24,9 +24,12 @@ + + #include + #include ++#include + #include ++#include + #include + #include ++#include + + #include "common.h" + +@@ -185,6 +188,22 @@ static int ffa_version_check(u32 *version) + return 0; + } + ++static int ffa_rx_release(void) ++{ ++ ffa_value_t ret; ++ ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_RX_RELEASE, ++ }, &ret); ++ ++ if (ret.a0 == FFA_ERROR) ++ return ffa_to_linux_errno((int)ret.a2); ++ ++ /* check for ret.a0 == FFA_RX_RELEASE ? */ ++ ++ return 0; ++} ++ + static int ffa_rxtx_map(phys_addr_t tx_buf, phys_addr_t rx_buf, u32 pg_cnt) + { + ffa_value_t ret; +@@ -214,6 +233,65 @@ static int ffa_rxtx_unmap(u16 vm_id) + return 0; + } + ++/* buffer must be sizeof(struct ffa_partition_info) * num_partitions */ ++static int ++__ffa_partition_info_get(u32 uuid0, u32 uuid1, u32 uuid2, u32 uuid3, ++ struct ffa_partition_info *buffer, int num_partitions) ++{ ++ int count; ++ ffa_value_t partition_info; ++ ++ mutex_lock(&drv_info->rx_lock); ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_PARTITION_INFO_GET, ++ .a1 = uuid0, .a2 = uuid1, .a3 = uuid2, .a4 = uuid3, ++ }, &partition_info); ++ ++ if (partition_info.a0 == FFA_ERROR) { ++ mutex_unlock(&drv_info->rx_lock); ++ return ffa_to_linux_errno((int)partition_info.a2); ++ } ++ ++ count = partition_info.a2; ++ ++ if (buffer && count <= num_partitions) ++ memcpy(buffer, drv_info->rx_buffer, sizeof(*buffer) * count); ++ ++ ffa_rx_release(); ++ ++ mutex_unlock(&drv_info->rx_lock); ++ ++ return count; ++} ++ ++/* buffer is allocated and caller must free the same if returned count > 0 */ ++static int ++ffa_partition_probe(const uuid_t *uuid, struct ffa_partition_info **buffer) ++{ ++ int count; ++ u32 uuid0_4[4]; ++ struct ffa_partition_info *pbuf; ++ ++ export_uuid((u8 *)uuid0_4, uuid); ++ count = __ffa_partition_info_get(uuid0_4[0], uuid0_4[1], uuid0_4[2], ++ uuid0_4[3], NULL, 0); ++ if (count <= 0) ++ return count; ++ ++ pbuf = kcalloc(count, sizeof(*pbuf), GFP_KERNEL); ++ if (!pbuf) ++ return -ENOMEM; ++ ++ count = __ffa_partition_info_get(uuid0_4[0], uuid0_4[1], uuid0_4[2], ++ uuid0_4[3], pbuf, count); ++ if (count <= 0) ++ kfree(pbuf); ++ else ++ *buffer = pbuf; ++ ++ return count; ++} ++ + #define VM_ID_MASK GENMASK(15, 0) + static int ffa_id_get(u16 *vm_id) + { +@@ -231,6 +309,147 @@ static int ffa_id_get(u16 *vm_id) + return 0; + } + ++static int ffa_msg_send_direct_req(u16 src_id, u16 dst_id, bool mode_32bit, ++ struct ffa_send_direct_data *data) ++{ ++ u32 req_id, resp_id, src_dst_ids = PACK_TARGET_INFO(src_id, dst_id); ++ ffa_value_t ret; ++ ++ if (mode_32bit) { ++ req_id = FFA_MSG_SEND_DIRECT_REQ; ++ resp_id = FFA_MSG_SEND_DIRECT_RESP; ++ } else { ++ req_id = FFA_FN_NATIVE(MSG_SEND_DIRECT_REQ); ++ resp_id = FFA_FN_NATIVE(MSG_SEND_DIRECT_RESP); ++ } ++ ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = req_id, .a1 = src_dst_ids, .a2 = 0, ++ .a3 = data->data0, .a4 = data->data1, .a5 = data->data2, ++ .a6 = data->data3, .a7 = data->data4, ++ }, &ret); ++ ++ while (ret.a0 == FFA_INTERRUPT) ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_RUN, .a1 = ret.a1, ++ }, &ret); ++ ++ if (ret.a0 == FFA_ERROR) ++ return ffa_to_linux_errno((int)ret.a2); ++ ++ if (ret.a0 == resp_id) { ++ data->data0 = ret.a3; ++ data->data1 = ret.a4; ++ data->data2 = ret.a5; ++ data->data3 = ret.a6; ++ data->data4 = ret.a7; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static u32 ffa_api_version_get(void) ++{ ++ return drv_info->version; ++} ++ ++static int ffa_partition_info_get(const char *uuid_str, ++ struct ffa_partition_info *buffer) ++{ ++ int count; ++ uuid_t uuid; ++ struct ffa_partition_info *pbuf; ++ ++ if (uuid_parse(uuid_str, &uuid)) { ++ pr_err("invalid uuid (%s)\n", uuid_str); ++ return -ENODEV; ++ } ++ ++ count = ffa_partition_probe(&uuid_null, &pbuf); ++ if (count <= 0) ++ return -ENOENT; ++ ++ memcpy(buffer, pbuf, sizeof(*pbuf) * count); ++ kfree(pbuf); ++ return 0; ++} ++ ++static void ffa_mode_32bit_set(struct ffa_device *dev) ++{ ++ dev->mode_32bit = true; ++} ++ ++static int ffa_sync_send_receive(struct ffa_device *dev, ++ struct ffa_send_direct_data *data) ++{ ++ return ffa_msg_send_direct_req(drv_info->vm_id, dev->vm_id, ++ dev->mode_32bit, data); ++} ++ ++static const struct ffa_dev_ops ffa_ops = { ++ .api_version_get = ffa_api_version_get, ++ .partition_info_get = ffa_partition_info_get, ++ .mode_32bit_set = ffa_mode_32bit_set, ++ .sync_send_receive = ffa_sync_send_receive, ++}; ++ ++const struct ffa_dev_ops *ffa_dev_ops_get(struct ffa_device *dev) ++{ ++ if (ffa_device_is_valid(dev)) ++ return &ffa_ops; ++ ++ return NULL; ++} ++EXPORT_SYMBOL_GPL(ffa_dev_ops_get); ++ ++void ffa_device_match_uuid(struct ffa_device *ffa_dev, const uuid_t *uuid) ++{ ++ int count, idx; ++ struct ffa_partition_info *pbuf, *tpbuf; ++ ++ count = ffa_partition_probe(uuid, &pbuf); ++ if (count <= 0) ++ return; ++ ++ for (idx = 0, tpbuf = pbuf; idx < count; idx++, tpbuf++) ++ if (tpbuf->id == ffa_dev->vm_id) ++ uuid_copy(&ffa_dev->uuid, uuid); ++ kfree(pbuf); ++} ++ ++static void ffa_setup_partitions(void) ++{ ++ int count, idx; ++ struct ffa_device *ffa_dev; ++ struct ffa_partition_info *pbuf, *tpbuf; ++ ++ count = ffa_partition_probe(&uuid_null, &pbuf); ++ if (count <= 0) { ++ pr_info("%s: No partitions found, error %d\n", __func__, count); ++ return; ++ } ++ ++ for (idx = 0, tpbuf = pbuf; idx < count; idx++, tpbuf++) { ++ /* Note that the &uuid_null parameter will require ++ * ffa_device_match() to find the UUID of this partition id ++ * with help of ffa_device_match_uuid(). Once the FF-A spec ++ * is updated to provide correct UUID here for each partition ++ * as part of the discovery API, we need to pass the ++ * discovered UUID here instead. ++ */ ++ ffa_dev = ffa_device_register(&uuid_null, tpbuf->id); ++ if (!ffa_dev) { ++ pr_err("%s: failed to register partition ID 0x%x\n", ++ __func__, tpbuf->id); ++ continue; ++ } ++ ++ ffa_dev_set_drvdata(ffa_dev, drv_info); ++ } ++ kfree(pbuf); ++} ++ + static int __init ffa_init(void) + { + int ret; +@@ -282,6 +501,8 @@ static int __init ffa_init(void) + mutex_init(&drv_info->rx_lock); + mutex_init(&drv_info->tx_lock); + ++ ffa_setup_partitions(); ++ + return 0; + free_pages: + if (drv_info->tx_buffer) +diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h +index 331ff62c9873..d672673fc621 100644 +--- a/include/linux/arm_ffa.h ++++ b/include/linux/arm_ffa.h +@@ -6,7 +6,6 @@ + #ifndef _LINUX_ARM_FFA_H + #define _LINUX_ARM_FFA_H + +-#include + #include + #include + #include +@@ -15,6 +14,7 @@ + /* FFA Bus/Device/Driver related */ + struct ffa_device { + int vm_id; ++ bool mode_32bit; + uuid_t uuid; + struct device dev; + }; +@@ -48,6 +48,7 @@ int ffa_driver_register(struct ffa_driver *driver, struct module *owner, + const char *mod_name); + void ffa_driver_unregister(struct ffa_driver *driver); + bool ffa_device_is_valid(struct ffa_device *ffa_dev); ++const struct ffa_dev_ops *ffa_dev_ops_get(struct ffa_device *dev); + + #else + static inline +@@ -70,6 +71,11 @@ static inline void ffa_driver_unregister(struct ffa_driver *driver) {} + static inline + bool ffa_device_is_valid(struct ffa_device *ffa_dev) { return false; } + ++static inline ++const struct ffa_dev_ops *ffa_dev_ops_get(struct ffa_device *dev) ++{ ++ return NULL; ++} + #endif /* CONFIG_ARM_FFA_TRANSPORT */ + + #define ffa_register(driver) \ +@@ -88,4 +94,35 @@ bool ffa_device_is_valid(struct ffa_device *ffa_dev) { return false; } + #define module_ffa_driver(__ffa_driver) \ + module_driver(__ffa_driver, ffa_register, ffa_unregister) + ++/* FFA transport related */ ++struct ffa_partition_info { ++ u16 id; ++ u16 exec_ctxt; ++/* partition supports receipt of direct requests */ ++#define FFA_PARTITION_DIRECT_RECV BIT(0) ++/* partition can send direct requests. */ ++#define FFA_PARTITION_DIRECT_SEND BIT(1) ++/* partition can send and receive indirect messages. */ ++#define FFA_PARTITION_INDIRECT_MSG BIT(2) ++ u32 properties; ++}; ++ ++/* For use with FFA_MSG_SEND_DIRECT_{REQ,RESP} which pass data via registers */ ++struct ffa_send_direct_data { ++ unsigned long data0; /* w3/x3 */ ++ unsigned long data1; /* w4/x4 */ ++ unsigned long data2; /* w5/x5 */ ++ unsigned long data3; /* w6/x6 */ ++ unsigned long data4; /* w7/x7 */ ++}; ++ ++struct ffa_dev_ops { ++ u32 (*api_version_get)(void); ++ int (*partition_info_get)(const char *uuid_str, ++ struct ffa_partition_info *buffer); ++ void (*mode_32bit_set)(struct ffa_device *dev); ++ int (*sync_send_receive)(struct ffa_device *dev, ++ struct ffa_send_direct_data *data); ++}; ++ + #endif /* _LINUX_ARM_FFA_H */ +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0017-firmware-arm_ffa-Add-support-for-MEM_-interfaces.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0017-firmware-arm_ffa-Add-support-for-MEM_-interfaces.patch new file mode 100644 index 0000000..d1a3e93 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0017-firmware-arm_ffa-Add-support-for-MEM_-interfaces.patch @@ -0,0 +1,409 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From cc2195fe536c28e192df5d07e6dd277af36814b4 Mon Sep 17 00:00:00 2001 +From: Sudeep Holla +Date: Fri, 21 May 2021 16:10:33 +0100 +Subject: [PATCH] firmware: arm_ffa: Add support for MEM_* interfaces + +Most of the MEM_* APIs share the same parameters, so they can be +generalised. Currently only MEM_SHARE is implemented and the user space +interface for that is not added yet. + +Link: https://lore.kernel.org/r/20210521151033.181846-6-sudeep.holla@arm.com +Tested-by: Jens Wiklander +Signed-off-by: Sudeep Holla +--- + drivers/firmware/arm_ffa/driver.c | 199 ++++++++++++++++++++++++++++++ + include/linux/arm_ffa.h | 139 +++++++++++++++++++++ + 2 files changed, 338 insertions(+) + +diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c +index 85b9bbdbeabe..b1edb4b2e94a 100644 +--- a/drivers/firmware/arm_ffa/driver.c ++++ b/drivers/firmware/arm_ffa/driver.c +@@ -28,6 +28,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + +@@ -349,6 +351,192 @@ static int ffa_msg_send_direct_req(u16 src_id, u16 dst_id, bool mode_32bit, + return -EINVAL; + } + ++static int ffa_mem_first_frag(u32 func_id, phys_addr_t buf, u32 buf_sz, ++ u32 frag_len, u32 len, u64 *handle) ++{ ++ ffa_value_t ret; ++ ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = func_id, .a1 = len, .a2 = frag_len, ++ .a3 = buf, .a4 = buf_sz, ++ }, &ret); ++ ++ while (ret.a0 == FFA_MEM_OP_PAUSE) ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_MEM_OP_RESUME, ++ .a1 = ret.a1, .a2 = ret.a2, ++ }, &ret); ++ ++ if (ret.a0 == FFA_ERROR) ++ return ffa_to_linux_errno((int)ret.a2); ++ ++ if (ret.a0 != FFA_SUCCESS) ++ return -EOPNOTSUPP; ++ ++ if (handle) ++ *handle = PACK_HANDLE(ret.a2, ret.a3); ++ ++ return frag_len; ++} ++ ++static int ffa_mem_next_frag(u64 handle, u32 frag_len) ++{ ++ ffa_value_t ret; ++ ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_MEM_FRAG_TX, ++ .a1 = HANDLE_LOW(handle), .a2 = HANDLE_HIGH(handle), ++ .a3 = frag_len, ++ }, &ret); ++ ++ while (ret.a0 == FFA_MEM_OP_PAUSE) ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_MEM_OP_RESUME, ++ .a1 = ret.a1, .a2 = ret.a2, ++ }, &ret); ++ ++ if (ret.a0 == FFA_ERROR) ++ return ffa_to_linux_errno((int)ret.a2); ++ ++ if (ret.a0 != FFA_MEM_FRAG_RX) ++ return -EOPNOTSUPP; ++ ++ return ret.a3; ++} ++ ++static int ++ffa_transmit_fragment(u32 func_id, phys_addr_t buf, u32 buf_sz, u32 frag_len, ++ u32 len, u64 *handle, bool first) ++{ ++ if (!first) ++ return ffa_mem_next_frag(*handle, frag_len); ++ ++ return ffa_mem_first_frag(func_id, buf, buf_sz, frag_len, len, handle); ++} ++ ++static u32 ffa_get_num_pages_sg(struct scatterlist *sg) ++{ ++ u32 num_pages = 0; ++ ++ do { ++ num_pages += sg->length / FFA_PAGE_SIZE; ++ } while ((sg = sg_next(sg))); ++ ++ return num_pages; ++} ++ ++static int ++ffa_setup_and_transmit(u32 func_id, void *buffer, u32 max_fragsize, ++ struct ffa_mem_ops_args *args) ++{ ++ int rc = 0; ++ bool first = true; ++ phys_addr_t addr = 0; ++ struct ffa_composite_mem_region *composite; ++ struct ffa_mem_region_addr_range *constituents; ++ struct ffa_mem_region_attributes *ep_mem_access; ++ struct ffa_mem_region *mem_region = buffer; ++ u32 idx, frag_len, length, buf_sz = 0, num_entries = sg_nents(args->sg); ++ ++ mem_region->tag = args->tag; ++ mem_region->flags = args->flags; ++ mem_region->sender_id = drv_info->vm_id; ++ mem_region->attributes = FFA_MEM_NORMAL | FFA_MEM_WRITE_BACK | ++ FFA_MEM_INNER_SHAREABLE; ++ ep_mem_access = &mem_region->ep_mem_access[0]; ++ ++ for (idx = 0; idx < args->nattrs; idx++, ep_mem_access++) { ++ ep_mem_access->receiver = args->attrs[idx].receiver; ++ ep_mem_access->attrs = args->attrs[idx].attrs; ++ ep_mem_access->composite_off = COMPOSITE_OFFSET(args->nattrs); ++ } ++ mem_region->ep_count = args->nattrs; ++ ++ composite = buffer + COMPOSITE_OFFSET(args->nattrs); ++ composite->total_pg_cnt = ffa_get_num_pages_sg(args->sg); ++ composite->addr_range_cnt = num_entries; ++ ++ length = COMPOSITE_CONSTITUENTS_OFFSET(args->nattrs, num_entries); ++ frag_len = COMPOSITE_CONSTITUENTS_OFFSET(args->nattrs, 0); ++ if (frag_len > max_fragsize) ++ return -ENXIO; ++ ++ if (!args->use_txbuf) { ++ addr = virt_to_phys(buffer); ++ buf_sz = max_fragsize / FFA_PAGE_SIZE; ++ } ++ ++ constituents = buffer + frag_len; ++ idx = 0; ++ do { ++ if (frag_len == max_fragsize) { ++ rc = ffa_transmit_fragment(func_id, addr, buf_sz, ++ frag_len, length, ++ &args->g_handle, first); ++ if (rc < 0) ++ return -ENXIO; ++ ++ first = false; ++ idx = 0; ++ frag_len = 0; ++ constituents = buffer; ++ } ++ ++ if ((void *)constituents - buffer > max_fragsize) { ++ pr_err("Memory Region Fragment > Tx Buffer size\n"); ++ return -EFAULT; ++ } ++ ++ constituents->address = sg_phys(args->sg); ++ constituents->pg_cnt = args->sg->length / FFA_PAGE_SIZE; ++ constituents++; ++ frag_len += sizeof(struct ffa_mem_region_addr_range); ++ } while ((args->sg = sg_next(args->sg))); ++ ++ return ffa_transmit_fragment(func_id, addr, buf_sz, frag_len, ++ length, &args->g_handle, first); ++} ++ ++static int ffa_memory_ops(u32 func_id, struct ffa_mem_ops_args *args) ++{ ++ int ret; ++ void *buffer; ++ ++ if (!args->use_txbuf) { ++ buffer = alloc_pages_exact(RXTX_BUFFER_SIZE, GFP_KERNEL); ++ if (!buffer) ++ return -ENOMEM; ++ } else { ++ buffer = drv_info->tx_buffer; ++ mutex_lock(&drv_info->tx_lock); ++ } ++ ++ ret = ffa_setup_and_transmit(func_id, buffer, RXTX_BUFFER_SIZE, args); ++ ++ if (args->use_txbuf) ++ mutex_unlock(&drv_info->tx_lock); ++ else ++ free_pages_exact(buffer, RXTX_BUFFER_SIZE); ++ ++ return ret < 0 ? ret : 0; ++} ++ ++static int ffa_memory_reclaim(u64 g_handle, u32 flags) ++{ ++ ffa_value_t ret; ++ ++ invoke_ffa_fn((ffa_value_t){ ++ .a0 = FFA_MEM_RECLAIM, ++ .a1 = HANDLE_LOW(g_handle), .a2 = HANDLE_HIGH(g_handle), ++ .a3 = flags, ++ }, &ret); ++ ++ if (ret.a0 == FFA_ERROR) ++ return ffa_to_linux_errno((int)ret.a2); ++ ++ return 0; ++} ++ + static u32 ffa_api_version_get(void) + { + return drv_info->version; +@@ -387,11 +575,22 @@ static int ffa_sync_send_receive(struct ffa_device *dev, + dev->mode_32bit, data); + } + ++static int ++ffa_memory_share(struct ffa_device *dev, struct ffa_mem_ops_args *args) ++{ ++ if (dev->mode_32bit) ++ return ffa_memory_ops(FFA_MEM_SHARE, args); ++ ++ return ffa_memory_ops(FFA_FN_NATIVE(MEM_SHARE), args); ++} ++ + static const struct ffa_dev_ops ffa_ops = { + .api_version_get = ffa_api_version_get, + .partition_info_get = ffa_partition_info_get, + .mode_32bit_set = ffa_mode_32bit_set, + .sync_send_receive = ffa_sync_send_receive, ++ .memory_reclaim = ffa_memory_reclaim, ++ .memory_share = ffa_memory_share, + }; + + const struct ffa_dev_ops *ffa_dev_ops_get(struct ffa_device *dev) +diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h +index d672673fc621..505c679b6a9b 100644 +--- a/include/linux/arm_ffa.h ++++ b/include/linux/arm_ffa.h +@@ -116,6 +116,142 @@ struct ffa_send_direct_data { + unsigned long data4; /* w7/x7 */ + }; + ++struct ffa_mem_region_addr_range { ++ /* The base IPA of the constituent memory region, aligned to 4 kiB */ ++ u64 address; ++ /* The number of 4 kiB pages in the constituent memory region. */ ++ u32 pg_cnt; ++ u32 reserved; ++}; ++ ++struct ffa_composite_mem_region { ++ /* ++ * The total number of 4 kiB pages included in this memory region. This ++ * must be equal to the sum of page counts specified in each ++ * `struct ffa_mem_region_addr_range`. ++ */ ++ u32 total_pg_cnt; ++ /* The number of constituents included in this memory region range */ ++ u32 addr_range_cnt; ++ u64 reserved; ++ /** An array of `addr_range_cnt` memory region constituents. */ ++ struct ffa_mem_region_addr_range constituents[]; ++}; ++ ++struct ffa_mem_region_attributes { ++ /* The ID of the VM to which the memory is being given or shared. */ ++ u16 receiver; ++ /* ++ * The permissions with which the memory region should be mapped in the ++ * receiver's page table. ++ */ ++#define FFA_MEM_EXEC BIT(3) ++#define FFA_MEM_NO_EXEC BIT(2) ++#define FFA_MEM_RW BIT(1) ++#define FFA_MEM_RO BIT(0) ++ u8 attrs; ++ /* ++ * Flags used during FFA_MEM_RETRIEVE_REQ and FFA_MEM_RETRIEVE_RESP ++ * for memory regions with multiple borrowers. ++ */ ++#define FFA_MEM_RETRIEVE_SELF_BORROWER BIT(0) ++ u8 flag; ++ u32 composite_off; ++ /* ++ * Offset in bytes from the start of the outer `ffa_memory_region` to ++ * an `struct ffa_mem_region_addr_range`. ++ */ ++ u64 reserved; ++}; ++ ++struct ffa_mem_region { ++ /* The ID of the VM/owner which originally sent the memory region */ ++ u16 sender_id; ++#define FFA_MEM_NORMAL BIT(5) ++#define FFA_MEM_DEVICE BIT(4) ++ ++#define FFA_MEM_WRITE_BACK (3 << 2) ++#define FFA_MEM_NON_CACHEABLE (1 << 2) ++ ++#define FFA_DEV_nGnRnE (0 << 2) ++#define FFA_DEV_nGnRE (1 << 2) ++#define FFA_DEV_nGRE (2 << 2) ++#define FFA_DEV_GRE (3 << 2) ++ ++#define FFA_MEM_NON_SHAREABLE (0) ++#define FFA_MEM_OUTER_SHAREABLE (2) ++#define FFA_MEM_INNER_SHAREABLE (3) ++ u8 attributes; ++ u8 reserved_0; ++/* ++ * Clear memory region contents after unmapping it from the sender and ++ * before mapping it for any receiver. ++ */ ++#define FFA_MEM_CLEAR BIT(0) ++/* ++ * Whether the hypervisor may time slice the memory sharing or retrieval ++ * operation. ++ */ ++#define FFA_TIME_SLICE_ENABLE BIT(1) ++ ++#define FFA_MEM_RETRIEVE_TYPE_IN_RESP (0 << 3) ++#define FFA_MEM_RETRIEVE_TYPE_SHARE (1 << 3) ++#define FFA_MEM_RETRIEVE_TYPE_LEND (2 << 3) ++#define FFA_MEM_RETRIEVE_TYPE_DONATE (3 << 3) ++ ++#define FFA_MEM_RETRIEVE_ADDR_ALIGN_HINT BIT(9) ++#define FFA_MEM_RETRIEVE_ADDR_ALIGN(x) ((x) << 5) ++ /* Flags to control behaviour of the transaction. */ ++ u32 flags; ++#define HANDLE_LOW_MASK GENMASK_ULL(31, 0) ++#define HANDLE_HIGH_MASK GENMASK_ULL(63, 32) ++#define HANDLE_LOW(x) ((u32)(FIELD_GET(HANDLE_LOW_MASK, (x)))) ++#define HANDLE_HIGH(x) ((u32)(FIELD_GET(HANDLE_HIGH_MASK, (x)))) ++ ++#define PACK_HANDLE(l, h) \ ++ (FIELD_PREP(HANDLE_LOW_MASK, (l)) | FIELD_PREP(HANDLE_HIGH_MASK, (h))) ++ /* ++ * A globally-unique ID assigned by the hypervisor for a region ++ * of memory being sent between VMs. ++ */ ++ u64 handle; ++ /* ++ * An implementation defined value associated with the receiver and the ++ * memory region. ++ */ ++ u64 tag; ++ u32 reserved_1; ++ /* ++ * The number of `ffa_mem_region_attributes` entries included in this ++ * transaction. ++ */ ++ u32 ep_count; ++ /* ++ * An array of endpoint memory access descriptors. ++ * Each one specifies a memory region offset, an endpoint and the ++ * attributes with which this memory region should be mapped in that ++ * endpoint's page table. ++ */ ++ struct ffa_mem_region_attributes ep_mem_access[]; ++}; ++ ++#define COMPOSITE_OFFSET(x) \ ++ (offsetof(struct ffa_mem_region, ep_mem_access[x])) ++#define CONSTITUENTS_OFFSET(x) \ ++ (offsetof(struct ffa_composite_mem_region, constituents[x])) ++#define COMPOSITE_CONSTITUENTS_OFFSET(x, y) \ ++ (COMPOSITE_OFFSET(x) + CONSTITUENTS_OFFSET(y)) ++ ++struct ffa_mem_ops_args { ++ bool use_txbuf; ++ u32 nattrs; ++ u32 flags; ++ u64 tag; ++ u64 g_handle; ++ struct scatterlist *sg; ++ struct ffa_mem_region_attributes *attrs; ++}; ++ + struct ffa_dev_ops { + u32 (*api_version_get)(void); + int (*partition_info_get)(const char *uuid_str, +@@ -123,6 +259,9 @@ struct ffa_dev_ops { + void (*mode_32bit_set)(struct ffa_device *dev); + int (*sync_send_receive)(struct ffa_device *dev, + struct ffa_send_direct_data *data); ++ int (*memory_reclaim)(u64 g_handle, u32 flags); ++ int (*memory_share)(struct ffa_device *dev, ++ struct ffa_mem_ops_args *args); + }; + + #endif /* _LINUX_ARM_FFA_H */ +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0018-firmware-arm_ffa-Ensure-drivers-provide-a-probe-function.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0018-firmware-arm_ffa-Ensure-drivers-provide-a-probe-function.patch new file mode 100644 index 0000000..3ecd28a --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0018-firmware-arm_ffa-Ensure-drivers-provide-a-probe-function.patch @@ -0,0 +1,40 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From 92743071464fca5acbbe812d9a0d88de3eaaad36 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= +Date: Mon, 21 Jun 2021 22:16:51 +0200 +Subject: [PATCH] firmware: arm_ffa: Ensure drivers provide a probe function +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The bus probe callback calls the driver callback without further +checking. Better be safe than sorry and refuse registration of a driver +without a probe function to prevent a NULL pointer exception. + +Link: https://lore.kernel.org/r/20210621201652.127611-1-u.kleine-koenig@pengutronix.de +Fixes: e781858488b9 ("firmware: arm_ffa: Add initial FFA bus support for device enumeration") +Signed-off-by: Uwe Kleine-König +Signed-off-by: Sudeep Holla +--- + drivers/firmware/arm_ffa/bus.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/firmware/arm_ffa/bus.c b/drivers/firmware/arm_ffa/bus.c +index 83166e02b191..d2cc24319626 100644 +--- a/drivers/firmware/arm_ffa/bus.c ++++ b/drivers/firmware/arm_ffa/bus.c +@@ -99,6 +99,9 @@ int ffa_driver_register(struct ffa_driver *driver, struct module *owner, + { + int ret; + ++ if (!driver->probe) ++ return -EINVAL; ++ + driver->driver.bus = &ffa_bus_type; + driver->driver.name = driver->name; + driver->driver.owner = owner; +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0019-firmware-arm_ffa-Simplify-probe-function.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0019-firmware-arm_ffa-Simplify-probe-function.patch new file mode 100644 index 0000000..13035d8 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0019-firmware-arm_ffa-Simplify-probe-function.patch @@ -0,0 +1,38 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From e362547addc39e4bb18ad5bdfd59ce4d512d0c08 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= +Date: Mon, 21 Jun 2021 22:16:52 +0200 +Subject: [PATCH] firmware: arm_ffa: Simplify probe function +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +When the driver core calls the probe callback it already checked that +the devices match, so there is no need to call the match callback again. + +Link: https://lore.kernel.org/r/20210621201652.127611-2-u.kleine-koenig@pengutronix.de +Signed-off-by: Uwe Kleine-König +Signed-off-by: Sudeep Holla +--- + drivers/firmware/arm_ffa/bus.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/firmware/arm_ffa/bus.c b/drivers/firmware/arm_ffa/bus.c +index d2cc24319626..00fe595a5bc8 100644 +--- a/drivers/firmware/arm_ffa/bus.c ++++ b/drivers/firmware/arm_ffa/bus.c +@@ -46,9 +46,6 @@ static int ffa_device_probe(struct device *dev) + struct ffa_driver *ffa_drv = to_ffa_driver(dev->driver); + struct ffa_device *ffa_dev = to_ffa_dev(dev); + +- if (!ffa_device_match(dev, dev->driver)) +- return -ENODEV; +- + return ffa_drv->probe(ffa_dev); + } + +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0020-firmware-arm_ffa-Fix-the-comment-style.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0020-firmware-arm_ffa-Fix-the-comment-style.patch new file mode 100644 index 0000000..0850c1c --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0020-firmware-arm_ffa-Fix-the-comment-style.patch @@ -0,0 +1,41 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From ba684a31d3626c86cd9097e12d6ed57d224d077d Mon Sep 17 00:00:00 2001 +From: Sudeep Holla +Date: Tue, 22 Jun 2021 17:22:02 +0100 +Subject: [PATCH] firmware: arm_ffa: Fix the comment style + +clang produces the following warning: + + drivers/firmware/arm_ffa/driver.c:123: warning: expecting + prototype for FF(). Prototype was for FFA_PAGE_SIZE() instead + + This comment starts with '/**', but isn't a kernel-doc comment. + Refer Documentation/doc-guide/kernel-doc.rst + +Fix the same by removing the kernel-doc style comment here. + +Link: https://lore.kernel.org/r/20210622162202.3485866-1-sudeep.holla@arm.com +Reported-by: kernel test robot +Signed-off-by: Sudeep Holla +--- + drivers/firmware/arm_ffa/driver.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c +index b1edb4b2e94a..88b822575ac4 100644 +--- a/drivers/firmware/arm_ffa/driver.c ++++ b/drivers/firmware/arm_ffa/driver.c +@@ -120,7 +120,7 @@ + #define PACK_TARGET_INFO(s, r) \ + (FIELD_PREP(SENDER_ID_MASK, (s)) | FIELD_PREP(RECEIVER_ID_MASK, (r))) + +-/** ++/* + * FF-A specification mentions explicitly about '4K pages'. This should + * not be confused with the kernel PAGE_SIZE, which is the translation + * granule kernel is configured and may be one among 4K, 16K and 64K. +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0021-firmware-arm_ffa-Fix-a-possible-ffa_linux_errmap-buffer-overflow.patch b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0021-firmware-arm_ffa-Fix-a-possible-ffa_linux_errmap-buffer-overflow.patch new file mode 100644 index 0000000..5575952 --- /dev/null +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0021-firmware-arm_ffa-Fix-a-possible-ffa_linux_errmap-buffer-overflow.patch @@ -0,0 +1,46 @@ +Upstream-Status: Accepted [merged with kernel 5.14] +Signed-off-by: Arpita S.K + +From dd925db6f07556061c11ab1fbfa4a0145ae6b438 Mon Sep 17 00:00:00 2001 +From: Sudeep Holla +Date: Wed, 7 Jul 2021 14:47:39 +0100 +Subject: [PATCH] firmware: arm_ffa: Fix a possible ffa_linux_errmap buffer + overflow + +The ffa_linux_errmap buffer access index is supposed to range from 0-8 +but it ranges from 1-9 instead. It reads one element out of bounds. It +also changes the success into -EINVAL though ffa_to_linux_errno is never +used in case of success, it is expected to work for success case too. + +It is slightly confusing code as the negative of the error code +is used as index to the buffer. Fix it by negating it at the start and +make it more readable. + +Link: https://lore.kernel.org/r/20210707134739.1869481-1-sudeep.holla@arm.com +Reported-by: kernel test robot +Reported-by: Dan Carpenter +Signed-off-by: Sudeep Holla +--- + drivers/firmware/arm_ffa/driver.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c +index 88b822575ac4..c9fb56afbcb4 100644 +--- a/drivers/firmware/arm_ffa/driver.c ++++ b/drivers/firmware/arm_ffa/driver.c +@@ -149,8 +149,10 @@ static const int ffa_linux_errmap[] = { + + static inline int ffa_to_linux_errno(int errno) + { +- if (errno < FFA_RET_SUCCESS && errno >= -ARRAY_SIZE(ffa_linux_errmap)) +- return ffa_linux_errmap[-errno]; ++ int err_idx = -errno; ++ ++ if (err_idx >= 0 && err_idx < ARRAY_SIZE(ffa_linux_errmap)) ++ return ffa_linux_errmap[err_idx]; + return -EINVAL; + } + +-- +2.17.1 + diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig index 4642352..205a243 100644 --- a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_VEXPRESS=y CONFIG_CMDLINE="console=ttyAMA0 loglevel=9" CONFIG_EFI=y # CONFIG_SUSPEND is not set +CONFIG_ARM_FFA_TRANSPORT=y CONFIG_EFI_BOOTLOADER_CONTROL=y CONFIG_EFI_CAPSULE_LOADER=y CONFIG_EFI_TEST=y diff --git a/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc b/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc index a32c393..f4b5604 100644 --- a/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc +++ b/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc @@ -101,6 +101,18 @@ SRC_URI:append:corstone1000 = " \ file://0007-usb-isp1760-add-support-for-isp1763.patch \ file://0008-dt-bindings-usb-nxp-isp1760-add-bindings.patch \ file://0009-usb-isp1763-add-peripheral-mode.patch \ + file://0010-firmware-smccc-Add-SMCCC-TRNG-function-call-IDs.patch \ + file://0011-firmware-smccc-Introduce-SMCCC-TRNG-framework.patch \ + file://0012-arm64-smccc-Add-support-for-SMCCCv1.2-extended-input-output-registers.patch \ + file://0013-firmware-arm_ffa-Add-initial-FFA-bus-support-for-device-enumeration.patch \ + file://0014-firmware-arm_ffa-Add-initial-Arm-FFA-driver-support.patch \ + file://0015-firmware-arm_ffa-Add-support-for-SMCCC-as-transport-to-ffa-driver.patch \ + file://0016-firmware-arm_ffa-Setup-in-kernel-users-of-FFA-partitions.patch \ + file://0017-firmware-arm_ffa-Add-support-for-MEM_-interfaces.patch \ + file://0018-firmware-arm_ffa-Ensure-drivers-provide-a-probe-function.patch \ + file://0019-firmware-arm_ffa-Simplify-probe-function.patch \ + file://0020-firmware-arm_ffa-Fix-the-comment-style.patch \ + file://0021-firmware-arm_ffa-Fix-a-possible-ffa_linux_errmap-buffer-overflow.patch \ file://0022-usb-isp1760-isp1760-udc-Provide-missing-description-.patch \ file://0023-usb-isp1760-Fix-meaningless-check-in-isp1763_run.patch \ file://0024-usb-isp1760-remove-debug-message-as-error.patch \ From patchwork Tue Nov 23 15:59:24 2021 Content-Type: text/plain; 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Tue, 23 Nov 2021 08:00:12 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Abdellatif El Khlifi , Jon Mason Subject: [PATCH][honister 17/19] arm/ffa-debugfs: corstone1000: enabling FF-A Debugfs Linux driver Date: Tue, 23 Nov 2021 15:59:24 +0000 Message-Id: <20211123155926.31743-18-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:15 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2446 From: Abdellatif El Khlifi - This commit provides a recipe for the FF-A Debugfs Linux driver v2.1.0. The driver is an out-of-tree loadable modules. It exposes FF-A operations to user space and only used for development purposes. - Create a dev package for ffa-debugfs-mod ffa-debugfs-mod recipe provides arm_ffa_user.h header for other recipes that need it at build time. The header is put in ffa-debugfs-mod-dev package. Change-Id: I92f33e20b5fdfc9a32cff03ae2a137150d0328db Signed-off-by: Arpita S.K Signed-off-by: Abdellatif El Khlifi Signed-off-by: Jon Mason --- .../linux/files/corstone1000/defconfig | 1 + .../ffa-debugfs/ffa-debugfs-mod_2.1.0.bb | 29 +++++++ .../files/0001-build-add-Yocto-support.patch | 79 +++++++++++++++++++ ...-loading-the-driver-in-a-generic-way.patch | 46 +++++++++++ 4 files changed, 155 insertions(+) create mode 100644 meta-arm/recipes-kernel/ffa-debugfs/ffa-debugfs-mod_2.1.0.bb create mode 100644 meta-arm/recipes-kernel/ffa-debugfs/files/0001-build-add-Yocto-support.patch create mode 100644 meta-arm/recipes-kernel/ffa-debugfs/files/0002-script-loading-the-driver-in-a-generic-way.patch diff --git a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig index 205a243..c402ca2 100644 --- a/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig +++ b/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig @@ -16,6 +16,7 @@ CONFIG_EFI_CAPSULE_LOADER=y CONFIG_EFI_TEST=y CONFIG_RESET_ATTACK_MITIGATION=y # CONFIG_STACKPROTECTOR is not set +CONFIG_MODULES=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_NET=y diff --git a/meta-arm/recipes-kernel/ffa-debugfs/ffa-debugfs-mod_2.1.0.bb b/meta-arm/recipes-kernel/ffa-debugfs/ffa-debugfs-mod_2.1.0.bb new file mode 100644 index 0000000..e9c3611 --- /dev/null +++ b/meta-arm/recipes-kernel/ffa-debugfs/ffa-debugfs-mod_2.1.0.bb @@ -0,0 +1,29 @@ +SUMMARY = "FF-A Debugfs Linux kernel module" +DESCRIPTION = "This out-of-tree kernel module exposes FF-A operations to user space \ +used for development purposes" +LICENSE = "GPLv2" +LIC_FILES_CHKSUM = "file://arm_ffa_user.c;beginline=1;endline=1;md5=fcab174c20ea2e2bc0be64b493708266" + +SRC_URI = "git://git.gitlab.arm.com/linux-arm/linux-trusted-services.git;branch=main;protocol=https" + +# ffa-debugfs v2.1.0 +SRCREV = "77967912d033144aff2695cecbd52d3be450deaa" + +S = "${WORKDIR}/git" + +inherit module + +SRC_URI:append = " \ + file://0001-build-add-Yocto-support.patch \ + file://0002-script-loading-the-driver-in-a-generic-way.patch \ + " + +FILES:${PN} += "${bindir}/load_ffa_debugfs.sh" +FILES:${PN}-dev += "${includedir}/arm_ffa_user.h" + +RPROVIDES:${PN} += "kernel-module-arm-ffa-user" + +do_install:append() { + install -D -p -m 0755 ${B}/load_ffa_debugfs.sh ${D}/${bindir}/load_ffa_debugfs.sh + install -m 0644 ${S}/arm_ffa_user.h ${D}/${includedir}/arm_ffa_user.h +} diff --git a/meta-arm/recipes-kernel/ffa-debugfs/files/0001-build-add-Yocto-support.patch b/meta-arm/recipes-kernel/ffa-debugfs/files/0001-build-add-Yocto-support.patch new file mode 100644 index 0000000..5d7e977 --- /dev/null +++ b/meta-arm/recipes-kernel/ffa-debugfs/files/0001-build-add-Yocto-support.patch @@ -0,0 +1,79 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From 8a7bea4e7d08395036ffc2fde57c4fb44315e181 Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi +Date: Mon, 25 Oct 2021 13:12:11 +0100 +Subject: [PATCH 1/2] build: add Yocto support + +This commit allows to build the driver under Yocto + +Signed-off-by: Abdellatif El Khlifi +--- + Kbuild | 4 ---- + Makefile | 40 +++++++++++----------------------------- + 2 files changed, 11 insertions(+), 33 deletions(-) + delete mode 100644 Kbuild + +diff --git a/Kbuild b/Kbuild +deleted file mode 100644 +index 330b019..0000000 +--- a/Kbuild ++++ /dev/null +@@ -1,4 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +- +-arm-ffa-user-objs := arm_ffa_user.o +-obj-m := arm-ffa-user.o +diff --git a/Makefile b/Makefile +index 62dbfb1..90dfaef 100644 +--- a/Makefile ++++ b/Makefile +@@ -1,33 +1,15 @@ +-# SPDX-License-Identifier: GPL-2.0-only ++arm-ffa-user-objs := arm_ffa_user.o ++obj-m := arm-ffa-user.o + +-ARCH := arm64 +-CROSS_COMPILE ?= aarch64-linux-gnu- ++SRC := $(shell pwd) + +-ROOT ?= $(CURDIR)/.. +-KDIR ?= $(ROOT)/linux +-TARGET_DIR ?= $(ROOT)/shared +-BUILD_DIR ?= $(CURDIR)/build +-BUILD_DIR_MAKEFILE ?= $(BUILD_DIR)/Makefile ++all: ++ $(MAKE) -C $(KERNEL_SRC) M=$(SRC) + +-all: module ++modules_install: ++ $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install + +-clean: module-clean +- +-install: all +- cp $(BUILD_DIR)/arm-ffa-user.ko $(TARGET_DIR)/ +- cp load_module.sh $(TARGET_DIR)/ +- +-module: $(BUILD_DIR_MAKEFILE) +- $(MAKE) -C $(KDIR) M=$(BUILD_DIR) src=$(CURDIR) modules \ +- ARCH=$(ARCH) CROSS_COMPILE="$(CROSS_COMPILE)" +- +-module-clean: +- $(MAKE) -C $(KDIR) M=$(BUILD_DIR) src=$(CURDIR) clean \ +- ARCH=$(ARCH) CROSS_COMPILE="$(CROSS_COMPILE)" +- rm $(BUILD_DIR_MAKEFILE) +- +-$(BUILD_DIR): +- mkdir -p "$@" +- +-$(BUILD_DIR_MAKEFILE): $(BUILD_DIR) +- touch "$@" ++clean: ++ rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c ++ rm -f Module.markers Module.symvers modules.order ++ rm -rf .tmp_versions Modules.symvers +-- +2.17.1 + diff --git a/meta-arm/recipes-kernel/ffa-debugfs/files/0002-script-loading-the-driver-in-a-generic-way.patch b/meta-arm/recipes-kernel/ffa-debugfs/files/0002-script-loading-the-driver-in-a-generic-way.patch new file mode 100644 index 0000000..e2469d9 --- /dev/null +++ b/meta-arm/recipes-kernel/ffa-debugfs/files/0002-script-loading-the-driver-in-a-generic-way.patch @@ -0,0 +1,46 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arpita S.K + +From e5d9dfa703a5a57e535b5dab4eda47a9707972d3 Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi +Date: Mon, 25 Oct 2021 12:51:37 +0100 +Subject: [PATCH 2/2] script: loading the driver in a generic way + +Use the kernel module from the modules path. + +Signed-off-by: Abdellatif El Khlifi +--- + load_module.sh => load_ffa_debugfs.sh | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + rename load_module.sh => load_ffa_debugfs.sh (50%) + mode change 100755 => 100644 + +diff --git a/load_module.sh b/load_ffa_debugfs.sh +old mode 100755 +new mode 100644 +similarity index 50% +rename from load_module.sh +rename to load_ffa_debugfs.sh +index 2137245..4f31ff3 +--- a/load_module.sh ++++ b/load_ffa_debugfs.sh +@@ -1,10 +1,14 @@ + #!/bin/sh ++# ++# Use: ++# load_ffa_debugfs.sh ++# + +-[ ! -f $(dirname "$0")/sp_uuid_list.txt ] && \ ++[ ! -f "$1"/sp_uuid_list.txt ] && \ + { echo "Error: missing SP UUID list"; exit 1; } + + if ! grep -qs 'arm-ffa-user' /proc/modules; then +- insmod $(dirname "$0")/arm-ffa-user.ko uuid_str_list=$(cat $(dirname "$0")/sp_uuid_list.txt) ++ insmod /lib/modules/$(uname -r)/extra/arm-ffa-user.ko uuid_str_list=$(cat "$1"/sp_uuid_list.txt) + fi + + if ! grep -qs 'debugfs' /proc/mounts; then +-- +2.17.1 + From patchwork Tue Nov 23 15:59:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 260EAC433F5 for ; Tue, 23 Nov 2021 16:00:17 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.13047.1637683215840777013 for ; Tue, 23 Nov 2021 08:00:16 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 82C031FB; Tue, 23 Nov 2021 08:00:15 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 28E153F5A1; Tue, 23 Nov 2021 08:00:14 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Jon Mason Subject: [PATCH][honister 18/19] corstone1000: Introducing ci and kas files Date: Tue, 23 Nov 2021 15:59:25 +0000 Message-Id: <20211123155926.31743-19-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:17 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2447 From: "Arpita S.K" Adding ci and yaml files to support corstone1000-fvp. Change-Id: I74ebc3570d4b0c8abae58be5ef69064fc33e5bea Signed-off-by: Arpita S.K Signed-off-by: Jon Mason --- .gitlab-ci.yml | 3 +++ ci/corstone1000-fvp.yml | 12 ++++++++++ kas/corstone1000-base.yml | 48 +++++++++++++++++++++++++++++++++++++++ kas/corstone1000-fvp.yml | 16 +++++++++++++ 4 files changed, 79 insertions(+) create mode 100644 ci/corstone1000-fvp.yml create mode 100644 kas/corstone1000-base.yml create mode 100644 kas/corstone1000-fvp.yml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 4a2b336..78f3373 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -109,6 +109,9 @@ corstone700-fvp: corstone700-mps3: extends: .build +corstone1000-fvp: + extends: .build + fvp-base/testimage: extends: .build tags: diff --git a/ci/corstone1000-fvp.yml b/ci/corstone1000-fvp.yml new file mode 100644 index 0000000..66cdec6 --- /dev/null +++ b/ci/corstone1000-fvp.yml @@ -0,0 +1,12 @@ +header: + version: 9 + includes: + - base.yml + - meta-openembedded.yml + +local_conf_header: + custom-local-conf: | + INITRAMFS_IMAGE_BUNDLE = "0" + INITRAMFS_IMAGE:remove = "corstone1000-initramfs-image" + +machine: corstone1000-fvp diff --git a/kas/corstone1000-base.yml b/kas/corstone1000-base.yml new file mode 100644 index 0000000..cbca2c1 --- /dev/null +++ b/kas/corstone1000-base.yml @@ -0,0 +1,48 @@ +header: + version: 9 + +distro: poky-tiny + +defaults: + repos: + refspec: honister + +repos: + meta-arm: + layers: + meta-arm: + meta-arm-bsp: + meta-arm-toolchain: + + poky: + url: https://git.yoctoproject.org/git/poky + refspec: b6b0af0889de9da0e4128cef8c9069b770b7d5a0 + layers: + meta: + meta-poky: + meta-yocto-bsp: + + meta-openembedded: + url: https://git.openembedded.org/meta-openembedded + refspec: ad52a41de8b4b7d619d1376d0a0090ebcfff56da + layers: + meta-oe: + meta-python: + + meta-arm-image: + url: https://git.gitlab.arm.com/arm-reference-solutions/meta-arm-image.git + refspec: CORSTONE-1000-2021.10.26 + +local_conf_header: + base: | + CONF_VERSION = "2" + PACKAGE_CLASSES = "package_ipk" + LICENSE_FLAGS_WHITELIST += "armcompiler" + BB_NUMBER_THREADS ?= "16" + PARALLEL_MAKE ?= "-j16" + PACKAGECONFIG:append:pn-perf = " coresight" + +machine: unset + +target: + - corstone1000-image diff --git a/kas/corstone1000-fvp.yml b/kas/corstone1000-fvp.yml new file mode 100644 index 0000000..ac1920c --- /dev/null +++ b/kas/corstone1000-fvp.yml @@ -0,0 +1,16 @@ +header: + version: 9 + includes: + - corstone1000-base.yml + +repos: + run-scripts: + url: https://git.gitlab.arm.com/arm-reference-solutions/model-scripts.git + refspec: CORSTONE-1000-2021.10.26 + layers: + .: 'excluded' + +machine: corstone1000-fvp + +target: + - corstone1000-image From patchwork Tue Nov 23 15:59:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 244FFC433FE for ; Tue, 23 Nov 2021 16:00:18 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.13302.1637683217394909897 for ; Tue, 23 Nov 2021 08:00:17 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: abdellatif.elkhlifi@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1F0E81063; Tue, 23 Nov 2021 08:00:17 -0800 (PST) Received: from e121910.arm.com (unknown [10.57.78.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C8B983F5A1; Tue, 23 Nov 2021 08:00:15 -0800 (PST) From: abdellatif.elkhlifi@arm.com To: meta-arm@lists.yoctoproject.org, Arpita.S.K@arm.com, vishnu.banavath@arm.com, Ross.Burton@arm.com Cc: nd@arm.com, Jon Mason Subject: [PATCH][honister 19/19] arm/trusted-firmware-a,fiptool-native: Fix fiptool execution wrt corstone1000 Date: Tue, 23 Nov 2021 15:59:26 +0000 Message-Id: <20211123155926.31743-20-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> References: <20211123155926.31743-1-abdellatif.elkhlifi@arm.com> List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 23 Nov 2021 16:00:18 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/2448 From: "Arpita S.K" After http://git.yoctoproject.org/cgit/cgit.cgi/meta-arm/commit/?id=648571b113b39420735859461fcd69cfc6f66c76, building the corstone1000-image fails with the below error. fiptool_platform.h:19:11: fatal error: openssl/sha.h: No such file or directory # include Put back the inclusion of BUILD_LDFLAGS to fix this. Change-Id: I57396eefe2c9a58e4c5c6a751b2ee7d32509cac5 Signed-off-by: Arpita S.K Signed-off-by: Jon Mason --- meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc | 1 + meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb | 1 + 2 files changed, 2 insertions(+) diff --git a/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc b/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc index 3c4cd58..0d49a0a 100644 --- a/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc +++ b/meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc @@ -155,6 +155,7 @@ do_compile() { # This is still needed to have the native fiptool executing properly by # setting the RPATH sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile + sed -i '/^INCLUDE_PATHS/ s,$, \$\{BUILD_CFLAGS},' ${S}/tools/fiptool/Makefile # Currently there are races if you build all the targets at once in parallel for T in ${TFA_BUILD_TARGET}; do diff --git a/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb b/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb index 9ad1166..dd36eca 100644 --- a/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb +++ b/meta-arm/recipes-devtools/fiptool/fiptool-native_2.5.bb @@ -22,6 +22,7 @@ do_compile () { # This is still needed to have the native fiptool executing properly by # setting the RPATH sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile + sed -i '/^INCLUDE_PATHS/ s,$, \$\{BUILD_CFLAGS},' ${S}/tools/fiptool/Makefile oe_runmake fiptool }