From patchwork Thu Jun 5 13:31:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Clement Faure X-Patchwork-Id: 64353 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BF76C61CE8 for ; Thu, 5 Jun 2025 13:31:30 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.7596.1749130283832849838 for ; Thu, 05 Jun 2025 06:31:23 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: clement.faure@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF5981691; Thu, 5 Jun 2025 06:31:05 -0700 (PDT) Received: from MGC575JXM4.emea.arm.com (unknown [10.34.124.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C17D13F5A1; Thu, 5 Jun 2025 06:31:22 -0700 (PDT) From: Clement Faure To: meta-arm@lists.yoctoproject.org Cc: =?utf-8?q?Cl=C3=A9ment_Faure?= Subject: [PATCH 1/3] arm/tf-a-tests: fix header guard compilation warning Date: Thu, 5 Jun 2025 15:31:06 +0200 Message-Id: <20250605133108.35177-2-clement.faure@arm.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250605133108.35177-1-clement.faure@arm.com> References: <20250605133108.35177-1-clement.faure@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 05 Jun 2025 13:31:30 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6530 From: Clément Faure Backport patch to fix the following compilation issue: | In file included from tftf/tests/runtime_services/realm_payload/host_realm_payload_simd_tests.c:21: | tftf/tests/runtime_services/realm_payload/host_realm_simd_common.h:6: error: header guard 'HOST_REALM_COMMON_H' followed by '#define' of a different macro [-Werror=header-guard] | 6 | #ifndef HOST_REALM_COMMON_H | tftf/tests/runtime_services/realm_payload/host_realm_simd_common.h:7: note: 'HOST_REALM_COMMON_h' is defined here; did you mean 'HOST_REALM_COMMON_H'? | 7 | #define HOST_REALM_COMMON_h | In file included from tftf/tests/runtime_services/realm_payload/host_realm_simd_common.c:13: | tftf/tests/runtime_services/realm_payload/host_realm_simd_common.h:6: error: header guard 'HOST_REALM_COMMON_H' followed by '#define' of a different macro [-Werror=header-guard] | 6 | #ifndef HOST_REALM_COMMON_H | tftf/tests/runtime_services/realm_payload/host_realm_simd_common.h:7: note: 'HOST_REALM_COMMON_h' is defined here; did you mean 'HOST_REALM_COMMON_H'? | 7 | #define HOST_REALM_COMMON_h | CC tftf/tests/runtime_services/secure_service/spm_test_helpers.c | In file included from tftf/tests/runtime_services/realm_payload/host_realm_spm.c:20: | tftf/tests/runtime_services/realm_payload/host_realm_simd_common.h:6: error: header guard 'HOST_REALM_COMMON_H' followed by '#define' of a different macro [-Werror=header-guard] | 6 | #ifndef HOST_REALM_COMMON_H | tftf/tests/runtime_services/realm_payload/host_realm_simd_common.h:7: note: 'HOST_REALM_COMMON_h' is defined here; did you mean 'HOST_REALM_COMMON_H'? | 7 | #define HOST_REALM_COMMON_h | cc1: all warnings being treated as errors | make: *** [Makefile:605: workspace/corstone1000/build/tmp/work/cortexa35-poky-linux-musl/tf-a-tests/2.12.0/build/corstone1000/release/tftf/host_realm_simd_common.o] Error 1 | make: *** Waiting for unfinished jobs.... | cc1: all warnings being treated as errors | make: *** [Makefile:605: workspace/corstone1000/build/tmp/work/cortexa35-poky-linux-musl/tf-a-tests/2.12.0/build/corstone1000/release/tftf/host_realm_spm.o] Error 1 | cc1: all warnings being treated as errors | make: *** [Makefile:605: workspace/corstone1000/build/tmp/work/cortexa35-poky-linux-musl/tf-a-tests/2.12.0/build/corstone1000/release/tftf/host_realm_payload_simd_tests.o] Error 1 | make: Leaving directory 'workspace/corstone1000/build/tmp/work/cortexa35-poky-linux-musl/tf-a-tests/2.12.0/git' Signed-off-by: Clément Faure --- ...-make-PCIe-tests-default-for-testing.patch | 531 ++++++++++++++++++ .../trusted-firmware-a/tf-a-tests_2.12.0.bb | 1 + 2 files changed, 532 insertions(+) create mode 100644 meta-arm/recipes-bsp/trusted-firmware-a/files/0001-fix-realm-make-PCIe-tests-default-for-testing.patch diff --git a/meta-arm/recipes-bsp/trusted-firmware-a/files/0001-fix-realm-make-PCIe-tests-default-for-testing.patch b/meta-arm/recipes-bsp/trusted-firmware-a/files/0001-fix-realm-make-PCIe-tests-default-for-testing.patch new file mode 100644 index 00000000..f8f998a6 --- /dev/null +++ b/meta-arm/recipes-bsp/trusted-firmware-a/files/0001-fix-realm-make-PCIe-tests-default-for-testing.patch @@ -0,0 +1,531 @@ +From f5c206b8d9019d8112e55ac8da1936c79c7d2ce7 Mon Sep 17 00:00:00 2001 +From: Soby Mathew +Date: Fri, 15 Nov 2024 17:11:24 +0000 +Subject: [PATCH] fix(realm): make PCIe tests default for testing + +This patch moves the PCIe DOE test to the default realm world +testsuite. + +Also fixes some build issues and hardens the PCIe functions. + +Note that FVP_Base_RevC model needs to have the following +options enabled for the PCIe tests to work : + + -C pci.pcie_rc.ahci0.endpoint.doe_supported=1 + -C pci.pcie_rc.ahci0.endpoint.ide_supported=1 + +Change-Id: Icfd6b68799b0bacb44299c6a3cf99a3c425f833d +Signed-off-by: Soby Mathew +Upstream-Status: Backport [2c2810f79e57e78d77899084b5439cbdd1aaa464] +--- + docs/porting/optional-mods.rst | 12 ++++++ + include/lib/pcie/pcie.h | 9 ++-- + include/plat/common/platform.h | 10 ++++- + lib/pcie/pcie.c | 41 ++++++++++++++----- + plat/arm/fvp/fvp_pcie.c | 4 +- + plat/arm/fvp/include/platform_pcie.h | 2 - + plat/arm/fvp/plat_setup.c | 2 - + plat/arm/fvp/platform.mk | 9 ++-- + plat/common/plat_common.c | 8 +++- + tftf/tests/doe_tests/doe_helpers.c | 11 +++-- + tftf/tests/doe_tests/doe_helpers.h | 2 + + tftf/tests/doe_tests/test_doe.c | 9 +++- + .../realm_payload/host_realm_simd_common.h | 2 +- + tftf/tests/tests-pcie-doe.mk | 22 ---------- + tftf/tests/tests-pcie-doe.xml | 14 ------- + tftf/tests/tests-realm-payload.mk | 14 ++++++- + tftf/tests/tests-realm-payload.xml | 7 +++- + 17 files changed, 105 insertions(+), 73 deletions(-) + delete mode 100644 tftf/tests/tests-pcie-doe.mk + delete mode 100644 tftf/tests/tests-pcie-doe.xml + +diff --git a/docs/porting/optional-mods.rst b/docs/porting/optional-mods.rst +index a88d682..7fc3813 100644 +--- a/docs/porting/optional-mods.rst ++++ b/docs/porting/optional-mods.rst +@@ -50,6 +50,18 @@ The default implementation uses the ARM watchdog peripheral (`SP805`_) to + generate a watchdog timeout interrupt. This interrupt remains deliberately + unserviced, which eventually asserts the reset signal. + ++Function : plat_pcie_get_info_table() ++---------------------------- ++ ++:: ++ ++ Argument : void ++ Return : struct pcie_info_table * ++ ++This function returns the pointer to `pcie_info_table` structure ++correponding to the platform. This needs to be implemented ++only if the platform want to run PCIe related tests. ++ + -------------- + + *Copyright (c) 2019, Arm Limited. All rights reserved.* +diff --git a/include/lib/pcie/pcie.h b/include/lib/pcie/pcie.h +index aa3911f..3ce6986 100644 +--- a/include/lib/pcie/pcie.h ++++ b/include/lib/pcie/pcie.h +@@ -11,6 +11,9 @@ + #include + #include + ++/* platforms need to ensure that number of entries is less that this value */ ++#define MAX_PCIE_INFO_ENTRIES 5 ++ + typedef struct { + unsigned long ecam_base; /* ECAM base address */ + unsigned int segment_num; /* Segment number of this ECAM */ +@@ -18,10 +21,10 @@ typedef struct { + unsigned int end_bus_num; /* Last bus number */ + } pcie_info_block_t; + +-typedef struct { ++struct pcie_info_table{ + unsigned int num_entries; /* Number of entries */ +- pcie_info_block_t block[]; +-} pcie_info_table_t; ++ pcie_info_block_t block[MAX_PCIE_INFO_ENTRIES]; ++}; + + typedef struct { + uint32_t bdf; +diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h +index c8b785c..1a51823 100644 +--- a/include/plat/common/platform.h ++++ b/include/plat/common/platform.h +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2018-2019, Arm Limited. All rights reserved. ++ * Copyright (c) 2018-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -193,4 +193,12 @@ static inline uint32_t get_current_core_id(void) + return platform_get_core_pos(read_mpidr_el1() & MPID_MASK); + } + ++/* Forward declaration */ ++struct pcie_info_table; ++ ++/* ++ * Retrieve platform PCIe information. ++ */ ++const struct pcie_info_table *plat_pcie_get_info_table(void); ++ + #endif /* __PLATFORM_H__ */ +diff --git a/lib/pcie/pcie.c b/lib/pcie/pcie.c +index c3906d5..5f8c97f 100644 +--- a/lib/pcie/pcie.c ++++ b/lib/pcie/pcie.c +@@ -11,13 +11,12 @@ + #include + #include + #include ++#include + #include + +-#include +- + #define PCIE_DEBUG VERBOSE + +-const pcie_info_table_t *g_pcie_info_table; ++const struct pcie_info_table *g_pcie_info_table; + pcie_device_bdf_table_t *g_pcie_bdf_table; + + pcie_device_bdf_table_t pcie_bdf_table[PCIE_DEVICE_BDF_TABLE_SZ]; +@@ -256,6 +255,8 @@ uint32_t pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf) + return 1; + } + ++ assert(g_pcie_bdf_table != NULL); ++ + while (index < g_pcie_bdf_table->num_entries) { + *rp_bdf = g_pcie_bdf_table->device[index++].bdf; + +@@ -294,6 +295,8 @@ static uint32_t pcie_populate_device_rootport(void) + uint32_t bdf, rp_bdf; + pcie_device_bdf_table_t *bdf_tbl_ptr = g_pcie_bdf_table; + ++ assert(bdf_tbl_ptr != NULL); ++ + for (unsigned int tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; + tbl_index++) { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; +@@ -317,6 +320,8 @@ static uint32_t pcie_populate_device_rootport(void) + */ + pcie_device_bdf_table_t *pcie_get_bdf_table(void) + { ++ assert(g_pcie_bdf_table != NULL); ++ + return g_pcie_bdf_table; + } + +@@ -336,6 +341,8 @@ void pcie_create_device_bdf_table(void) + assert(g_pcie_bdf_table != NULL); + + g_pcie_bdf_table->num_entries = 0; ++ ++ assert(g_pcie_info_table != NULL); + assert(g_pcie_info_table->num_entries != 0); + + for (ecam_index = 0; ecam_index < g_pcie_info_table->num_entries; ecam_index++) { +@@ -420,6 +427,8 @@ uintptr_t pcie_get_ecam_base(uint32_t bdf) + uint32_t reg_value; + uintptr_t ecam_base = 0; + ++ assert(g_pcie_info_table != NULL); ++ + while (ecam_index < g_pcie_info_table->num_entries) { + /* Derive ECAM specific information */ + const pcie_info_block_t *block = &g_pcie_info_table->block[ecam_index]; +@@ -462,13 +471,15 @@ void pcie_print_device_info(void) + uint32_t ecam_index = 0; + uint32_t ecam_base, ecam_start_bus, ecam_end_bus; + pcie_device_bdf_table_t *bdf_tbl_ptr = g_pcie_bdf_table; +- uint32_t num_rciep = 0, num_rcec = 0; +- uint32_t num_iep = 0, num_irp = 0; +- uint32_t num_ep = 0, num_rp = 0; +- uint32_t num_dp = 0, num_up = 0; +- uint32_t num_pcie_pci = 0, num_pci_pcie = 0; ++ uint32_t num_rciep __unused = 0, num_rcec __unused = 0; ++ uint32_t num_iep __unused = 0, num_irp __unused = 0; ++ uint32_t num_ep __unused = 0, num_rp __unused = 0; ++ uint32_t num_dp __unused = 0, num_up __unused = 0; ++ uint32_t num_pcie_pci __unused = 0, num_pci_pcie __unused = 0; + uint32_t bdf_counter; + ++ assert(bdf_tbl_ptr != NULL); ++ + if (bdf_tbl_ptr->num_entries == 0) { + INFO("BDF Table: No RCiEP or iEP found\n"); + return; +@@ -525,6 +536,8 @@ void pcie_print_device_info(void) + INFO("Number of PCI/PCIe Bridge: %u\n", num_pci_pcie); + INFO("Number of PCIe/PCI Bridge: %u\n", num_pcie_pci); + ++ assert(g_pcie_info_table != NULL); ++ + while (ecam_index < g_pcie_info_table->num_entries) { + + /* Derive ECAM specific information */ +@@ -540,7 +553,7 @@ void pcie_print_device_info(void) + + while (tbl_index < bdf_tbl_ptr->num_entries) { + uint32_t seg_num, bus_num, dev_num, func_num; +- uint32_t device_id, vendor_id, reg_value; ++ uint32_t device_id __unused, vendor_id __unused, reg_value; + uint32_t bdf, dev_ecam_base; + + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; +@@ -588,12 +601,18 @@ void pcie_create_info_table(void) + INFO("Creating PCIe info table\n"); + + g_pcie_info_table = plat_pcie_get_info_table(); ++ if (g_pcie_info_table == NULL) { ++ ERROR("PCIe info not returned by platform\n"); ++ panic(); ++ } ++ + g_pcie_bdf_table = pcie_bdf_table; + + num_ecam = g_pcie_info_table->num_entries; + INFO("Number of ECAM regions : %u\n", num_ecam); +- if (num_ecam == 0) { +- return; ++ if ((num_ecam == 0) || (num_ecam > MAX_PCIE_INFO_ENTRIES)) { ++ ERROR("PCIe info entries invalid\n"); ++ panic(); + } + pcie_create_device_bdf_table(); + pcie_print_device_info(); +diff --git a/plat/arm/fvp/fvp_pcie.c b/plat/arm/fvp/fvp_pcie.c +index 0569832..c43e42d 100644 +--- a/plat/arm/fvp/fvp_pcie.c ++++ b/plat/arm/fvp/fvp_pcie.c +@@ -11,7 +11,7 @@ + + CASSERT(PLATFORM_NUM_ECAM != 0, PLATFORM_NUM_ECAM_is_zero); + +-const pcie_info_table_t fvp_pcie_cfg = { ++const struct pcie_info_table fvp_pcie_cfg = { + .num_entries = PLATFORM_NUM_ECAM, + .block[0] = { + PLATFORM_PCIE_ECAM_BASE_ADDR_0, +@@ -21,7 +21,7 @@ const pcie_info_table_t fvp_pcie_cfg = { + } + }; + +-const pcie_info_table_t *plat_pcie_get_info_table(void) ++const struct pcie_info_table *plat_pcie_get_info_table(void) + { + return &fvp_pcie_cfg; + } +diff --git a/plat/arm/fvp/include/platform_pcie.h b/plat/arm/fvp/include/platform_pcie.h +index c76c7d9..4b3a0e9 100644 +--- a/plat/arm/fvp/include/platform_pcie.h ++++ b/plat/arm/fvp/include/platform_pcie.h +@@ -19,6 +19,4 @@ + #define PLATFORM_PCIE_START_BUS_NUM_0 0x0 + #define PLATFORM_PCIE_END_BUS_NUM_0 0xFF + +-const pcie_info_table_t *plat_pcie_get_info_table(void); +- + #endif /* PLATFORM_PCIE_H */ +diff --git a/plat/arm/fvp/plat_setup.c b/plat/arm/fvp/plat_setup.c +index e6e4244..69cb0a1 100644 +--- a/plat/arm/fvp/plat_setup.c ++++ b/plat/arm/fvp/plat_setup.c +@@ -35,9 +35,7 @@ static const mmap_region_t mmap[] = { + #if USE_NVM + MAP_REGION_FLAT(FLASH_BASE, FLASH_SIZE, MT_DEVICE | MT_RW | MT_NS), + #endif +-#if USE_PCIE + MAP_REGION_FLAT(PCIE_CONFIG_BASE, PCIE_CONFIG_SIZE, MT_DEVICE | MT_RW | MT_NS), +-#endif + MAP_REGION_FLAT(DRAM_BASE, TFTF_BASE - DRAM_BASE, MT_MEMORY | MT_RW | MT_NS), + {0} + }; +diff --git a/plat/arm/fvp/platform.mk b/plat/arm/fvp/platform.mk +index 7a2850f..ee30721 100644 +--- a/plat/arm/fvp/platform.mk ++++ b/plat/arm/fvp/platform.mk +@@ -90,12 +90,8 @@ $(eval $(call add_define,NS_BL2U_DEFINES,PA_SIZE)) + $(eval $(call add_define,TFTF_DEFINES,PA_SIZE)) + $(eval $(call add_define,REALM_DEFINES,PA_SIZE)) + +-ifeq ($(TESTS),pcie-doe) +-USE_PCIE=1 +-$(eval $(call add_define,TFTF_DEFINES,USE_PCIE)) +-endif +- +-PLAT_INCLUDES += -Iplat/arm/fvp/include/ ++PLAT_INCLUDES += -Iplat/arm/fvp/include/ \ ++ -Iinclude/lib/pcie/ + + PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \ + drivers/arm/gic/gic_v2.c \ +@@ -104,6 +100,7 @@ PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \ + drivers/arm/timer/private_timer.c \ + drivers/arm/timer/system_timer.c \ + plat/arm/fvp/${ARCH}/plat_helpers.S \ ++ plat/arm/fvp/fvp_pcie.c \ + plat/arm/fvp/fvp_pwr_state.c \ + plat/arm/fvp/fvp_topology.c \ + plat/arm/fvp/fvp_mem_prot.c \ +diff --git a/plat/common/plat_common.c b/plat/common/plat_common.c +index c43ae12..a4195c3 100644 +--- a/plat/common/plat_common.c ++++ b/plat/common/plat_common.c +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2018-2020, Arm Limited. All rights reserved. ++ * Copyright (c) 2018-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -24,6 +24,7 @@ + #pragma weak tftf_plat_enable_mmu + #pragma weak tftf_plat_reset + #pragma weak plat_get_prot_regions ++#pragma weak plat_pcie_get_info_table + + #if IMAGE_TFTF + +@@ -148,3 +149,8 @@ const mem_region_t *plat_get_prot_regions(int *nelem) + *nelem = 0; + return NULL; + } ++ ++const struct pcie_info_table *plat_pcie_get_info_table(void) ++{ ++ return NULL; ++} +diff --git a/tftf/tests/doe_tests/doe_helpers.c b/tftf/tests/doe_tests/doe_helpers.c +index 28b6a86..911fbd0 100644 +--- a/tftf/tests/doe_tests/doe_helpers.c ++++ b/tftf/tests/doe_tests/doe_helpers.c +@@ -13,12 +13,15 @@ + #include + #include + +-#include +- + void pcie_init(void) + { ++ static bool is_init; ++ + /* Create PCIe table and enumeration */ +- pcie_create_info_table(); ++ if (!is_init) { ++ pcie_create_info_table(); ++ is_init = true; ++ } + } + + /* +@@ -113,7 +116,7 @@ int get_spdm_version(uint32_t bdf, uint32_t doe_cap_base) + sizeof(ver_resp->version_number_entry_count)); + + while (entry_count-- != 0) { +- spdm_version_number_t ver = *ver_ptr++; ++ spdm_version_number_t ver __unused = *ver_ptr++; + + INFO("SPDM v%llu.%llu.%llu.%llu\n", + EXTRACT(SPDM_VER_MAJOR, ver), +diff --git a/tftf/tests/doe_tests/doe_helpers.h b/tftf/tests/doe_tests/doe_helpers.h +index 08137e3..d0fc5c8 100644 +--- a/tftf/tests/doe_tests/doe_helpers.h ++++ b/tftf/tests/doe_tests/doe_helpers.h +@@ -8,6 +8,8 @@ + #ifndef DOE_HELPERS_H + #define DOE_HELPERS_H + ++#include ++ + void pcie_init(void); + int find_doe_device(uint32_t *bdf_ptr, uint32_t *cap_base_ptr); + int doe_discovery(uint32_t bdf, uint32_t doe_cap_base); +diff --git a/tftf/tests/doe_tests/test_doe.c b/tftf/tests/doe_tests/test_doe.c +index 6eb5079..cc852fa 100644 +--- a/tftf/tests/doe_tests/test_doe.c ++++ b/tftf/tests/doe_tests/test_doe.c +@@ -10,6 +10,13 @@ + + #define SKIP_TEST_IF_DOE_NOT_SUPPORTED() \ + do { \ ++ /* Test PCIe DOE only for RME */ \ ++ if (!get_armv9_2_feat_rme_support()) { \ ++ tftf_testcase_printf("FEAT_RME not supported\n"); \ ++ return TEST_RESULT_SKIPPED; \ ++ } \ ++ \ ++ pcie_init(); \ + if (find_doe_device(&bdf, &doe_cap_base) != 0) { \ + tftf_testcase_printf("PCIe DOE not supported\n"); \ + return TEST_RESULT_SKIPPED; \ +@@ -21,8 +28,6 @@ test_result_t doe_discovery_test(void) + uint32_t bdf, doe_cap_base; + int ret; + +- pcie_init(); +- + SKIP_TEST_IF_DOE_NOT_SUPPORTED(); + + ret = doe_discovery(bdf, doe_cap_base); +diff --git a/tftf/tests/runtime_services/realm_payload/host_realm_simd_common.h b/tftf/tests/runtime_services/realm_payload/host_realm_simd_common.h +index 377c85b..6ab45c3 100644 +--- a/tftf/tests/runtime_services/realm_payload/host_realm_simd_common.h ++++ b/tftf/tests/runtime_services/realm_payload/host_realm_simd_common.h +@@ -4,7 +4,7 @@ + */ + + #ifndef HOST_REALM_COMMON_H +-#define HOST_REALM_COMMON_h ++#define HOST_REALM_COMMON_H + + #define NS_NORMAL_SVE 0x1U + #define NS_STREAMING_SVE 0x2U +diff --git a/tftf/tests/tests-pcie-doe.mk b/tftf/tests/tests-pcie-doe.mk +deleted file mode 100644 +index 14bc9cf..0000000 +--- a/tftf/tests/tests-pcie-doe.mk ++++ /dev/null +@@ -1,22 +0,0 @@ +-# +-# Copyright (c) 2024, Arm Limited. All rights reserved. +-# +-# SPDX-License-Identifier: BSD-3-Clause +-# +- +-TESTS_SOURCES += \ +- $(addprefix plat/arm/fvp/, \ +- fvp_pcie.c \ +- ) +- +-TESTS_SOURCES += \ +- $(addprefix tftf/tests/doe_tests/, \ +- doe_helpers.c \ +- test_doe.c \ +- ) +- +-TESTS_SOURCES += \ +- $(addprefix lib/pcie/, \ +- pcie.c \ +- pcie_doe.c \ +- ) +diff --git a/tftf/tests/tests-pcie-doe.xml b/tftf/tests/tests-pcie-doe.xml +deleted file mode 100644 +index ed8b7cb..0000000 +--- a/tftf/tests/tests-pcie-doe.xml ++++ /dev/null +@@ -1,14 +0,0 @@ +- +- +- +- +- +- +- +- +- +- +diff --git a/tftf/tests/tests-realm-payload.mk b/tftf/tests/tests-realm-payload.mk +index ae4b20a..4da8e3e 100644 +--- a/tftf/tests/tests-realm-payload.mk ++++ b/tftf/tests/tests-realm-payload.mk +@@ -1,5 +1,5 @@ + # +-# Copyright (c) 2021-2023, Arm Limited. All rights reserved. ++# Copyright (c) 2021-2024, Arm Limited. All rights reserved. + # + # SPDX-License-Identifier: BSD-3-Clause + # +@@ -44,4 +44,16 @@ TESTS_SOURCES += \ + $(addprefix lib/extensions/fpu/, \ + fpu.c \ + ) ++ ++TESTS_SOURCES += \ ++ $(addprefix tftf/tests/doe_tests/, \ ++ doe_helpers.c \ ++ test_doe.c \ ++ ) ++ ++TESTS_SOURCES += \ ++ $(addprefix lib/pcie/, \ ++ pcie.c \ ++ pcie_doe.c \ ++ ) + endif +diff --git a/tftf/tests/tests-realm-payload.xml b/tftf/tests/tests-realm-payload.xml +index 3c0dda4..d99a6b9 100644 +--- a/tftf/tests/tests-realm-payload.xml ++++ b/tftf/tests/tests-realm-payload.xml +@@ -1,7 +1,7 @@ + + + +@@ -126,5 +126,10 @@ + function="host_test_non_lpa2_realm_on_lpa2plat" /> + ++ ++ ++ + + +-- +2.34.1 + diff --git a/meta-arm/recipes-bsp/trusted-firmware-a/tf-a-tests_2.12.0.bb b/meta-arm/recipes-bsp/trusted-firmware-a/tf-a-tests_2.12.0.bb index 31b0964b..105f0a4a 100644 --- a/meta-arm/recipes-bsp/trusted-firmware-a/tf-a-tests_2.12.0.bb +++ b/meta-arm/recipes-bsp/trusted-firmware-a/tf-a-tests_2.12.0.bb @@ -9,6 +9,7 @@ COMPATIBLE_MACHINE ?= "invalid" SRC_URI_TRUSTED_FIRMWARE_A_TESTS ?= "git://git.trustedfirmware.org/TF-A/tf-a-tests.git;protocol=https" SRC_URI = "${SRC_URI_TRUSTED_FIRMWARE_A_TESTS};branch=${SRCBRANCH} \ + file://0001-fix-realm-make-PCIe-tests-default-for-testing.patch \ " SRCBRANCH = "master" SRCREV = "6a113621a9efdc143e9270b1789046cd7d9cdfb1" From patchwork Thu Jun 5 13:31:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Clement Faure X-Patchwork-Id: 64352 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BF35C5AE59 for ; Thu, 5 Jun 2025 13:31:30 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.7597.1749130284801680581 for ; Thu, 05 Jun 2025 06:31:24 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: clement.faure@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0ACBC1692; Thu, 5 Jun 2025 06:31:07 -0700 (PDT) Received: from MGC575JXM4.emea.arm.com (unknown [10.34.124.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CA03A3F5A1; Thu, 5 Jun 2025 06:31:23 -0700 (PDT) From: Clement Faure To: meta-arm@lists.yoctoproject.org Cc: =?utf-8?q?Cl=C3=A9ment_Faure?= Subject: [PATCH 2/3] arm-bsp/trusted-firmware-a: corstone1000: Upgrade TF-A to 2.12.1 Date: Thu, 5 Jun 2025 15:31:07 +0200 Message-Id: <20250605133108.35177-3-clement.faure@arm.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250605133108.35177-1-clement.faure@arm.com> References: <20250605133108.35177-1-clement.faure@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 05 Jun 2025 13:31:30 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6531 From: Clément Faure Upgrade trusted-firmware-a to 2.12.1 for Corstone-1000 When GENERATE_COT is enabled, use the Yocto dependency cot-dt2c instead of installing it with Poetry. Signed-off-by: Clément Faure --- meta-arm-bsp/conf/machine/include/corstone1000.inc | 4 ++-- .../trusted-firmware-a/trusted-firmware-a-corstone1000.inc | 6 ++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/meta-arm-bsp/conf/machine/include/corstone1000.inc b/meta-arm-bsp/conf/machine/include/corstone1000.inc index 6d68cd0f..bbaeee29 100644 --- a/meta-arm-bsp/conf/machine/include/corstone1000.inc +++ b/meta-arm-bsp/conf/machine/include/corstone1000.inc @@ -7,8 +7,8 @@ PREFERRED_VERSION_trusted-firmware-m ?= "2.1.%" # TF-A TFA_PLATFORM = "corstone1000" -PREFERRED_VERSION_trusted-firmware-a ?= "2.11.%" -PREFERRED_VERSION_tf-a-tests ?= "2.10.%" +PREFERRED_VERSION_trusted-firmware-a ?= "2.12.%" +PREFERRED_VERSION_tf-a-tests ?= "2.12.%" TFA_BL2_BINARY = "bl2-corstone1000.bin" TFA_FIP_BINARY = "fip-corstone1000.bin" diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc index f6677f70..5e41ab6e 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc @@ -56,3 +56,9 @@ EXTRA_OEMAKE:append = " \ FVP_USE_GIC_DRIVER=FVP_GICV2 \ " EXTRA_OEMAKE:append:corstone1000-fvp = "${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_fvp_smp', ' ENABLE_MULTICORE=1', '', d)}" + +# If GENERATE_COT is set, then TF-A will try to use local poetry install +# to run the python cot-dt2c command. Disable the local poetry and use +# the provided cot-dt2c. +EXTRA_OEMAKE += "POETRY=''" +DEPENDS += "cot-dt2c-native" From patchwork Thu Jun 5 13:31:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Clement Faure X-Patchwork-Id: 64351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D633C5B552 for ; Thu, 5 Jun 2025 13:31:30 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.7796.1749130285908339402 for ; Thu, 05 Jun 2025 06:31:26 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: clement.faure@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1679D168F; Thu, 5 Jun 2025 06:31:08 -0700 (PDT) Received: from MGC575JXM4.emea.arm.com (unknown [10.34.124.26]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DA4653F5A1; Thu, 5 Jun 2025 06:31:24 -0700 (PDT) From: Clement Faure To: meta-arm@lists.yoctoproject.org Cc: =?utf-8?q?Cl=C3=A9ment_Faure?= Subject: [PATCH 3/3] arm-bsp/trusted-firmware-a: corstone1000: remove TF-A 2.11.0 recipe Date: Thu, 5 Jun 2025 15:31:08 +0200 Message-Id: <20250605133108.35177-4-clement.faure@arm.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250605133108.35177-1-clement.faure@arm.com> References: <20250605133108.35177-1-clement.faure@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 05 Jun 2025 13:31:30 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/6532 From: Clément Faure Remove TF-A 2.11.0 Yocto recipe. Remove patches that are now upstreamed in TF-A 2.12 Signed-off-by: Clément Faure --- ...stone1000-pass-spsr-value-explicitly.patch | 32 ---- ...0-remove-unused-NS_SHARED_RAM-region.patch | 92 ---------- ...-clean-the-cache-and-disable-interru.patch | 46 ----- ...0-Add-multicore-support-for-FVP-plat.patch | 161 ------------------ ...one1000-include-platform-header-file.patch | 28 --- .../trusted-firmware-a-corstone1000.inc | 5 - .../trusted-firmware-a_2.11.0.bb | 20 --- 7 files changed, 384 deletions(-) delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-fix-corstone1000-pass-spsr-value-explicitly.patch delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0005-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-include-platform-header-file.patch delete mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.11.0.bb diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-fix-corstone1000-pass-spsr-value-explicitly.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-fix-corstone1000-pass-spsr-value-explicitly.patch deleted file mode 100644 index 276d095d..00000000 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-fix-corstone1000-pass-spsr-value-explicitly.patch +++ /dev/null @@ -1,32 +0,0 @@ -From d70a07562d3b0a7b4441922fd3ce136565927d04 Mon Sep 17 00:00:00 2001 -From: Emekcan Aras -Date: Wed, 21 Feb 2024 07:57:36 +0000 -Subject: [PATCH] fix(corstone1000): pass spsr value explicitly - -Passes spsr value for BL32 (OPTEE) explicitly between different boot -stages. - -Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/30116/2] -Signed-off-by: Emekcan Aras ---- - .../corstone1000/common/corstone1000_bl2_mem_params_desc.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c -index fe521a9fa..2cc096f38 100644 ---- a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c -+++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c -@@ -72,7 +72,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), - .ep_info.pc = BL33_BASE, -- -+ .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, -+ DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = BL33_BASE, --- -2.25.1 - - diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch deleted file mode 100644 index f9a0c116..00000000 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 19600e6718e1a5b2ac8ec27d471acdafce0e433e Mon Sep 17 00:00:00 2001 -From: Emekcan Aras -Date: Thu, 25 Apr 2024 11:30:58 +0100 -Subject: [PATCH] fix(corstone1000): remove unused NS_SHARED_RAM region - -After enabling additional features in Trusted Services, the size of BL32 image -(OP-TEE + Trusted Services SPs) is larger now. To create more space in secure RAM -for BL32 image, this patch removes NS_SHARED_RAM region which is not currently used by -corstone1000 platform. - -Signed-off-by: Emekcan Aras -Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/30117/2] ---- - .../corstone1000/common/corstone1000_plat.c | 1 - - .../common/include/platform_def.h | 19 +------------------ - 2 files changed, 1 insertion(+), 19 deletions(-) - -diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c -index ed3801caa..a9475859a 100644 ---- a/plat/arm/board/corstone1000/common/corstone1000_plat.c -+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c -@@ -23,7 +23,6 @@ - - const mmap_region_t plat_arm_mmap[] = { - ARM_MAP_SHARED_RAM, -- ARM_MAP_NS_SHARED_RAM, - ARM_MAP_NS_DRAM1, - CORSTONE1000_MAP_DEVICE, - CORSTONE1000_EXTERNAL_FLASH, -diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h -index 442d187f0..18fce4486 100644 ---- a/plat/arm/board/corstone1000/common/include/platform_def.h -+++ b/plat/arm/board/corstone1000/common/include/platform_def.h -@@ -90,9 +90,6 @@ - * partition size: 176 KB - * content: BL2 - * -- * = + 1 MB -- * partition size: 512 KB -- * content: BL33 (u-boot) - */ - - /* DDR memory */ -@@ -117,11 +114,7 @@ - /* The remaining Trusted SRAM is used to load the BL images */ - #define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */ - --/* Last 512KB of CVM is allocated for shared RAM as an example openAMP */ --#define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K) -- - #define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \ -- ARM_NS_SHARED_RAM_SIZE - \ - ARM_SHARED_RAM_SIZE) - - #define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */ -@@ -160,11 +153,6 @@ - - /* NS memory */ - --/* The last 512KB of the SRAM is allocated as shared memory */ --#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \ -- (PLAT_ARM_MAX_BL31_SIZE + \ -- PLAT_ARM_MAX_BL32_SIZE)) -- - #define BL33_BASE ARM_DRAM1_BASE - #define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/ - #define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE) -@@ -266,7 +254,7 @@ - #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE - #define PLAT_ARM_NSTIMER_FRAME_ID U(1) - --#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE) -+#define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE) - - #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) - #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) -@@ -295,11 +283,6 @@ - ARM_SHARED_RAM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) - --#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \ -- ARM_NS_SHARED_RAM_BASE, \ -- ARM_NS_SHARED_RAM_SIZE, \ -- MT_MEMORY | MT_RW | MT_NS) -- - #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ - ARM_NS_DRAM1_BASE, \ - ARM_NS_DRAM1_SIZE, \ --- -2.25.1 - - diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch deleted file mode 100644 index e92cb5f9..00000000 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 37f92eeb4361626072e690adb3b0bb20db7c2fca Mon Sep 17 00:00:00 2001 -From: Emekcan Aras -Date: Wed, 15 May 2024 13:54:51 +0100 -Subject: [PATCH] fix(corstone1000): clean the cache and disable interrupt - before system reset - -Corstone1000 does not properly clean the cache and disable gic interrupts -before the reset. This causes a race condition especially in FVP after reset. -This adds proper sequence before resetting the platform. - -Signed-off-by: Emekcan Aras -Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/30118/2] ---- - plat/arm/board/corstone1000/common/corstone1000_pm.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c -index 4b0a791e7..a52e945bf 100644 ---- a/plat/arm/board/corstone1000/common/corstone1000_pm.c -+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - /******************************************************************************* - * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard - * platform layer will take care of registering the handlers with PSCI. -@@ -18,6 +19,14 @@ static void __dead2 corstone1000_system_reset(void) - uint32_t volatile * const watchdog_ctrl_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_CTRL_REG; - uint32_t volatile * const watchdog_val_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_VAL_REG; - -+ /* Flush and invalidate data cache */ -+ dcsw_op_all(DCCISW); -+ /* -+ * Disable GIC CPU interface to prevent pending interrupt -+ * from waking up the AP from WFI. -+ */ -+ gicv2_cpuif_disable(); -+ - *(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL; - *watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE; - while (1) { --- -2.25.1 - diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0005-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0005-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch deleted file mode 100644 index 2a385d83..00000000 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0005-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch +++ /dev/null @@ -1,161 +0,0 @@ -From dcc9cf5111c41edc691f007bd97548d96f5efddb Mon Sep 17 00:00:00 2001 -From: Harsimran Singh Tungal -Date: Thu, 9 May 2024 16:59:34 +0000 -Subject: [PATCH] feat(corstone1000): add multicore support for fvp - -This changeset adds the multicore support for the Corstone-1000 FVP. -It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities -for the secondary cores. - -Upstream-Status: Backport [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/29176] -Signed-off-by: Harsimran Singh Tungal ---- - .../common/corstone1000_helpers.S | 26 +++++++++++ - .../corstone1000/common/corstone1000_pm.c | 43 ++++++++++++++++++- - .../common/include/platform_def.h | 15 ++++++- - plat/arm/board/corstone1000/platform.mk | 7 +++ - 4 files changed, 89 insertions(+), 2 deletions(-) - -diff --git a/plat/arm/board/corstone1000/common/corstone1000_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S -index cbe27c3b5..90dc4fee6 100644 ---- a/plat/arm/board/corstone1000/common/corstone1000_helpers.S -+++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S -@@ -21,8 +21,34 @@ - * -------------------------------------------------------------------- - */ - func plat_secondary_cold_boot_setup -+#if defined(CORSTONE1000_FVP_MULTICORE) -+ -+ /* Calculate the address of our hold entry */ -+ bl plat_my_core_pos -+ lsl x0, x0, #CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT -+ mov_imm x2, CORSTONE1000_SECONDARY_CORE_HOLD_BASE -+ -+ /* Set the wait state for the secondary core */ -+ mov_imm x3, CORSTONE1000_SECONDARY_CORE_STATE_WAIT -+ str x3, [x2, x0] -+ dmb ish -+ -+ /* Poll until the primary core signals to go */ -+poll_mailbox: -+ ldr x1, [x2, x0] -+ cmp x1, #CORSTONE1000_SECONDARY_CORE_STATE_WAIT -+ beq 1f -+ mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE -+ ldr x1, [x0] -+ br x1 -+1: -+ wfe -+ b poll_mailbox -+#else - cb_panic: - b cb_panic -+#endif -+ - endfunc plat_secondary_cold_boot_setup - - /* --------------------------------------------------------------------- -diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c -index a52e945bf..979243317 100644 ---- a/plat/arm/board/corstone1000/common/corstone1000_pm.c -+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c -@@ -33,10 +33,51 @@ static void __dead2 corstone1000_system_reset(void) - wfi(); - } - } -+#if defined(CORSTONE1000_FVP_MULTICORE) -+int corstone1000_validate_ns_entrypoint(uintptr_t entrypoint) -+{ -+ /* -+ * Check if the non secure entrypoint lies within the non -+ * secure DRAM. -+ */ -+ if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { -+ return PSCI_E_SUCCESS; -+ } -+ return PSCI_E_INVALID_ADDRESS; -+} -+ -+int corstone1000_pwr_domain_on(u_register_t mpidr) -+{ -+ int core_index = plat_core_pos_by_mpidr(mpidr); -+ uint64_t *secondary_core_hold_base = (uint64_t *)CORSTONE1000_SECONDARY_CORE_HOLD_BASE; - -+ /* Validate the core index */ -+ if ((core_index < 0) || (core_index > PLATFORM_CORE_COUNT)) { -+ return PSCI_E_INVALID_PARAMS; -+ } -+ secondary_core_hold_base[core_index] = CORSTONE1000_SECONDARY_CORE_STATE_GO; -+ dsbish(); -+ sev(); -+ -+ return PSCI_E_SUCCESS; -+} -+ -+void corstone1000_pwr_domain_on_finish(const psci_power_state_t *target_state) -+{ -+ (void)target_state; -+ plat_arm_gic_init(); -+} -+#endif - plat_psci_ops_t plat_arm_psci_pm_ops = { -+#if defined(CORSTONE1000_FVP_MULTICORE) -+ .pwr_domain_on = corstone1000_pwr_domain_on, -+ .pwr_domain_on_finish = corstone1000_pwr_domain_on_finish, -+ .validate_ns_entrypoint = corstone1000_validate_ns_entrypoint, -+ .system_reset = corstone1000_system_reset, -+#else -+ .validate_ns_entrypoint = NULL, - .system_reset = corstone1000_system_reset, -- .validate_ns_entrypoint = NULL -+#endif - }; - - const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) -diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h -index b9a1d43df..c4839ccf3 100644 ---- a/plat/arm/board/corstone1000/common/include/platform_def.h -+++ b/plat/arm/board/corstone1000/common/include/platform_def.h -@@ -249,7 +249,20 @@ - */ - #define ARM_LOCAL_STATE_OFF U(2) - --#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE -+#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE -+ -+#if defined(CORSTONE1000_FVP_MULTICORE) -+/* The secondary core entrypoint address points to bl31_warm_entrypoint -+ * and the address size is 8 bytes */ -+#define CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE UL(0x8) -+ -+#define CORSTONE1000_SECONDARY_CORE_HOLD_BASE (PLAT_ARM_TRUSTED_MAILBOX_BASE + \ -+ CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE) -+#define CORSTONE1000_SECONDARY_CORE_STATE_WAIT ULL(0) -+#define CORSTONE1000_SECONDARY_CORE_STATE_GO ULL(1) -+#define CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT ULL(3) -+#endif -+ - #define PLAT_ARM_NSTIMER_FRAME_ID U(1) - - #define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE) -diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk -index fd08803e8..45092ace9 100644 ---- a/plat/arm/board/corstone1000/platform.mk -+++ b/plat/arm/board/corstone1000/platform.mk -@@ -31,6 +31,13 @@ override NEED_BL31 := yes - NEED_BL32 ?= yes - override NEED_BL33 := yes - -+ENABLE_MULTICORE := 0 -+ifneq ($(filter ${TARGET_PLATFORM}, fvp),) -+ifeq (${ENABLE_MULTICORE},1) -+$(eval $(call add_define,CORSTONE1000_FVP_MULTICORE)) -+endif -+endif -+ - # Add CORSTONE1000_WITH_BL32 as a preprocessor define (-D option) - ifeq (${NEED_BL32},yes) - $(eval $(call add_define,CORSTONE1000_WITH_BL32)) --- -2.25.1 - diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-include-platform-header-file.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-include-platform-header-file.patch deleted file mode 100644 index 13310143..00000000 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-include-platform-header-file.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 8070bf4a89492727b6da3fb7bdec61748eae1d7d Mon Sep 17 00:00:00 2001 -From: Harsimran Singh Tungal -Date: Tue, 2 Jul 2024 12:49:12 +0000 -Subject: [PATCH] fix(corstone1000): include platform header file - -Include platform.h file in order to remove compiler warnings - -Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/29727] -Signed-off-by: Harsimran Singh Tungal ---- - plat/arm/board/corstone1000/common/corstone1000_pm.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c -index 979243317..9babe5b11 100644 ---- a/plat/arm/board/corstone1000/common/corstone1000_pm.c -+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - /******************************************************************************* - * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard - * platform layer will take care of registering the handlers with PSCI. --- -2.34.1 - diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc index 5e41ab6e..97a9e55b 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc @@ -5,11 +5,6 @@ COMPATIBLE_MACHINE = "(corstone1000)" FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:" SRC_URI:append = " \ file://0001-Fix-FF-A-version-in-SPMC-manifest.patch \ - file://0002-fix-corstone1000-pass-spsr-value-explicitly.patch \ - file://0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch \ - file://0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch \ - file://0005-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch \ - file://0006-feat-corstone1000-include-platform-header-file.patch \ " TFA_DEBUG = "1" diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.11.0.bb b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.11.0.bb deleted file mode 100644 index d4dd8c2a..00000000 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.11.0.bb +++ /dev/null @@ -1,20 +0,0 @@ -require recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc - -# TF-A v2.11.0 -SRCREV_tfa = "f2735ebccf5173f74c0458736ec526276106097e" -SRCBRANCH = "master" - -LIC_FILES_CHKSUM += "file://docs/license.rst;md5=b5fbfdeb6855162dded31fadcd5d4dc5" - -# in TF-A src, docs/getting_started/prerequisites.rst lists the expected version mbedtls -# mbedtls-3.6.0 -SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls;branch=main" -SRCREV_mbedtls = "2ca6c285a0dd3f33982dd57299012dacab1ff206" - -LIC_FILES_CHKSUM_MBEDTLS = "file://mbedtls/LICENSE;md5=379d5819937a6c2f1ef1630d341e026d" - -# continue to boot also without TPM -SRC_URI += "\ - file://0001-qemu_measured_boot.c-ignore-TPM-error-and-continue-w.patch \ - file://0001-fix-zynqmp-handle-secure-SGI-at-EL1-for-OP-TEE.patch \ -"