From patchwork Tue Jun 18 15:27:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: harsimransingh.tungal@arm.com X-Patchwork-Id: 45315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FA8BC27C4F for ; Tue, 18 Jun 2024 15:27:44 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.89534.1718724453958392489 for ; Tue, 18 Jun 2024 08:27:34 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: harsimransingh.tungal@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2DC4FDA7; Tue, 18 Jun 2024 08:27:58 -0700 (PDT) Received: from e132995.cambridge.arm.com (e132995.arm.com [10.1.30.21]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A9A0A3F6A8; Tue, 18 Jun 2024 08:27:32 -0700 (PDT) From: harsimransingh.tungal@arm.com To: meta-arm@lists.yoctoproject.org Cc: Harsimran Singh Tungal Subject: [PATCH v2 1/5] arm-bsp/optee: corstone1000: Remove MMCOMM buffer address Date: Tue, 18 Jun 2024 16:27:20 +0100 Message-Id: <20240618152724.7273-2-harsimransingh.tungal@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240618152724.7273-1-harsimransingh.tungal@arm.com> References: <20240618152724.7273-1-harsimransingh.tungal@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jun 2024 15:27:44 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/5820 From: Harsimran Singh Tungal Remove MMCOMM buffer address and its mapping, as it is not being used anymore Signed-off-by: Harsimran Singh Tungal --- ...one1000-Remove-MMCOMM-buffer-address.patch | 43 +++++++++++++++++++ .../optee/optee-os-corstone1000-common.inc | 1 + 2 files changed, 44 insertions(+) create mode 100644 meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0003-plat-corstone1000-Remove-MMCOMM-buffer-address.patch diff --git a/meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0003-plat-corstone1000-Remove-MMCOMM-buffer-address.patch b/meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0003-plat-corstone1000-Remove-MMCOMM-buffer-address.patch new file mode 100644 index 00000000..e493ee1a --- /dev/null +++ b/meta-arm-bsp/recipes-security/optee/files/optee-os/corstone1000/0003-plat-corstone1000-Remove-MMCOMM-buffer-address.patch @@ -0,0 +1,43 @@ +From 2fadadf1075c95b2955f047fa0387b39612f7b30 Mon Sep 17 00:00:00 2001 +From: Harsimran Singh Tungal +Date: Thu, 30 May 2024 13:37:38 +0000 +Subject: [PATCH] plat-corstone1000: Remove MMCOMM buffer address + +Remove MMCOMM buffer address and mapping, as it is not being used anymore + +Upstream-Status: Backport [In v3, https://github.com/OP-TEE/optee_os/commit/eaee88fbcac6dcc15fe1d1a758b53eb2b66cfc60] +Signed-off-by: Harsimran Singh Tungal +--- + core/arch/arm/plat-corstone1000/main.c | 1 - + core/arch/arm/plat-corstone1000/platform_config.h | 3 --- + 2 files changed, 4 deletions(-) + +diff --git a/core/arch/arm/plat-corstone1000/main.c b/core/arch/arm/plat-corstone1000/main.c +index b3861c4c8..61171b9a9 100644 +--- a/core/arch/arm/plat-corstone1000/main.c ++++ b/core/arch/arm/plat-corstone1000/main.c +@@ -15,7 +15,6 @@ + static struct pl011_data console_data __nex_bss; + + register_ddr(DRAM0_BASE, DRAM0_SIZE); +-register_ddr(MM_COMM_BUF_BASE, MM_COMM_BUF_SIZE); + + register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); + register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); +diff --git a/core/arch/arm/plat-corstone1000/platform_config.h b/core/arch/arm/plat-corstone1000/platform_config.h +index 6653d38bc..f59c93a14 100644 +--- a/core/arch/arm/plat-corstone1000/platform_config.h ++++ b/core/arch/arm/plat-corstone1000/platform_config.h +@@ -26,9 +26,6 @@ + #define GICD_BASE (GIC_BASE + GICD_OFFSET) + #define GICC_BASE (GIC_BASE + GICC_OFFSET) + +-#define MM_COMM_BUF_BASE 0x02000000 +-#define MM_COMM_BUF_SIZE 0x1000 +- + #define UART_BAUDRATE 115200 + #define CONSOLE_BAUDRATE UART_BAUDRATE + +-- +2.34.1 + diff --git a/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc b/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc index 260abc05..4f4ed12a 100644 --- a/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc +++ b/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc @@ -2,6 +2,7 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files/optee-os/corstone1000:" SRC_URI:append = " \ file://0001-Handle-logging-syscall.patch \ file://0002-increase-tzdram-size.patch \ + file://0003-plat-corstone1000-Remove-MMCOMM-buffer-address.patch \ " COMPATIBLE_MACHINE = "corstone1000" From patchwork Tue Jun 18 15:27:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: harsimransingh.tungal@arm.com X-Patchwork-Id: 45314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 255A9C2BB85 for ; Tue, 18 Jun 2024 15:27:44 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.89282.1718724455685529124 for ; Tue, 18 Jun 2024 08:27:35 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: harsimransingh.tungal@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E3216DA7; Tue, 18 Jun 2024 08:27:59 -0700 (PDT) Received: from e132995.cambridge.arm.com (e132995.arm.com [10.1.30.21]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 837DA3F6A8; Tue, 18 Jun 2024 08:27:34 -0700 (PDT) From: harsimransingh.tungal@arm.com To: meta-arm@lists.yoctoproject.org Cc: Harsimran Singh Tungal Subject: [PATCH v2 2/5] arm-bsp/u-boot: corstone1000: Enable secondary cores for Corstone-1000 FVP Date: Tue, 18 Jun 2024 16:27:21 +0100 Message-Id: <20240618152724.7273-3-harsimransingh.tungal@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240618152724.7273-1-harsimransingh.tungal@arm.com> References: <20240618152724.7273-1-harsimransingh.tungal@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jun 2024 15:27:44 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/5821 From: Harsimran Singh Tungal This changeset adds secondary cpu nodes for Corstone-1000 FVP dts. Signed-off-by: Harsimran Singh Tungal --- .../u-boot/u-boot-corstone1000.inc | 1 + ...dd-secondary-cores-cpu-nodes-for-FVP.patch | 63 +++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0049-corstone1000-Add-secondary-cores-cpu-nodes-for-FVP.patch diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot-corstone1000.inc b/meta-arm-bsp/recipes-bsp/u-boot/u-boot-corstone1000.inc index 82049c43..7d8155d4 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot-corstone1000.inc @@ -64,6 +64,7 @@ SRC_URI:append = " \ file://0046-Corstone1000-Change-MMCOMM-buffer-location.patch \ file://0047-corstone1000-dts-add-external-system-node.patch \ file://0048-corstone1000-Enable-UEFI-Secure-boot.patch \ + file://0049-corstone1000-Add-secondary-cores-cpu-nodes-for-FVP.patch \ " do_configure:append() { diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0049-corstone1000-Add-secondary-cores-cpu-nodes-for-FVP.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0049-corstone1000-Add-secondary-cores-cpu-nodes-for-FVP.patch new file mode 100644 index 00000000..0e90f577 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0049-corstone1000-Add-secondary-cores-cpu-nodes-for-FVP.patch @@ -0,0 +1,63 @@ +From 68708d6b4953f58a0484b9a83efa8318747cea80 Mon Sep 17 00:00:00 2001 +From: Harsimran Singh Tungal +Date: Thu, 9 May 2024 14:16:55 +0000 +Subject: [PATCH] arm: dts: corstone1000: enable secondary cores for FVP + +Add the secondary cores nodes in the dts file + +Upstream-Status: Submitted [https://lore.kernel.org/all/20240612100421.47938-1-harsimransingh.tungal@arm.com/] +Signed-off-by: Harsimran Singh Tungal +--- + arch/arm/dts/corstone1000-fvp.dts | 25 +++++++++++++++++++++++++ + arch/arm/dts/corstone1000.dtsi | 2 +- + 2 files changed, 26 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts +index 26b0f1b3ce..3076fb9f34 100644 +--- a/arch/arm/dts/corstone1000-fvp.dts ++++ b/arch/arm/dts/corstone1000-fvp.dts +@@ -49,3 +49,28 @@ + clock-names = "smclk", "apb_pclk"; + }; + }; ++ ++&cpus { ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a35"; ++ reg = <0x1>; ++ enable-method = "psci"; ++ next-level-cache = <&L2_0>; ++ }; ++ cpu2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a35"; ++ reg = <0x2>; ++ enable-method = "psci"; ++ next-level-cache = <&L2_0>; ++ }; ++ cpu3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a35"; ++ reg = <0x3>; ++ enable-method = "psci"; ++ next-level-cache = <&L2_0>; ++ }; ++}; ++ +diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi +index 1e0ec075e4..5d9d95b21c 100644 +--- a/arch/arm/dts/corstone1000.dtsi ++++ b/arch/arm/dts/corstone1000.dtsi +@@ -21,7 +21,7 @@ + stdout-path = "serial0:115200n8"; + }; + +- cpus { ++ cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + +-- +2.25.1 + From patchwork Tue Jun 18 15:27:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: harsimransingh.tungal@arm.com X-Patchwork-Id: 45317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B32FC2BA18 for ; Tue, 18 Jun 2024 15:27:44 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.89536.1718724457325582576 for ; Tue, 18 Jun 2024 08:27:37 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: harsimransingh.tungal@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A3410DA7; Tue, 18 Jun 2024 08:28:01 -0700 (PDT) Received: from e132995.cambridge.arm.com (e132995.arm.com [10.1.30.21]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 313013F6A8; Tue, 18 Jun 2024 08:27:36 -0700 (PDT) From: harsimransingh.tungal@arm.com To: meta-arm@lists.yoctoproject.org Cc: Harsimran Singh Tungal Subject: [PATCH v2 3/5] arm-bsp/trusted-firmware-a: corstone1000: Multicore support for Corstone-1000 FVP Date: Tue, 18 Jun 2024 16:27:22 +0100 Message-Id: <20240618152724.7273-4-harsimransingh.tungal@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240618152724.7273-1-harsimransingh.tungal@arm.com> References: <20240618152724.7273-1-harsimransingh.tungal@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jun 2024 15:27:44 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/5822 From: Harsimran Singh Tungal This changeset adds the multicore support in trusted-firmware-a for the Corstone-1000 FVP. Signed-off-by: Harsimran Singh Tungal --- ...0-Add-multicore-support-for-FVP-plat.patch | 162 ++++++++++++++++++ .../trusted-firmware-a-corstone1000.inc | 1 + 2 files changed, 163 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch new file mode 100644 index 00000000..34630442 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch @@ -0,0 +1,162 @@ +From bd975fbcff8886b3d3ed3268d7b6fa41bd7fba2d Mon Sep 17 00:00:00 2001 +From: Harsimran Singh Tungal +Date: Thu, 9 May 2024 16:59:34 +0000 +Subject: [PATCH] feat(corstone1000): add multicore support for fvp + +This changeset adds the multicore support for the Corstone-1000 FVP. +It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities +for the secondary cores. + +Upstream-Status: Backport [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/29176] +Signed-off-by: Harsimran Singh Tungal +--- + .../common/corstone1000_helpers.S | 26 +++++++++++ + .../corstone1000/common/corstone1000_pm.c | 43 ++++++++++++++++++- + .../common/include/platform_def.h | 15 ++++++- + plat/arm/board/corstone1000/platform.mk | 8 ++++ + 4 files changed, 90 insertions(+), 2 deletions(-) + +diff --git a/plat/arm/board/corstone1000/common/corstone1000_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S +index cbe27c3b5..90dc4fee6 100644 +--- a/plat/arm/board/corstone1000/common/corstone1000_helpers.S ++++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S +@@ -21,8 +21,34 @@ + * -------------------------------------------------------------------- + */ + func plat_secondary_cold_boot_setup ++#if defined(CORSTONE1000_FVP_MULTICORE) ++ ++ /* Calculate the address of our hold entry */ ++ bl plat_my_core_pos ++ lsl x0, x0, #CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT ++ mov_imm x2, CORSTONE1000_SECONDARY_CORE_HOLD_BASE ++ ++ /* Set the wait state for the secondary core */ ++ mov_imm x3, CORSTONE1000_SECONDARY_CORE_STATE_WAIT ++ str x3, [x2, x0] ++ dmb ish ++ ++ /* Poll until the primary core signals to go */ ++poll_mailbox: ++ ldr x1, [x2, x0] ++ cmp x1, #CORSTONE1000_SECONDARY_CORE_STATE_WAIT ++ beq 1f ++ mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE ++ ldr x1, [x0] ++ br x1 ++1: ++ wfe ++ b poll_mailbox ++#else + cb_panic: + b cb_panic ++#endif ++ + endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- +diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c +index 4b0a791e7..9cd384e18 100644 +--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c ++++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c +@@ -24,10 +24,51 @@ static void __dead2 corstone1000_system_reset(void) + wfi(); + } + } ++#if defined(CORSTONE1000_FVP_MULTICORE) ++int corstone1000_validate_ns_entrypoint(uintptr_t entrypoint) ++{ ++ /* ++ * Check if the non secure entrypoint lies within the non ++ * secure DRAM. ++ */ ++ if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { ++ return PSCI_E_SUCCESS; ++ } ++ return PSCI_E_INVALID_ADDRESS; ++} ++ ++int corstone1000_pwr_domain_on(u_register_t mpidr) ++{ ++ int core_index = plat_core_pos_by_mpidr(mpidr); ++ uint64_t *secondary_core_hold_base = (uint64_t *)CORSTONE1000_SECONDARY_CORE_HOLD_BASE; ++ ++ /* Validate the core index */ ++ if ((core_index < 0) || (core_index > PLATFORM_CORE_COUNT)) { ++ return PSCI_E_INVALID_PARAMS; ++ } ++ secondary_core_hold_base[core_index] = CORSTONE1000_SECONDARY_CORE_STATE_GO; ++ dsbish(); ++ sev(); ++ ++ return PSCI_E_SUCCESS; ++} + ++void corstone1000_pwr_domain_on_finish(const psci_power_state_t *target_state) ++{ ++ (void)target_state; ++ plat_arm_gic_init(); ++} ++#endif + plat_psci_ops_t plat_arm_psci_pm_ops = { ++#if defined(CORSTONE1000_FVP_MULTICORE) ++ .pwr_domain_on = corstone1000_pwr_domain_on, ++ .pwr_domain_on_finish = corstone1000_pwr_domain_on_finish, ++ .validate_ns_entrypoint = corstone1000_validate_ns_entrypoint, ++ .system_reset = corstone1000_system_reset, ++#else ++ .validate_ns_entrypoint = NULL, + .system_reset = corstone1000_system_reset, +- .validate_ns_entrypoint = NULL ++#endif + }; + + const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) +diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h +index 35bb6ad5c..56e124f96 100644 +--- a/plat/arm/board/corstone1000/common/include/platform_def.h ++++ b/plat/arm/board/corstone1000/common/include/platform_def.h +@@ -251,7 +251,20 @@ + */ + #define ARM_LOCAL_STATE_OFF U(2) + +-#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE ++#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE ++ ++#if defined(CORSTONE1000_FVP_MULTICORE) ++/* The secondary core entrypoint address points to bl31_warm_entrypoint ++ * and the address size is 8 bytes */ ++#define CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE UL(0x8) ++ ++#define CORSTONE1000_SECONDARY_CORE_HOLD_BASE (PLAT_ARM_TRUSTED_MAILBOX_BASE + \ ++ CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE) ++#define CORSTONE1000_SECONDARY_CORE_STATE_WAIT ULL(0) ++#define CORSTONE1000_SECONDARY_CORE_STATE_GO ULL(1) ++#define CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT ULL(3) ++#endif ++ + #define PLAT_ARM_NSTIMER_FRAME_ID U(1) + + #define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE) +diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk +index dcd0df844..71b7f324c 100644 +--- a/plat/arm/board/corstone1000/platform.mk ++++ b/plat/arm/board/corstone1000/platform.mk +@@ -31,6 +31,14 @@ override NEED_BL31 := yes + NEED_BL32 := yes + override NEED_BL33 := yes + ++ENABLE_MULTICORE := 0 ++ifneq ($(filter ${TARGET_PLATFORM}, fvp),) ++ifeq (${ENABLE_MULTICORE},1) ++$(eval $(call add_define,CORSTONE1000_FVP_MULTICORE)) ++endif ++endif ++ ++ + # Include GICv2 driver files + include drivers/arm/gic/v2/gicv2.mk + +-- +2.34.1 + diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc index f5737ca4..b19e52aa 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc @@ -9,6 +9,7 @@ SRC_URI:append = " \ file://0003-fix-spmd-remove-EL3-interrupt-registration.patch \ file://0004-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch \ file://0005-fix-corstone1000-clean-the-cache-and-disable-interru.patch \ + file://0006-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch \ " TFA_DEBUG = "1" From patchwork Tue Jun 18 15:27:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: harsimransingh.tungal@arm.com X-Patchwork-Id: 45318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CF13C41513 for ; Tue, 18 Jun 2024 15:27:44 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.89284.1718724459185191049 for ; Tue, 18 Jun 2024 08:27:39 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: harsimransingh.tungal@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 95F7EDA7; Tue, 18 Jun 2024 08:28:03 -0700 (PDT) Received: from e132995.cambridge.arm.com (e132995.arm.com [10.1.30.21]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1DCC33F6A8; Tue, 18 Jun 2024 08:27:37 -0700 (PDT) From: harsimransingh.tungal@arm.com To: meta-arm@lists.yoctoproject.org Cc: Harsimran Singh Tungal Subject: [PATCH v2 4/5] arm-bsp/trusted-firmware-m: corstone1000: Multicore support for Corstone-1000 FVP Date: Tue, 18 Jun 2024 16:27:23 +0100 Message-Id: <20240618152724.7273-5-harsimransingh.tungal@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240618152724.7273-1-harsimransingh.tungal@arm.com> References: <20240618152724.7273-1-harsimransingh.tungal@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jun 2024 15:27:44 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/5823 From: Harsimran Singh Tungal This changeset introduces the multicore support for the Corstone-1000 FVP. Signed-off-by: Harsimran Singh Tungal --- ...CS1000-Add-multicore-support-for-FVP.patch | 119 ++++++++++++++++++ .../trusted-firmware-m-corstone1000.inc | 1 + 2 files changed, 120 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0013-platform-CS1000-Add-multicore-support-for-FVP.patch diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0013-platform-CS1000-Add-multicore-support-for-FVP.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0013-platform-CS1000-Add-multicore-support-for-FVP.patch new file mode 100644 index 00000000..9ede5341 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0013-platform-CS1000-Add-multicore-support-for-FVP.patch @@ -0,0 +1,119 @@ +From 1120957e74a1a0727a215188813cab3e47602e71 Mon Sep 17 00:00:00 2001 +From: Harsimran Singh Tungal +Date: Thu, 9 May 2024 13:20:57 +0000 +Subject: [PATCH] platform: CS1000: Add multicore support for FVP + +This changeset adds the support to enable the secondary cores for +the Corstone-1000 FVP + +Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/29242] +Signed-off-by: Harsimran Singh Tungal +--- + .../target/arm/corstone1000/CMakeLists.txt | 6 +++ + .../corstone1000/Device/Config/device_cfg.h | 6 +++ + .../arm/corstone1000/tfm_hal_multi_core.c | 38 ++++++++++++++++++- + 3 files changed, 48 insertions(+), 2 deletions(-) + +diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt +index e2a7ac302..a269251aa 100644 +--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt ++++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt +@@ -374,6 +374,12 @@ target_sources(tfm_psa_rot_partition_ns_agent_mailbox + tfm_hal_multi_core.c + ) + ++if (PLATFORM_IS_FVP) ++target_compile_definitions(tfm_psa_rot_partition_ns_agent_mailbox ++ PUBLIC ++ $<$:CORSTONE1000_FVP_MULTICORE> ++) ++endif() + #========================= tfm_spm ============================================# + + target_sources(tfm_spm +diff --git a/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h b/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h +index 222905d3d..9d48f119e 100644 +--- a/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h ++++ b/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h +@@ -45,5 +45,11 @@ + /* CFI Controller */ + #define CFI_S + ++/* Total number of host cores */ ++#if CORSTONE1000_FVP_MULTICORE ++#define PLATFORM_HOST_MAX_CORE_COUNT 4 ++#else ++#define PLATFORM_HOST_MAX_CORE_COUNT 1 ++#endif + + #endif /* __DEVICE_CFG_H__ */ +diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c +index f0e2bc333..ce72e50c9 100644 +--- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c ++++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c +@@ -11,9 +11,14 @@ + #include "tfm_hal_multi_core.h" + #include "fwu_agent.h" + +-#define HOST_SYS_RST_CTRL_OFFSET 0x0 ++#define HOST_SYS_RST_CTRL_OFFSET 0x000 ++#define HOST_CPU_PE0_CONFIG_OFFSET 0x010 ++#define HOST_CPU_PE1_CONFIG_OFFSET 0x020 ++#define HOST_CPU_PE2_CONFIG_OFFSET 0x030 ++#define HOST_CPU_PE3_CONFIG_OFFSET 0x040 ++#define HOST_CPU_BOOT_MASK_OFFSET 0x300 + #define HOST_CPU_CORE0_WAKEUP_OFFSET 0x308 +-#define HOST_CPU_PE0_CONFIG_OFFSET 0x010 ++ + #define AA64nAA32_MASK (1 << 3) + + #ifdef EXTERNAL_SYSTEM_SUPPORT +@@ -53,9 +58,29 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr) + volatile uint32_t *PE0_CONFIG = + (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE + + HOST_CPU_PE0_CONFIG_OFFSET); ++#if CORSTONE1000_FVP_MULTICORE ++ volatile uint32_t *PE1_CONFIG = ++ (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE ++ + HOST_CPU_PE1_CONFIG_OFFSET); ++ volatile uint32_t *PE2_CONFIG = ++ (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE ++ + HOST_CPU_PE2_CONFIG_OFFSET); ++ volatile uint32_t *PE3_CONFIG = ++ (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE ++ + HOST_CPU_PE3_CONFIG_OFFSET); ++ volatile uint32_t *CPU_BOOT_MASK = ++ (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE ++ + HOST_CPU_BOOT_MASK_OFFSET); + ++ *CPU_BOOT_MASK = 0xf; ++#endif + /* Select host CPU architecture as AArch64 */ + *PE0_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */ ++#if CORSTONE1000_FVP_MULTICORE ++ *PE1_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */ ++ *PE2_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */ ++ *PE3_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */ ++#endif + + /* wakeup CORE0 before bringing it out of reset */ + *reset_ctl_wakeup_reg = 0x1; +@@ -63,6 +88,15 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr) + /* Clear HOST_SYS_RST_CTRL register to bring host out of RESET */ + *reset_ctl_reg = 0; + ++#if CORSTONE1000_FVP_MULTICORE ++ /* Wake up secondary cores. ++ * This should be done after bringing the primary core out of reset. */ ++ for(int core_index=1; core_index < PLATFORM_HOST_MAX_CORE_COUNT; core_index++) ++ { ++ *reset_ctl_wakeup_reg = (0x1 << core_index); ++ } ++#endif ++ + (void) start_addr; + + #ifdef EXTERNAL_SYSTEM_SUPPORT +-- +2.34.1 + diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc index dcba79ef..b362461e 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc @@ -29,6 +29,7 @@ SRC_URI:append:corstone1000 = " \ file://0010-CC312-alignment-of-cc312-differences-between-fvp-and.patch \ file://0011-Platform-corstone1000-Increase-buffers-for-EFI-vars.patch \ file://0012-corstone1000-Remove-reset-after-capsule-update.patch \ + file://0013-platform-CS1000-Add-multicore-support-for-FVP.patch \ " # TF-M ships patches for external dependencies that needs to be applied From patchwork Tue Jun 18 15:27:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: harsimransingh.tungal@arm.com X-Patchwork-Id: 45316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52715C2BBCA for ; Tue, 18 Jun 2024 15:27:44 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.89538.1718724461274516745 for ; Tue, 18 Jun 2024 08:27:41 -0700 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: harsimransingh.tungal@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8899BDA7; Tue, 18 Jun 2024 08:28:05 -0700 (PDT) Received: from e132995.cambridge.arm.com (e132995.arm.com [10.1.30.21]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 109C73F6A8; Tue, 18 Jun 2024 08:27:39 -0700 (PDT) From: harsimransingh.tungal@arm.com To: meta-arm@lists.yoctoproject.org Cc: Harsimran Singh Tungal Subject: [PATCH v2 5/5] ci,arm-bsp: corstone1000: New MACHINE_FEATURES for Corstone-1000 FVP multicore Date: Tue, 18 Jun 2024 16:27:24 +0100 Message-Id: <20240618152724.7273-6-harsimransingh.tungal@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240618152724.7273-1-harsimransingh.tungal@arm.com> References: <20240618152724.7273-1-harsimransingh.tungal@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jun 2024 15:27:44 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/5824 From: Harsimran Singh Tungal Introduce `corstone1000_fvp_smp` as a value of the `MACHINE_FEATURES` variable to support Corstone-1000 FVP Symmetric Multiprocessing. A new YAML file is created to add this new machine only for the FVP variant of the target platform. The multicore feature is enabled in TrustedFirmware-A, TrustedFirmware-M, and OP-TEE based on this machine feature. Signed-off-by: Harsimran Singh Tungal --- kas/corstone1000-fvp-multicore.yml | 8 ++++++++ .../trusted-firmware-a-corstone1000.inc | 1 + .../trusted-firmware-m-corstone1000.inc | 1 + .../optee/optee-os-corstone1000-common.inc | 2 ++ 4 files changed, 12 insertions(+) create mode 100644 kas/corstone1000-fvp-multicore.yml diff --git a/kas/corstone1000-fvp-multicore.yml b/kas/corstone1000-fvp-multicore.yml new file mode 100644 index 00000000..d806bb11 --- /dev/null +++ b/kas/corstone1000-fvp-multicore.yml @@ -0,0 +1,8 @@ +# yaml-language-server: $schema=https://raw.githubusercontent.com/siemens/kas/master/kas/schema-kas.json + +header: + version: 14 + +local_conf_header: + fvp-multicore: | + MACHINE_FEATURES += "corstone1000_fvp_smp" diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc index b19e52aa..c53bc6cd 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc @@ -55,3 +55,4 @@ EXTRA_OEMAKE:append = " \ BL32=${RECIPE_SYSROOT}/${nonarch_base_libdir}/firmware/tee-pager_v2.bin \ FVP_USE_GIC_DRIVER=FVP_GICV2 \ " +EXTRA_OEMAKE:append:corstone1000-fvp = "${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_fvp_smp', ' ENABLE_MULTICORE=1', '', d)}" diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc index b362461e..4777251d 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc @@ -10,6 +10,7 @@ TFM_DEBUG = "1" TFM_PLATFORM_IS_FVP ?= "FALSE" EXTRA_OECMAKE += "-DPLATFORM_IS_FVP=${TFM_PLATFORM_IS_FVP}" EXTRA_OECMAKE += "-DCC312_LEGACY_DRIVER_API_ENABLED=OFF" +EXTRA_OECMAKE:append:corstone1000-fvp = " -DENABLE_MULTICORE=${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_fvp_smp', 'TRUE', 'FALSE', d)}" SRC_URI += " \ file://0001-arm-trusted-firmware-m-disable-address-warnings-into.patch \ diff --git a/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc b/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc index 4f4ed12a..22289087 100644 --- a/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc +++ b/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc @@ -17,3 +17,5 @@ EXTRA_OEMAKE += " CFG_TEE_BENCHMARK=n" EXTRA_OEMAKE += " CFG_CORE_SEL1_SPMC=y CFG_CORE_FFA=y" EXTRA_OEMAKE += " CFG_WITH_SP=y" + +EXTRA_OEMAKE:append:corstone1000-fvp = "${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_fvp_smp', ' CFG_TEE_CORE_NB_CORE=4', '', d)}"