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Mon, 13 May 2024 16:05:30 -0700 (PDT) Received: from apollo.hsd1.ca.comcast.net ([2601:646:9d80:4380::6fff]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0bad9f3asm84998995ad.112.2024.05.13.16.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 16:05:30 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Cc: Khem Raj Subject: [PATCH] openssl: Fix build on riscv Date: Mon, 13 May 2024 16:05:28 -0700 Message-ID: <20240513230528.4115348-1-raj.khem@gmail.com> X-Mailer: git-send-email 2.45.0 MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 13 May 2024 23:05:38 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/199251 GCC-14 unearths this bug which is already fixed upstream so backport it Signed-off-by: Khem Raj --- ...Implement-riscv_vlen_asm-for-riscv32.patch | 43 +++++++++++++++++++ .../openssl/openssl_3.3.0.bb | 1 + 2 files changed, 44 insertions(+) create mode 100644 meta/recipes-connectivity/openssl/openssl/0001-Implement-riscv_vlen_asm-for-riscv32.patch diff --git a/meta/recipes-connectivity/openssl/openssl/0001-Implement-riscv_vlen_asm-for-riscv32.patch b/meta/recipes-connectivity/openssl/openssl/0001-Implement-riscv_vlen_asm-for-riscv32.patch new file mode 100644 index 00000000000..e398d1074a4 --- /dev/null +++ b/meta/recipes-connectivity/openssl/openssl/0001-Implement-riscv_vlen_asm-for-riscv32.patch @@ -0,0 +1,43 @@ +From 725b1530456545e8511adc9cbdd265309dffad53 Mon Sep 17 00:00:00 2001 +From: Hongren Zheng +Date: Fri, 26 Apr 2024 06:03:43 +0000 +Subject: [PATCH] Implement riscv_vlen_asm for riscv32 + +riscvcap.c: undefined reference to 'riscv_vlen_asm' + +Upstream-Status: Backport [https://github.com/openssl/openssl/pull/24270] +Signed-off-by: Khem Raj +--- + crypto/riscv32cpuid.pl | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/crypto/riscv32cpuid.pl b/crypto/riscv32cpuid.pl +index 20694e7..ac1c043 100644 +--- a/crypto/riscv32cpuid.pl ++++ b/crypto/riscv32cpuid.pl +@@ -84,5 +84,22 @@ OPENSSL_cleanse: + ___ + } + ++{ ++my ($ret) = ('a0'); ++$code .= <<___; ++################################################################################ ++# size_t riscv_vlen_asm(void) ++# Return VLEN (i.e. the length of a vector register in bits). ++.p2align 3 ++.globl riscv_vlen_asm ++.type riscv_vlen_asm,\@function ++riscv_vlen_asm: ++ csrr $ret, vlenb ++ slli $ret, $ret, 3 ++ ret ++.size riscv_vlen_asm,.-riscv_vlen_asm ++___ ++} ++ + print $code; + close STDOUT or die "error closing STDOUT: $!"; +-- +2.45.0 + diff --git a/meta/recipes-connectivity/openssl/openssl_3.3.0.bb b/meta/recipes-connectivity/openssl/openssl_3.3.0.bb index d9233b356ad..b800d0de909 100644 --- a/meta/recipes-connectivity/openssl/openssl_3.3.0.bb +++ b/meta/recipes-connectivity/openssl/openssl_3.3.0.bb @@ -12,6 +12,7 @@ SRC_URI = "http://www.openssl.org/source/openssl-${PV}.tar.gz \ file://0001-buildinfo-strip-sysroot-and-debug-prefix-map-from-co.patch \ file://0001-Configure-do-not-tweak-mips-cflags.patch \ file://0001-Added-handshake-history-reporting-when-test-fails.patch \ + file://0001-Implement-riscv_vlen_asm-for-riscv32.patch \ file://bti.patch \ "