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([98.142.47.158]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffaf9e98sm1879168a91.38.2025.01.24.07.57.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2025 07:57:11 -0800 (PST) From: Steve Sakoman To: openembedded-core@lists.openembedded.org Subject: [OE-core][styhead 5/6] rust-target-config: Fix TARGET_C_INT_WIDTH with correct size Date: Fri, 24 Jan 2025 07:56:53 -0800 Message-ID: <2ed3b74eb45802cfa64ec9ab460422e098e975d5.1737734087.git.steve@sakoman.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 24 Jan 2025 15:57:14 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/210232 From: Harish Sadineni [YOCTO #15600] The TARGET_C_INT_WIDTH value was incorrectly set to 64 instead of 32. It is updated for PPC, Mips, and riscv64 architectures. Discussion links for solution: https://lists.openembedded.org/g/openembedded-core/message/207486 https://lists.openembedded.org/g/openembedded-core/message/207496 Signed-off-by: Harish Sadineni Signed-off-by: Richard Purdie (cherry picked from commit b9df8cd8b29064d115dab3bfd1ea14f94a5c0238) Signed-off-by: Steve Sakoman --- meta/classes-recipe/rust-target-config.bbclass | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/meta/classes-recipe/rust-target-config.bbclass b/meta/classes-recipe/rust-target-config.bbclass index 334f2e7d5f..58d2ae2117 100644 --- a/meta/classes-recipe/rust-target-config.bbclass +++ b/meta/classes-recipe/rust-target-config.bbclass @@ -198,7 +198,7 @@ MAX_ATOMIC_WIDTH[mipsel] = "32" DATA_LAYOUT[mips64] = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128" TARGET_ENDIAN[mips64] = "big" TARGET_POINTER_WIDTH[mips64] = "64" -TARGET_C_INT_WIDTH[mips64] = "64" +TARGET_C_INT_WIDTH[mips64] = "32" MAX_ATOMIC_WIDTH[mips64] = "64" ## mips64-n32-unknown-linux-{gnu, musl} @@ -212,7 +212,7 @@ MAX_ATOMIC_WIDTH[mips64-n32] = "64" DATA_LAYOUT[mips64el] = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128" TARGET_ENDIAN[mips64el] = "little" TARGET_POINTER_WIDTH[mips64el] = "64" -TARGET_C_INT_WIDTH[mips64el] = "64" +TARGET_C_INT_WIDTH[mips64el] = "32" MAX_ATOMIC_WIDTH[mips64el] = "64" ## powerpc-unknown-linux-{gnu, musl} @@ -226,14 +226,14 @@ MAX_ATOMIC_WIDTH[powerpc] = "32" DATA_LAYOUT[powerpc64] = "E-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512" TARGET_ENDIAN[powerpc64] = "big" TARGET_POINTER_WIDTH[powerpc64] = "64" -TARGET_C_INT_WIDTH[powerpc64] = "64" +TARGET_C_INT_WIDTH[powerpc64] = "32" MAX_ATOMIC_WIDTH[powerpc64] = "64" ## powerpc64le-unknown-linux-{gnu, musl} DATA_LAYOUT[powerpc64le] = "e-m:e-i64:64-n32:64-v256:256:256-v512:512:512" TARGET_ENDIAN[powerpc64le] = "little" TARGET_POINTER_WIDTH[powerpc64le] = "64" -TARGET_C_INT_WIDTH[powerpc64le] = "64" +TARGET_C_INT_WIDTH[powerpc64le] = "32" MAX_ATOMIC_WIDTH[powerpc64le] = "64" ## riscv32gc-unknown-linux-{gnu, musl} @@ -247,7 +247,7 @@ MAX_ATOMIC_WIDTH[riscv32gc] = "32" DATA_LAYOUT[riscv64gc] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" TARGET_ENDIAN[riscv64gc] = "little" TARGET_POINTER_WIDTH[riscv64gc] = "64" -TARGET_C_INT_WIDTH[riscv64gc] = "64" +TARGET_C_INT_WIDTH[riscv64gc] = "32" MAX_ATOMIC_WIDTH[riscv64gc] = "64" ## loongarch64-unknown-linux-{gnu, musl}