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Wed, 25 Mar 2026 19:09:30 -0700 (PDT) Received: from apollo.localdomain ([208.95.233.74]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12aa6e5b38csm2359060c88.2.2026.03.25.19.09.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2026 19:09:29 -0700 (PDT) From: Khem Raj X-Google-Original-From: Khem Raj To: openembedded-core@lists.openembedded.org Cc: Khem Raj Subject: [PATCH v2 4/4] rust: Fix build with llvm-22 Date: Wed, 25 Mar 2026 19:09:22 -0700 Message-ID: <20260326020923.297511-4-khem.raj@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326020923.297511-1-khem.raj@oss.qualcomm.com> References: <20260326020923.297511-1-khem.raj@oss.qualcomm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from 45-33-107-173.ip.linodeusercontent.com [45.33.107.173] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 26 Mar 2026 02:09:37 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/233944 Backport patch to update data layout for amdgpu Signed-off-by: Khem Raj --- .../0001-Update-amdgpu-data-layout.patch | 44 +++++++++++++++++++ meta/recipes-devtools/rust/rust-source.inc | 1 + 2 files changed, 45 insertions(+) create mode 100644 meta/recipes-devtools/rust/files/0001-Update-amdgpu-data-layout.patch diff --git a/meta/recipes-devtools/rust/files/0001-Update-amdgpu-data-layout.patch b/meta/recipes-devtools/rust/files/0001-Update-amdgpu-data-layout.patch new file mode 100644 index 0000000000..1c09cd8fa6 --- /dev/null +++ b/meta/recipes-devtools/rust/files/0001-Update-amdgpu-data-layout.patch @@ -0,0 +1,44 @@ +From bf3ac98d6930ba4e258cf33240c2fe7c99d19eae Mon Sep 17 00:00:00 2001 +From: Nikita Popov +Date: Tue, 6 Jan 2026 11:51:33 +0100 +Subject: [PATCH] Update amdgpu data layout + +This changed in: +https://github.com/llvm/llvm-project/commit/853760bca6aa7a960b154cef8c61f87271870b8a + +Upstream-Status: Backport [https://github.com/rust-lang/rust/commit/bf3ac98d6930ba4e258cf33240c2fe7c99d19eae] +Signed-off-by: Khem Raj +--- + compiler/rustc_codegen_llvm/src/context.rs | 5 +++++ + compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs | 2 +- + 2 files changed, 6 insertions(+), 1 deletion(-) + +diff --git a/compiler/rustc_codegen_llvm/src/context.rs b/compiler/rustc_codegen_llvm/src/context.rs +index 4b2544b7efd..4328b15c73f 100644 +--- a/compiler/rustc_codegen_llvm/src/context.rs ++++ b/compiler/rustc_codegen_llvm/src/context.rs +@@ -215,6 +215,11 @@ pub(crate) unsafe fn create_module<'ll>( + // LLVM 22 updated the ABI alignment for double on AIX: https://github.com/llvm/llvm-project/pull/144673 + target_data_layout = target_data_layout.replace("-f64:32:64", ""); + } ++ if sess.target.arch == Arch::AmdGpu { ++ // LLVM 22 specified ELF mangling in the amdgpu data layout: ++ // https://github.com/llvm/llvm-project/pull/163011 ++ target_data_layout = target_data_layout.replace("-m:e", ""); ++ } + } + + // Ensure the data-layout values hardcoded remain the defaults. +diff --git a/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs b/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs +index 828d853ac65..d6a2cfc2aab 100644 +--- a/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs ++++ b/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs +@@ -5,7 +5,7 @@ + pub(crate) fn target() -> Target { + Target { + arch: Arch::AmdGpu, +- data_layout: "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9".into(), ++ data_layout: "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9".into(), + llvm_target: "amdgcn-amd-amdhsa".into(), + metadata: TargetMetadata { + description: Some("AMD GPU".into()), diff --git a/meta/recipes-devtools/rust/rust-source.inc b/meta/recipes-devtools/rust/rust-source.inc index 4579b6bf6a..e1942db93d 100644 --- a/meta/recipes-devtools/rust/rust-source.inc +++ b/meta/recipes-devtools/rust/rust-source.inc @@ -8,6 +8,7 @@ SRC_URI += "https://static.rust-lang.org/dist/rustc-${RUST_VERSION}-src.tar.xz;n file://0001-riscv32-Define-plain-syscalls-as-their-time64-varian.patch;patchdir=${RUSTSRC} \ file://0001-Update-call-llvm-intrinsics-test.patch;patchdir=${RUSTSRC} \ file://0001-Fix-flaky-assertions-in-oneshot-tests.patch;patchdir=${RUSTSRC} \ + file://0001-Update-amdgpu-data-layout.patch;patchdir=${RUSTSRC} \ " SRC_URI[rust.sha256sum] = "0b53ae34f5c0c3612cfe1de139f9167a018cd5737bc2205664fd69ba9b25f600"