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Sun, 24 Nov 2024 09:59:39 -0800 (PST) Received: from apollo.hsd1.ca.comcast.net ([2601:646:8201:fd20::4338]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-724ea6a23a4sm4035357b3a.60.2024.11.24.09.59.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 09:59:38 -0800 (PST) From: Khem Raj To: openembedded-core@lists.openembedded.org Cc: Khem Raj Subject: [PATCH] qemu: Fix build on riscv64 Date: Sun, 24 Nov 2024 09:59:35 -0800 Message-ID: <20241124175936.3682310-1-raj.khem@gmail.com> X-Mailer: git-send-email 2.47.0 MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Sun, 24 Nov 2024 17:59:48 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/207712 Signed-off-by: Khem Raj --- meta/recipes-devtools/qemu/qemu.inc | 1 + ...o-riscv.c-fix-riscv64-build-on-musl-.patch | 41 +++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 meta/recipes-devtools/qemu/qemu/0001-util-util-cpuinfo-riscv.c-fix-riscv64-build-on-musl-.patch diff --git a/meta/recipes-devtools/qemu/qemu.inc b/meta/recipes-devtools/qemu/qemu.inc index 02cd7c8dc8f..041a24e711c 100644 --- a/meta/recipes-devtools/qemu/qemu.inc +++ b/meta/recipes-devtools/qemu/qemu.inc @@ -33,6 +33,7 @@ SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \ file://0010-configure-lookup-meson-exutable-from-PATH.patch \ file://0011-qemu-Ensure-pip-and-the-python-venv-aren-t-used-for-.patch \ file://0001-sched_attr-Do-not-define-for-glibc-2.41.patch \ + file://0001-util-util-cpuinfo-riscv.c-fix-riscv64-build-on-musl-.patch \ file://qemu-guest-agent.init \ file://qemu-guest-agent.udev \ " diff --git a/meta/recipes-devtools/qemu/qemu/0001-util-util-cpuinfo-riscv.c-fix-riscv64-build-on-musl-.patch b/meta/recipes-devtools/qemu/qemu/0001-util-util-cpuinfo-riscv.c-fix-riscv64-build-on-musl-.patch new file mode 100644 index 00000000000..16762e033eb --- /dev/null +++ b/meta/recipes-devtools/qemu/qemu/0001-util-util-cpuinfo-riscv.c-fix-riscv64-build-on-musl-.patch @@ -0,0 +1,41 @@ +From f60ea4ae2298f0f077a97648c138283357337370 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Milan=20P=2E=20Stani=C4=87?= +Date: Thu, 5 Sep 2024 16:17:50 +0200 +Subject: [PATCH] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +build fails on musl libc (alpine linux) with this error: + +../util/cpuinfo-riscv.c: In function 'cpuinfo_init': +../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe' undeclared (first use in this function); did you mean 'riscv_hwprobe'? + 63 | if (syscall(__NR_riscv_hwprobe, &pair, 1, 0, NULL, 0) == 0 + | ^~~~~~~~~~~~~~~~~~ + | riscv_hwprobe +../util/cpuinfo-riscv.c:63:21: note: each undeclared identifier is reported only once for each function it appears in +ninja: subcommand failed + +add '#include "asm/unistd.h"' to util/cpuinfo-riscv.c fixes build + +Upstream-Status: Backport [https://github.com/qemu/qemu/commit/c5757f808bd74db7ef1a90ee28334f3b5afb8179] +Signed-off-by: Milan P. Stanić +--- + util/cpuinfo-riscv.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c +index 497ce12680..8cacc67645 100644 +--- a/util/cpuinfo-riscv.c ++++ b/util/cpuinfo-riscv.c +@@ -9,6 +9,7 @@ + #ifdef CONFIG_ASM_HWPROBE_H + #include + #include ++#include + #endif + + unsigned cpuinfo; +-- +2.46.0 +