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Fri, 13 Sep 2024 09:21:53 +0000 From: Qi.Chen@windriver.com To: openembedded-core@lists.openembedded.org Subject: [OE-core][scarthgap][PATCH] qemu: back port patches to fix riscv64 build failure Date: Fri, 13 Sep 2024 02:21:36 -0700 Message-Id: <20240913092136.2273686-1-Qi.Chen@windriver.com> X-Mailer: git-send-email 2.25.1 X-ClientProxiedBy: SJ0PR13CA0080.namprd13.prod.outlook.com (2603:10b6:a03:2c4::25) To CO6PR11MB5602.namprd11.prod.outlook.com (2603:10b6:303:13a::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO6PR11MB5602:EE_|DM4PR11MB6525:EE_ X-MS-Office365-Filtering-Correlation-Id: bfdb3fdb-ca43-46ad-52be-08dcd3d57ec6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|52116014|366016|38350700014; X-Microsoft-Antispam-Message-Info: 14yBDFw11ryvSKmNWPTP98z2RQ1MMs2h6tGeA90hffkvkMD3fo5UZVIxc+yl19q0sdzoWn9yNQNomaG2WguUORoph36qDA5tS2XSPfw5YEBqddVxFF9B0sahnBXhBnwXOg4QWFnZisUbR9Uueh4/H0JgkMPWxpgk/euDr9hlgNJXboUoxzgifzfIHfgv4LbOXoxeMrb6+uFx3EizaJ3L6sZEl88+dmfbEjp718KNi2gkhY23fEJPjHjHf/to5l+QXDCFTXX/JvuNnRiOdzix9xYawdIm3k2ZXRoC8YHw6xW1FXk5BaSH6FrgU5QM2uFURYi4OEkEi3zR2txOE+IHRNDjQZVwjUyGstFVetrqq2Cck+awvCWiE+ZC+124Qa4dAKSC6PhA8I2rWKsYPu9DsSMHXIle4wufjm3fzxPVx6MEneMaFkTOBBCZYkk6ECYsh77J5jushFeD7ZrtP+KBkj0rApgSe4RnJjUGHLBra9jwJbVbkf8cfSHsMSzeK9Bd92OShNPb7aoi/GY3+VpGSx6vAZUjLeoj+utBMsJHFpofe5MifJnEZnFDMPE1E4Ju97Pl8XURB+G+hQsDeS2pBZGccUzUdpokXeZrms197QaoAL5qlncKTQcdBt7Ae+W78GXgN4NfXZCApTDrgC9L8jVzVBr/p9fpS/QY5EMzidapgzUXgXgV6WoeyrVff5qVqNYFN1S4VHZpGYkPUXLaMHLa2IgSWLgEvTRO81gliR7d1Q9HPBYS/RflJYrtTxXJDg2F+rS85kWgTzmZkp2umBa8gA5iRoyPMHQRw2+XiYpONsvFnAZfaZGUYvYarN0SoIxbZxgfq4+MntElHY+KhAsr/To8YcapB0uCQfOvPXTx7gSFQ6WYkhA9vq6LM9XQ61zxk+xT3HdjvBIrWiFwEPWoERqjWZ+RpXEmqMWkQQYToKEjgOx4GeQiXVLas62u7AOVbKNT9ovg+GryzNvMIEyhdlQA69oZIW/PXKo4sHHezT6MtLPgkkqJQne8OJM/WjIK7CgFuTfkmfvlP/4pKYFdtkBBNCq91STPTE/ca3UmKrd9WZYi1HhLRqlofv9kJQFNYl7dEf8O/A1ZRimP2YjnEMjxCcHqVbmKdSyyX25SS2GDX7u27/vdZohgDQ2NnV9gny+LjHtYNCNmtPZLmh1DtJQepP2l5HNpj5w3jcE8hTP2Em/NQcpGZDdCZRVGOfdDoNLtU3uzDOvDRdtiaPEJgy9VM7ykHzcX7bZV4VhoPrnPzk3On51YRPPYWAeaPXdDSDLpm3wD4i1DhVfn0Bv/CddIt54gC8vrGBOcYte15TtQzIq4B6CKxY2hpV196VLGtQ6zn+7tiDNiwExBH0tJz3VMnu7PGkvRwHV8A1g= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CO6PR11MB5602.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(52116014)(366016)(38350700014);DIR:OUT;SFP:1101; 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Fri, 13 Sep 2024 09:21:59 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/204475 From: Chen Qi Backport patches to fix riscv64 build failure. Signed-off-by: Chen Qi --- meta/recipes-devtools/qemu/qemu.inc | 3 + ...kvm-change-KVM_REG_RISCV_FP_F-to-u32.patch | 75 ++++++++++++ ...kvm-change-KVM_REG_RISCV_FP_D-to-u64.patch | 73 ++++++++++++ ...cv-kvm-change-timer-regs-size-to-u64.patch | 107 ++++++++++++++++++ 4 files changed, 258 insertions(+) create mode 100644 meta/recipes-devtools/qemu/qemu/0001-target-riscv-kvm-change-KVM_REG_RISCV_FP_F-to-u32.patch create mode 100644 meta/recipes-devtools/qemu/qemu/0002-target-riscv-kvm-change-KVM_REG_RISCV_FP_D-to-u64.patch create mode 100644 meta/recipes-devtools/qemu/qemu/0003-target-riscv-kvm-change-timer-regs-size-to-u64.patch diff --git a/meta/recipes-devtools/qemu/qemu.inc b/meta/recipes-devtools/qemu/qemu.inc index a1d8a309a0..e9f63b9eaf 100644 --- a/meta/recipes-devtools/qemu/qemu.inc +++ b/meta/recipes-devtools/qemu/qemu.inc @@ -49,6 +49,9 @@ SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \ file://CVE-2024-7409-0002.patch \ file://CVE-2024-7409-0003.patch \ file://CVE-2024-7409-0004.patch \ + file://0001-target-riscv-kvm-change-KVM_REG_RISCV_FP_F-to-u32.patch \ + file://0002-target-riscv-kvm-change-KVM_REG_RISCV_FP_D-to-u64.patch \ + file://0003-target-riscv-kvm-change-timer-regs-size-to-u64.patch \ " UPSTREAM_CHECK_REGEX = "qemu-(?P\d+(\.\d+)+)\.tar" diff --git a/meta/recipes-devtools/qemu/qemu/0001-target-riscv-kvm-change-KVM_REG_RISCV_FP_F-to-u32.patch b/meta/recipes-devtools/qemu/qemu/0001-target-riscv-kvm-change-KVM_REG_RISCV_FP_F-to-u32.patch new file mode 100644 index 0000000000..39a6a85162 --- /dev/null +++ b/meta/recipes-devtools/qemu/qemu/0001-target-riscv-kvm-change-KVM_REG_RISCV_FP_F-to-u32.patch @@ -0,0 +1,75 @@ +From bbdcc89678daa5cb131ef22a6cd41a5f7f9dcea9 Mon Sep 17 00:00:00 2001 +From: Daniel Henrique Barboza +Date: Fri, 8 Dec 2023 15:38:31 -0300 +Subject: [PATCH 1/3] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 + +KVM_REG_RISCV_FP_F regs have u32 size according to the API, but by using +kvm_riscv_reg_id() in RISCV_FP_F_REG() we're returning u64 sizes when +running with TARGET_RISCV64. The most likely reason why no one noticed +this is because we're not implementing kvm_cpu_synchronize_state() in +RISC-V yet. + +Create a new helper that returns a KVM ID with u32 size and use it in +RISCV_FP_F_REG(). + +Reported-by: Andrew Jones +Signed-off-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Message-ID: <20231208183835.2411523-2-dbarboza@ventanamicro.com> +Signed-off-by: Alistair Francis +(cherry picked from commit 49c211ffca00fdf7c0c29072c224e88527a14838) +Signed-off-by: Michael Tokarev + +Upstream-Status: Backport [bbdcc89678daa5cb131ef22a6cd41a5f7f9dcea9] + +Signed-off-by: Chen Qi +--- + target/riscv/kvm/kvm-cpu.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c +index c1675158fe..2eef2be86a 100644 +--- a/target/riscv/kvm/kvm-cpu.c ++++ b/target/riscv/kvm/kvm-cpu.c +@@ -72,6 +72,11 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, + return id; + } + ++static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) ++{ ++ return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; ++} ++ + #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ + KVM_REG_RISCV_CORE_REG(name)) + +@@ -81,7 +86,7 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, + #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ + KVM_REG_RISCV_TIMER_REG(name)) + +-#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) ++#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) + + #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) + +@@ -586,7 +591,7 @@ static int kvm_riscv_get_regs_fp(CPUState *cs) + if (riscv_has_ext(env, RVF)) { + uint32_t reg; + for (i = 0; i < 32; i++) { +- ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); ++ ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); + if (ret) { + return ret; + } +@@ -620,7 +625,7 @@ static int kvm_riscv_put_regs_fp(CPUState *cs) + uint32_t reg; + for (i = 0; i < 32; i++) { + reg = env->fpr[i]; +- ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®); ++ ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); + if (ret) { + return ret; + } +-- +2.25.1 + diff --git a/meta/recipes-devtools/qemu/qemu/0002-target-riscv-kvm-change-KVM_REG_RISCV_FP_D-to-u64.patch b/meta/recipes-devtools/qemu/qemu/0002-target-riscv-kvm-change-KVM_REG_RISCV_FP_D-to-u64.patch new file mode 100644 index 0000000000..9480d3e0b5 --- /dev/null +++ b/meta/recipes-devtools/qemu/qemu/0002-target-riscv-kvm-change-KVM_REG_RISCV_FP_D-to-u64.patch @@ -0,0 +1,73 @@ +From 125b95d79e746cbab6b72683b3382dd372e38c61 Mon Sep 17 00:00:00 2001 +From: Daniel Henrique Barboza +Date: Fri, 8 Dec 2023 15:38:32 -0300 +Subject: [PATCH 2/3] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 + +KVM_REG_RISCV_FP_D regs are always u64 size. Using kvm_riscv_reg_id() in +RISCV_FP_D_REG() ends up encoding the wrong size if we're running with +TARGET_RISCV32. + +Create a new helper that returns a KVM ID with u64 size and use it with +RISCV_FP_D_REG(). + +Reported-by: Andrew Jones +Signed-off-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Message-ID: <20231208183835.2411523-3-dbarboza@ventanamicro.com> +Signed-off-by: Alistair Francis +(cherry picked from commit 450bd6618fda3d2e2ab02b2fce1c79efd5b66084) +Signed-off-by: Michael Tokarev + +Upstream-Status: Backport [125b95d79e746cbab6b72683b3382dd372e38c61] + +Signed-off-by: Chen Qi +--- + target/riscv/kvm/kvm-cpu.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c +index 2eef2be86a..82ed4455a5 100644 +--- a/target/riscv/kvm/kvm-cpu.c ++++ b/target/riscv/kvm/kvm-cpu.c +@@ -77,6 +77,11 @@ static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) + return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; + } + ++static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) ++{ ++ return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; ++} ++ + #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ + KVM_REG_RISCV_CORE_REG(name)) + +@@ -88,7 +93,7 @@ static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) + + #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) + +-#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) ++#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) + + #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ + do { \ +@@ -579,7 +584,7 @@ static int kvm_riscv_get_regs_fp(CPUState *cs) + if (riscv_has_ext(env, RVD)) { + uint64_t reg; + for (i = 0; i < 32; i++) { +- ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); ++ ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); + if (ret) { + return ret; + } +@@ -613,7 +618,7 @@ static int kvm_riscv_put_regs_fp(CPUState *cs) + uint64_t reg; + for (i = 0; i < 32; i++) { + reg = env->fpr[i]; +- ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); ++ ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); + if (ret) { + return ret; + } +-- +2.25.1 + diff --git a/meta/recipes-devtools/qemu/qemu/0003-target-riscv-kvm-change-timer-regs-size-to-u64.patch b/meta/recipes-devtools/qemu/qemu/0003-target-riscv-kvm-change-timer-regs-size-to-u64.patch new file mode 100644 index 0000000000..1ea1bcfe70 --- /dev/null +++ b/meta/recipes-devtools/qemu/qemu/0003-target-riscv-kvm-change-timer-regs-size-to-u64.patch @@ -0,0 +1,107 @@ +From cbae1080988e0f1af0fb4c816205f7647f6de16f Mon Sep 17 00:00:00 2001 +From: Daniel Henrique Barboza +Date: Fri, 8 Dec 2023 15:38:33 -0300 +Subject: [PATCH 3/3] target/riscv/kvm: change timer regs size to u64 + +KVM_REG_RISCV_TIMER regs are always u64 according to the KVM API, but at +this moment we'll return u32 regs if we're running a RISCV32 target. + +Use the kvm_riscv_reg_id_u64() helper in RISCV_TIMER_REG() to fix it. + +Reported-by: Andrew Jones +Signed-off-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Message-ID: <20231208183835.2411523-4-dbarboza@ventanamicro.com> +Signed-off-by: Alistair Francis +(cherry picked from commit 10f86d1b845087d14b58d65dd2a6e3411d1b6529) +Signed-off-by: Michael Tokarev + +Upstream-Status: Backport [cbae1080988e0f1af0fb4c816205f7647f6de16f] + +Signed-off-by: Chen Qi +--- + target/riscv/kvm/kvm-cpu.c | 26 +++++++++++++------------- + 1 file changed, 13 insertions(+), 13 deletions(-) + +diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c +index 82ed4455a5..ddbe820e10 100644 +--- a/target/riscv/kvm/kvm-cpu.c ++++ b/target/riscv/kvm/kvm-cpu.c +@@ -88,7 +88,7 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) + #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ + KVM_REG_RISCV_CSR_REG(name)) + +-#define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ ++#define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ + KVM_REG_RISCV_TIMER_REG(name)) + + #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) +@@ -111,17 +111,17 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) + } \ + } while (0) + +-#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ ++#define KVM_RISCV_GET_TIMER(cs, name, reg) \ + do { \ +- int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ ++ int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ + if (ret) { \ + abort(); \ + } \ + } while (0) + +-#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ ++#define KVM_RISCV_SET_TIMER(cs, name, reg) \ + do { \ +- int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ ++ int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ + if (ret) { \ + abort(); \ + } \ +@@ -649,10 +649,10 @@ static void kvm_riscv_get_regs_timer(CPUState *cs) + return; + } + +- KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); +- KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); +- KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); +- KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); ++ KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); ++ KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); ++ KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); ++ KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); + + env->kvm_timer_dirty = true; + } +@@ -666,8 +666,8 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) + return; + } + +- KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); +- KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); ++ KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); ++ KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); + + /* + * To set register of RISCV_TIMER_REG(state) will occur a error from KVM +@@ -676,7 +676,7 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) + * TODO If KVM changes, adapt here. + */ + if (env->kvm_timer_state) { +- KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); ++ KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); + } + + /* +@@ -685,7 +685,7 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) + * during the migration. + */ + if (migration_is_running(migrate_get_current()->state)) { +- KVM_RISCV_GET_TIMER(cs, env, frequency, reg); ++ KVM_RISCV_GET_TIMER(cs, frequency, reg); + if (reg != env->kvm_timer_frequency) { + error_report("Dst Hosts timer frequency != Src Hosts"); + } +-- +2.25.1 +